CN103064808A - Priority adjustable multiple-channel direct memory access (DMA) controller - Google Patents
Priority adjustable multiple-channel direct memory access (DMA) controller Download PDFInfo
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Abstract
本发明属于一种DMA控制器，具体公开一种优先级可调多通道DMA控制器，包括：数据输入通道数相等的数据缓冲存储及其控制模块和一组控制寄存器；用于所述数据缓冲存储及其控制模块通信的多路复用模块，该模块用于把数据缓冲存储及其控制模块中的信号和数据进行多路复用后传输到DMA引擎；DMA引擎根据各数据输入通道所配置的工作模式及预设优先级完成各种数据传输任务。该DMA控制器可以实现多数据输入通道共享一个DMA数据通道。
The invention belongs to a DMA controller, and specifically discloses a multi-channel DMA controller with adjustable priority, including: data buffer storage with equal numbers of data input channels, its control module and a group of control registers; used for the data buffer The multiplexing module for communication between the storage and its control module, which is used to multiplex the signals and data in the data buffer storage and its control module and then transmit them to the DMA engine; the DMA engine is configured according to each data input channel Complete various data transmission tasks with specific working modes and preset priorities. The DMA controller can share one DMA data channel with multiple data input channels.
Description
Technical field
The invention belongs to a kind of dma controller, be specifically related to the adjustable multi-channel DMA controller of a kind of priority.
Background technology
In data handling system and SoC chip take microprocessor (microprocessor unit, MPU) as main control equipment, data transfer adopts 3 kinds of modes usually.1) polling mode: MPU periodically detects the state from equipment, takes out data and write destination device from source device at reasonable time.When adopting this mode, a large amount of processor time will be taken, and data rate is subjected to the MPU restriction of instruction time.2) interrupt mode: in the time need to carrying out data transmission from equipment, send interrupt request to MPU, performing data transmission task after the MPU response.When adopting this mode, MPU needn't active inquiry from equipment state, saved the segment processor time, but transmission course is controlled by MPU still, does not improve data rate.3) direct memory access (DMA) (direct memory access, DMA) mode: DMA is a kind of mechanism of fast transfer of data, realize that by dma controller the application of .DMA can effectively alleviate the burden of processor, can greatly improve the efficient of data transmission, thereby improve system performance.
DMA is as a kind of machine-processed fine data transmission that has solved between peripheral hardware and the storer of fast transfer of data, still often very limited take microprocessor (microprocessor unit, MPU) as main control equipment DMA number of channels.Being difficult to each data channel for the high-speed multiple channel data acquisition system (DAS) distributes a DMA passage to be used for the storage data.
Summary of the invention
The object of the present invention is to provide the adjustable multi-channel DMA controller of a kind of priority, this dma controller can be realized most according to the shared DMA data channel of input channel.
Realize the technical scheme of the object of the invention: the adjustable multi-channel DMA controller of a kind of priority, it comprises:
A plurality of data input channels, the corresponding channel control register group of the input end of each data input channel, the corresponding data buffer-stored of the output terminal of each data input channel and control module thereof, the output terminal of data buffering storage and control module thereof is communicated by letter with multiplexing module, and the output terminal of multiplexing module is communicated by letter with the DMA engine;
Data buffering storage and control module thereof are used for the data that buffered data input channel real-time Transmission is come, and carry out data transmission and data flow con-trol to transmitting the data of coming;
The control register group is communicated by letter with described data buffering storage and control module thereof, is used for according to the pre-configured data of described control register the data transmission of described data buffering storage and control module thereof being controlled;
Multiplexing module is communicated by letter with the storage of described data buffering and control module thereof, is used for described data buffering stored and the signal of control module and data carry out being transferred to the DMA engine after multiplexed;
The DMA engine is finished various data transfer tasks according to mode of operation and pre-setting priority that each data input channel disposes.
Directly communicate by letter by the passage arbitration modules between described channel control register group and the DMA engine, the passage arbitration modules is selected the next passage that carries out data transmission according to the logical priority of data input, directly is transferred to the DMA engine.
Communicate by letter by the passage arbitration modules between described channel control register group and the multiplexing module, the passage arbitration modules is selected the next passage that carries out data transmission according to the logical priority of data inputs, and the data of this passage carry out being transferred to the DMA engine after multiplexed.
Described passage arbitration modules adopts the arbitration mechanism of priority and the combination of wheel phase inversion, and the passage arbitration modules is divided into several groups with a plurality of data channel, and every group has two passages, two passages wheel flow transmission in every group.
Described multiplexing module contains the second buffered memory module, and the second buffered memory module is used for the data of storage DMA data transmission, avoids the DMA data from overflow.
Store the chained list descriptor in the described DMA engine buffer, form and the control information of each the descriptor definition data to be transmitted frame in the chained list cooperate dma controller to finish data transfer task; Simultaneously, the chained list descriptor is dynamically adjusted Frame and buffer size in transmission course, reduces MPU to the participation of DMA transmission course.
Described DMA engine is provided with two host device interface, respectively is provided with one group of hardware handshaking signal on each host device interface, and every group of hardware handshaking signal comprises 2 signals: i.e. dma request signal and DMA answer signal; When need to initiate the DMA transmission from equipment the time, the dma request signal of corresponding host device interface is effective, start the DMA engine after the dma controller response request, behind a Frame end of transmission, dma controller sends answer signal, receive from equipment to make request signal reset after replying, finish the DMA transformation task one time.
Useful technique effect of the present invention: this dma controller can be realized most according to the shared DMA data channel of input channel.Each DMA channel module comprises respectively data buffering storage and control module and the one group of control register that equates with data input channel number, the priority that control register can the control channel transmission.Data input channel input data are stored in first in the buffer zone, and the priority timesharing of setting according to control register takies the DMA data channel and carries out data transmission.The present invention can realize that by the setting to passage configuration register and passage arbitration modules the wheel of fixed priority, different service distribution ratio turns the multiple priorities arbitration algorithms such as priority, has strengthened the versatility of dma controller.
Description of drawings
Fig. 1 is the block diagram of system of the adjustable multi-channel DMA controller of a kind of priority provided by the present invention;
Fig. 2 is a kind of synoptic diagram that utilizes the address mask device to produce loop buffer provided by the present invention;
Fig. 3 is the synoptic diagram of a kind of FIFO buffer circle provided by the present invention;
Fig. 4 is the synoptic diagram of a kind of chained list descriptor structure provided by the present invention.
Among the figure: 1. register file, 101. first passage register group, 102. second channel register group, 103. third channel register group, 104. four-way register group, 105. Five-channel register groups, 106. the 6th channel register groups, 107. the 7th channel register group, 108. the 8th channel register groups;
2. data input channel, 201. the first data input channel, 202. the second data input channel, 203. the 3rd data input channel, 204. the 4th data input channel, 205. the 5th data input channels, 206. the 6th data input channels, 207. the 7th data input channel, 208. the 8th data input channels;
3. the first data buffering is stored and control module, 301. the storage of first passage data buffering and control module, 302. the storage of second channel data buffering and control module, 303. the storage of third channel data buffering and control module, 304. the storage of four-way data buffering and control module, 305. the storage of Five-channel data buffering and control module, 306. the storage of the 6th channel data buffer and control module, 307. the storage of the 7th channel data buffer and control module, the storage of 308. the 8th channel data buffers and control module;
4. multiplexing module, 401. second data buffering memory modules;
5. the second host device interface, 6.DMA engine, 7. the first host device interface, 8. passage arbitration modules.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail.
The block diagram of system of the adjustable multi-channel DMA controller of a kind of priority provided by the present invention as shown in Figure 1.MPU can by the register group of instruction setting and internal memory unified addressing, finish the dynamic-configuration to adjustable multi-channel DMA controller.
As shown in Figure 1:
Register file 1 comprises eight register groups: namely comprise first passage register group 101, second channel register group 102, third channel register group 103, four-way register group 104, Five-channel register group 105, the 6th channel register group 106, the 7th channel register group 107, the 8th channel register group 108.
Data input channel 2 comprises eight data passages: the first data input channel 201, the second data input channel 202, the 3rd data input channel 203, the 4th data input channel 204, the 5th data input channel 205, the 6th data input channel 206, the 7th data input channel 207, the 8th data input channel 208.
Eight register groups in the register file 1 respectively with data input channel 2 in a tunneling traffic, that is: first passage register group 101 is communicated by letter with the first data input channel 201, second channel register group 102 is communicated by letter with the second data input channel 202, third channel register group 103 is communicated by letter with the 3rd data input channel 203, four-way register group 104 is communicated by letter with the 4th data input channel 204, Five-channel register group 105 is communicated by letter with the 5th data input channel 205, the 6th channel register group 106 is communicated by letter with the 6th data input channel 206, the 7th channel register group 107 is communicated by letter with the 7th data input channel 207, the 8th channel register group 108 and the 8th data input channel 208.
The storage of the first data buffering and control module 3 comprise eight data buffer-stored and control module: the storage of first passage data buffering and control module 301, the storage of second channel data buffering and control module 302, the storage of third channel data buffering and control module 303, the storage of four-way data buffering and control module 304, the storage of Five-channel data buffering and control module 305, the storage of the 6th channel data buffer and control module 306, the storage of the 7th channel data buffer and control module 307, the storage of the 8th channel data buffer and control module 308.
Eight modules of the storage of the first data buffering and control module 3 all adopt fifo memory buffer.
Each passage of data input channel 2 respectively with the first data buffering storage and control module 3 in a module communication, that is: the first data input channel 201 is communicated by letter with the storage of first passage data buffering and control module 301, the second data input channel 202 is communicated by letter with the storage of second channel data buffering and control module 302, the 3rd data input channel 203 is communicated by letter with the storage of third channel data buffering and control module 303, the 4th data input channel 204 is communicated by letter with the storage of four-way data buffering and control module 304, the 5th data input channel 205 is communicated by letter with the storage of Five-channel data buffering and control module 305, the 6th data input channel 206 is communicated by letter with the storage of the 6th channel data buffer and control module 306, the 7th data input channel 207 is communicated by letter with the storage of the 7th channel data buffer and control module 307, and the 8th data input channel 208 is communicated by letter with the storage of the 8th channel data buffer and control module 308.
Eight modules of the storage of the first data buffering and control module 3 are all communicated by letter with a multiplexing module 4, eight modules that comprise the second data buffering memory module 401, the first data bufferings storage and control module 3 in the multiplexing module 4 are all communicated by letter with the second data buffering memory module 401.Multiplexing module 4 adopts multiplexer.The second data buffering memory module 401 adopts annular fifo buffer memory.
Multiplexing module 4 is communicated by letter with DMA engine 6.Two bus interface of DMA engine 6 are connected with the second host device interface 5, the first host device interface 7 respectively.
Also directly communicate by letter by passage arbitration modules 8 between register file 1 and the DMA engine 6.Also directly communicate by letter by passage arbitration modules 8 between register file 1 and the multiplexing module 4.Passage arbitration modules 8 adopts the arbitrate state register.
The function of main modular is as follows:
(1) register file 1:
Register file 1 is communicated by letter with the storage of the first data buffering and control module 3 by data input channel 2, and register file 1 is used for according to the pre-configured data of register the DMA data transmission of the storage of the first data buffering and control module 3 being controlled.
The invention provides 8 DMA data input channels 201,202...203, each data input channel has an independently register group, and a plurality of register groups consist of a register file 1.The register group comprises state of a control register, source/destination address register, source/destination address pointer register, source/destination address mask register, transmission length register, chained list descriptor pointer register.The transmission course of data element is as follows: the storage space reading out data that 1. points to from source address; 2. these data being write the storage space that destination address points to. the data transmission procedure of each passage is the repetition of data element transmission course, after the multiplicity of this process reaches the value of transmitting in the length register, namely finished a complete DMA data frame transfer process.
Can finish setting to each channel source address, destination address, the transmission of data frame sign, mode of operation and priority by writing register.
(2) a plurality of data input channels 2:
Can set by register file 1 priority of channel module.The data of the passage input of transmitting deposit first the storage of the first data buffering and control module 3 in, can control the priority of data input channel 2 transmission according to register file 1 and carry out data transmission.
The storage of (3) first data bufferings and control module 3:
Be used for the in real time data of input of buffering, wait for that dma controller carries out data transmission.
It comprises multichannel buffered memory module and buffering storage control module: the multichannel buffered memory module is used for the data storage of data input channel; The buffer-stored control module is used for control the data from outside DMA request module is write the storage of the first data buffering and control module 3, and the data in the first data buffering storage and control module 3 are when reaching certain capacity, produce written request signal, and written request signal is transferred to the bus interface of DMA engine 6 through multiplexing module 4; Also be used for controlling delivering to the DMA request module behind the data reading of the storage of the first data buffering and control module 3, and the data in the first data buffering storage and control module 3 are when reaching certain capacity, produce reading request signal, and reading request signal is sent to the bus interface of DMA engine 6 through described multiplexing module 4.
The first buffered memory module 3 adopts fifo memory buffers, deposits in the middle of the fifo memory buffer when the data input channel is continual when inputting data simultaneously to dma module with data.Application DMA transmission when the input data arrive some, the sequencing of the priority arbitration determination data transmission by passage arbitration modules 8.
(4) multiplexing module 4:
All modules of the storage of multiplexing module 4 and the first data buffering and control module 3 are all communicated by letter, and are used for a plurality of channel data buffers are stored and the signal of control module and data carry out being transferred to after multiplexed the bus interface of DMA engine 6.
(5) second buffered memory module 401:
The second buffered memory module 401 of multiplexing module 4 inside is all communicated by letter with all modules of the storage of the first data buffering and control module 3.
The second buffered memory module 401 adopts annular FIFO storer, is used for the data of storage DMA data transmission, avoids the DMA data from overflow.
For making the dma controller run time address not exceed DMA buffer storage space scope, utilize in the present invention the address mask device to produce loop buffer, as shown in Figure 2: source address or destination address register can be set to " constant ", automatic " adding 1 ", " subtracting 1 " or " value of indexing ", revised address enters selector switch, only having the corresponding position of address mask register is that 1 address bit can be made amendment, other position remains unchanged, and amended address will be written back into address register.For example, the buffer zone start address is 0x80, and the address mask register is set to 0x7f, and then the buffer zone address scope is that 0x80 to 0xff. has realized by this method the DMA buffer circle and circulates without expense, simplified the design of driver and hardware, but the capacity limit of buffer zone is 2 n side.
Fig. 3 is the corresponding FIFO type of dma controller buffer circle synoptic diagram.When design DMA buffer zone, need consider impact and data transmission time-delay on the MPU load: buffer zone is crossed senior general and is caused transmission delay to increase; Buffer zone is crossed the young pathbreaker makes interruption too frequent, cause the MPU Efficiency Decreasing. for onesize buffer zone, the sub-number of buffer of dividing is crossed the major general and is increased transmission delay, and sub-number of buffer is crossed at most can reduce the buffer zone service efficiency. during practical application, need make as the case may be balance.
(5) the DMA engine 6:
DMA engine 6 is nucleus modules of DMA, can finish various data transfer tasks according to mode of operation and pre-setting priority that each data input channel 2 disposes.
Priority is adjustable, and multi-channel DMA controller chained list descriptor is stored in the impact damper of DMA engine 6, can dynamically adjust Frame and buffer size in transmission course, reduces MPU to the participation of DMA transmission course.Form and the control information of each the descriptor definition data to be transmitted frame in the chained list cooperate dma controller to finish data transfer task.
The chained list descriptor structure is seen Fig. 4: descriptor is comprised of 4 32 word, comprise respectively control bit/transmission length, source address, destination address, pointing to the pointer of next descriptor. control bit comprises model selection position and equipment interface selection position. the descriptor pointer consists of single-track link table with each descriptor, the linked list head node is determined by chained list descriptor pointer register, tail node is determined by the chained list stop bit (EOL) in the descriptor. when adopting chained list descriptor mode the transmission of data, at first need the chained list descriptor pointer register assignment to transmission channel, the descriptor enable bit that arranges in the control register is effective, and starts DMA engine 6.DMA engine 6 will take out descriptor from the buffer address of the pointed of chained list descriptor, data in the descriptor are respectively charged into control register, source address register, destination address register and chained list descriptor pointer register. and after this, the DMA engine will begin the data transfer process.
Behind the transformation task of finishing a Frame, DMA will according to the value in the chained list descriptor pointer register, take out next descriptor automatically from the corresponding address of impact damper.If the EOL position in the descriptor is 1, then the DMA engine quits work, and sends interrupt request singal to MPU. in some application, data transmission is not to carry out according to linked list order fully.For example, in congested ethernet node occurs, if several IP grouping arrives router simultaneously, and expect to transmit through same output port, if this situation continues for some time, buffer memory is depleted, and router only has the low grouping of loss priority.At this moment, when the MAC module is sent the request of carrying out data transmission to dma controller, should abandon the processing to current descriptor, force to take out the next descriptor in the chained list.Realized this function by increase input signal in dma controller in the hardware handshaking pattern, if signal effectively also continued for 2 clock period, current descriptor will lose efficacy.After the DMA engine is finished the transmission of current data frame, next descriptor will be forced to take out in the chained list, and data wherein are written into corresponding registers.In the data transmission procedure, need the data of a specific region in the protection internal memory to be uncovered and when not knowing this area size, this function also has practical use.
(6) the passage arbitration modules 8:
Because hyperchannel 201,202...208 may initiate request at one time, when a plurality of data input channels are initiated the DMA request simultaneously, need to carry out the passage arbitration.Passage arbitration modules 8 can be selected the next passage that carries out data transmission according to the logical priority of each data input in the data input channel 2.
When directly communicate by letter by passage arbitration modules 8 between register file 1 and the DMA engine 6, passage arbitration modules 8 is carried out the passage of data transmission according to the logical priority selection next one of data input, directly is transferred to DMA engine 6.
When communicating by letter by passage arbitration modules 8 between register file 1 and the multiplexing module 4, passage arbitration modules 8 is selected the next passage that carries out data transmission according to the logical priority of data inputs, and the data of this passage carry out being transferred to DMA engine 6 after multiplexed.
Passage arbitration modules 8 has adopted the arbitration mechanism of priority and the combination of wheel phase inversion.Passage arbitration modules 8 is divided into 4 groups (I, II, III, IV) with eight passages, and every group has 2 passages, contains which 2 passage and can put register by 24 passage assembly and be configured.The passage group has 4 kinds of priority orders (A, B, C, D).Passage arbitration modules 8 is divided into 10 arbitrate states with system, and the corresponding a kind of priority orders of each state can arrange by 20 arbitrate state register.2 passages in every group are then taken turns flow transmission, suppose that the I group comprises passage 1 and passage 4, if passage 1 transmitted when this I group was obtained the authorization, then next I organizes when obtaining the authorization prioritised transmission passage 4.
(7) bus interface, i.e. equipment interface: the interface between dma controller and storer and the IO equipment is provided, adopts the design that meets the AMBA2.0 bus specification.Dma controller has 2 host device interface, and namely the second host device interface 5, the first host device interface 7 are used at 2 storage unit or IO equipment room swap data; One from equipment interface, and the data path of MPU access register heap is provided.
When dma controller is in running order, by the data in host device interface 5, the 7 playback buffer districts or data are write the buffer circle of the second buffered memory module 401.For realizing that processor and dma controller to the parallel work-flow of buffer zone, generally can adopt multi cache mechanism, buffer zone is divided into some sub-buffer zones.Be valid data for making the data of from buffer zone, reading, or write data untreated data of overriding processor not in the buffer zone, can be processor be read (writing) operation at every turn to a sub-buffer zone after, to purpose (source) address register and the transmission length register again assignment of dma controller.Make the design of driver more flexible, DMA device processed is realized circle queue by address pointer register is set in buffer zone.The each value of upgrading in rear and the address pointer register of value in the DMA address register compares, as equating that then the DMA engine quits work, processor is finished the value in the scheduler pointer register after the read-write of a Frame, and this moment, the DMA engine just can restart.
Multi-channel DMA controller hardware handshaking pattern that priority is adjustable: respectively designed one group of hardware handshaking signal in 2 host device interface 5,7 of dma controller, every group comprises 2 signals, i.e. DMA request and DMA reply.When need to initiate the DMA transmission from equipment the time, the dma request signal of corresponding host device interface is effective, start DMA engine 6 after the dma controller response request, behind a Frame (size is pre-if determined by the chained list descriptor by MPU) end of transmission, dma controller sends answer signal, receive from equipment to make request signal reset after replying, finish the DMA transformation task one time.The hardware handshaking pattern for carry out DMA transmission from equipment, have slow devices the time be particularly useful.
Priority is adjustable multi-channel DMA controller two-level pipeline: 2 host device interface 5 of dma controller, 7 each corresponding one group of data address bus, data transmission can be carried out one group of bus, also can carry out between 2 groups of buses.When one group of bus is transmitted, data need be carried out buffer memory, bus adopts the time division multiplex strategy, namely in address path, source address and destination address interval one-period alternately appear in the data transfer path on address bus, the DMA data bus is bidirectional bus, and its reading data from this dma controller is put into temporary register, this data communication device is crossed same bus in next cycle and is write in this this dma controller.Therefore, utilize one group of bus transfer data, data of every biography are near to take two clock period less.When dma controller during the transmission of data, is to improve data rate between two groups of buses, data can be without the buffer memory location of going directly to destination in transmission course.DMA engine 6 carries out read-write operation by read bus and write bus to this dma controller, and read-write motion can be carried out simultaneously, thereby has consisted of a two-level pipeline.
The data input channel 2 of the adjustable multi-channel DMA controller of a kind of priority provided by the present invention not only is confined to described eight passages 201 of above-described embodiment, 202...208, data input channel 2 can be any a plurality of passages, each data input channel is a corresponding data buffer-stored and control module and one group of control register group respectively, and is most according to the shared DMA engine of input channel.
The above has done detailed description to the present invention in conjunction with the accompanying drawings and embodiments, but the present invention is not limited to above-described embodiment, in the ken that those of ordinary skills possess, can also make various variations under the prerequisite that does not break away from aim of the present invention.The content that the present invention is not described in detail all can adopt prior art.
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