CN103064807A - Multi-channel direct memory access controller - Google Patents
Multi-channel direct memory access controller Download PDFInfo
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Abstract
The invention discloses a multi-channel direct memory access (DMA) controller. A plurality of DMA channels and a data transmission unit are arranged in the DMA controller, the control operation and the data transportation work of data transmission are separated, the control operation of DMA data transmission is processed by the plurality of DMA channels, each DMA channel performs buffer descriptor (BD) management operation and operation for generating a transmission instruction, one data transmission unit is used for processing total data transportation work of DMA data transmission, the data transmission unit performs arbitration on transmission instructions from the plurality of DMA channels, each transmission instruction is sequentially executed according to a ranking sequence obtained by the arbitration, data are transmitted between a central processing unit (CPU) internal memory and an external cache, a flow process of the control operation of the data transmission can be formed in the DMA channels, a flow process of the data transportation work of data transmission is formed in the data transmission unit, the data transmission speed of the DMA controller can be increased, and the DMA controller is suitable for an application scene of high speed data transmission.
Description
Technical Field
The present invention relates to the field of data communications, and in particular, to a multi-channel direct memory access controller.
Background
Direct Memory Access (DMA) is a high-speed data transmission operation, allowing data to be directly read and written between an external device and a Memory, the whole data transmission operation is performed under the control of a DMA controller, and a Central Processing Unit (CPU) does not need to intervene in the transmission process, and can perform other work, thereby greatly improving the operating efficiency of the CPU.
Fig. 1a is a block diagram of a typical DMA system in the prior art. CPU, DMA controller, on-chip and off-chip memory (including on-chip RAM, RAM controller, on-chip Flash, Flash controller, off-chip memory and memory controller) and high-speed I/O are connected to the high-speed bus, and various low-speed peripherals (including low-speed peripheral 1, low-speed peripheral 2 and low-speed peripheral 3) are connected to the low-speed bus and connected to the high-speed bus through a bus bridge. If the device on the bus needs to carry out DMA transmission, a request is sent to the DMA controller, and after the DMA controller obtains the bus use right, the DMA controller controls the data transmission in the CPU memory and other devices and returns the bus use right after the transmission is finished. And a CPU is not needed in the DMA transmission process, so that the extra expense of the CPU is saved.
Chinese patent application No. 200910080751 (publication No. 101504633) discloses a multi-channel DMA controller, which includes a plurality of DMA channel modules and a multiplexing module, each DMA channel module includes a data buffer and control module thereof and a set of control registers, and the data buffer and control modules thereof of all channels are connected to the multiplexing module. The DMA controller can reduce the overhead of a bus arbitration block and a storage unit on a system on a chip to a certain extent and improve the reusability of the system.
However, in the technical solution of the chinese patent, each DMA channel performs data control and data transmission, specifically, the DMA channel generates a read data request for data to be read, and after sending the read data request to the CPU memory, the DMA channel must wait until the CPU memory returns the requested read data to perform the next operation of generating the read data request, but there is usually a time delay for the CPU memory to return data, which causes a problem of slow data transmission speed, and thus the DMA controller is not suitable for an application scenario of high-speed data transmission.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a multi-channel DMA controller, so as to solve the problems that the DMA controller in the prior art is slow in transmission speed and is not suitable for a high-speed data transmission application scenario.
The technical scheme of the embodiment of the invention is as follows:
a DMA controller comprising: a plurality of DMA channels and data transmission units; the DMA channel is used for reading a BD (Buffer Descriptor) from a CPU (central processing unit) memory after receiving a BD update message from the CPU, and generating a transmission instruction according to the BD and the data storage condition in an external cache; and the data transmission unit is used for arbitrating the transmission instructions from the plurality of DMA channels, sequentially executing each transmission instruction according to the sequencing sequence obtained by arbitration, and transmitting data between the CPU memory and the peripheral cache.
The embodiment of the invention separates the control operation of data transmission and the data carrying work of data transmission by arranging a plurality of DMA channels and a data transmission unit in a DMA controller, namely the plurality of DMA channels process the control operation of DMA data transmission, concretely, each DMA channel carries out BD management operation and generates transmission instruction operation, one data transmission unit processes all the data carrying work of DMA data transmission, concretely, the data transmission unit arbitrates the transmission instructions from the plurality of DMA channels, and executes the transmission instructions in sequence according to the sequencing sequence obtained by arbitration to transmit data between a CPU memory and an external cache, thus, the data control operation executed by the data transmission unit does not depend on the data carrying operation executed by the data transmission unit, and can form the pipelining of the control operation of data transmission on the side of the DMA channels, the data transmission unit sequentially processes transmission instructions from the plurality of DMA channels, and the data transmission unit side forms the flow operation of data carrying operation of data transmission, so that the data transmission speed of the DMA controller can be improved, and the DMA controller can be suitable for application scenes of high-speed data transmission.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
FIG. 1a is a block diagram of a typical DMA system of the prior art;
FIG. 1b is a block diagram of a multi-channel DMA controller according to an embodiment of the present invention;
FIG. 1c is a flow chart of the operation of the multi-channel DMA controller shown in FIG. 1 b;
FIG. 2 is a block diagram of a preferred architecture of the multi-channel DMA controller shown in FIG. 1 b;
FIG. 3 is a block diagram of a preferred architecture of the multi-channel DMA controller shown in FIG. 2;
FIG. 4 is a flowchart of the operation of the downstream instruction generation module of FIG. 3;
FIG. 5 is a flowchart of the processing operation of the read data module in FIG. 3 on downstream data;
FIG. 6 is a flowchart of the operation of the downstream write back module of FIG. 3;
FIG. 7 is a block diagram of another preferred architecture of the multi-channel DMA controller shown in FIG. 2;
FIG. 8 is a flowchart of the operation of the upbound instruction generation module of FIG. 7;
FIG. 9 is a flowchart of the processing of upstream data by the write data module of FIG. 7;
FIG. 10 is a flowchart of the operation of the upstream write back module of FIG. 7.
Detailed Description
The embodiments of the present invention will be described in conjunction with the accompanying drawings, and it should be understood that the embodiments described herein are only for the purpose of illustrating and explaining the present invention, and are not intended to limit the present invention.
The embodiment of the invention provides a multi-channel DMA controller aiming at the problems that the DMA controller in the prior art is low in data transmission speed and is not suitable for application scenes of high-speed data transmission, and aims to solve the problems. The embodiment of the invention separates the control operation of DMA data transmission from the data handling work, several DMA channels and data transmission units are set in the DMA controller, the DMA channels process the control operation of DMA data transmission, that is, a transfer instruction indicating how to perform data transfer is generated, a data transfer job of DMA data transfer is processed by the data transfer unit, namely, specific data transfer operation is carried out according to the transmission instruction, the control operation of the DMA channel is independent of the data transfer work of the data transfer unit, the flow operation of the control operation can be formed at the DMA channel side, the data transfer unit processes the transmission instructions from a plurality of DMA channels in sequence, the flow process of data carrying operation is formed on the data transmission unit side, so that the data transmission speed of the DMA controller can be improved, and the method can be applied to the application scene of high-speed data transmission.
The following describes in detail a multi-channel DMA controller provided by an embodiment of the present invention.
Fig. 1b shows a block diagram of a multi-channel DMA controller according to an embodiment of the present invention, which includes several DMA channels 11 and a data transmission unit 12.
The DMA channel 11 is used for reading the BD from the CPU memory after receiving the BD updating message from the CPU, and generating a transmission instruction according to the BD and the data storage condition in the peripheral cache;
and the data transmission unit 12 is connected to the DMA channels 11 and is configured to arbitrate the transmission instructions from the DMA channels, sequentially execute each transmission instruction according to the ordering sequence obtained by arbitration, and transmit data between the CPU memory and the peripheral cache.
The work flow diagram of the multi-channel DMA controller shown in fig. 1c, as shown in fig. 1c, comprises:
102, the data transmission unit 12 receives transmission instructions from each DMA channel 11, and arbitrates the received transmission instructions to obtain a sequence of the transmission instructions;
Through the multi-channel DMA controller shown in FIG. 1b and the operation principle shown in FIG. 1c, the control operation of DMA data transmission and the data carrying operation of data transmission can be separated, that is, the control operation of data transmission is processed by a plurality of DMA channels, the data carrying operation of DMA data transmission is processed by the data transmission unit, the control operation of DMA channels is independent of the data carrying operation of the data transmission unit, and the data transmission unit arbitrates the transmission instructions from the plurality of DMA channels, and the data carrying operations indicated by the transmission instructions are executed in sequence according to the ordering sequence obtained by arbitration, the DMA channels do not need to wait for the next control operation after the data carrying operation of the data transmission unit is finished, the flow operation of control operation can be formed on the DMA channel side, and the flow operation of data carrying operation can be formed on the data transmission unit side, and then can improve DMA controller's data transmission speed, can be applicable to the application scene of high-speed data transmission.
Before explaining the operation of the apparatus shown in fig. 1b in detail, the BD will be explained.
The BD is a data structure of control information for describing data read/write operations, a plurality of BDs occupy a continuous piece of storage space in the CPU memory, and the structure of the BD is shown in table 1, and includes a data address, a data length, an indication (Sop) of whether a data piece is a beginning part of a packet, an indication (Eop) of whether a data piece is an ending part of a packet, an error information indication (Err), a control right information indication (Owner), and an indication (Valid) of whether a BD is Valid.
TABLE 1
| Data address | Data length | SOP | EOP | Err | Owner | valid |
Before the CPU gives the bus control right to the multi-channel DMA controller, the address and the data length of data to be read are respectively written into a data address field and a data length field of the BD, an Owner field is rewritten into information representing the multi-channel DMA controller, then a BD updating message is sent to the multi-channel DMA controller, after the multi-channel DMA controller receives the BD updating message, the BD is read from a CPU memory, and the bus control right is judged to belong to the multi-channel DMA controller according to the information in the Owner field in the BD, so that the data can be read from the CPU memory according to the information in the data address field and the data length field in the BD. When the multichannel DMA controller writes data into the CPU memory, the data is written into the CPU memory according to the information in the data address field of the BD, the data length of the stored data is written into the data length field of the BD, the Owner field is rewritten into the information representing the CPU, the rewritten BD is sent to the CPU memory, and the CPU learns the bus control right to return to the CPU again by monitoring the information of the Owner field of the BD newly stored in the CPU memory.
Specifically, the DMA channel 11 is configured to process a control operation of downlink data and a control operation of uplink data of DMA data transmission, where the downlink data is data read from and written into the CPU memory and the uplink data is data read from and written into the CPU memory, and accordingly, the transmission instruction is also divided into a read instruction and a write instruction, and the data transmission unit 12 performs a data transfer operation on the downlink data according to the read instruction and performs a data transfer operation on the uplink data according to the write instruction.
Fig. 2 shows a block diagram of a preferred structure of the multi-channel DMA controller shown in fig. 1b, wherein the DMA channel 11 specifically includes a downstream channel 111 and an upstream channel 112, and the data transmission unit 12 includes a read data module 121 and a write data module 122.
The downlink channel 111 is used for reading the BD from the CPU memory after receiving the BD updating message from the CPU, and generating a reading instruction according to the read data length information in the read BD and the data size of the received data stored in the peripheral cache;
and the data reading module 121 is connected to the downlink channels 111 of the DMA channels 11, and is configured to arbitrate the read instructions from the downlink channels 111 of the DMA channels 11, sequentially read corresponding data from the CPU memory according to each read instruction according to the ordering sequence obtained by the arbitration, and send the read data to the peripheral cache.
The uplink channel 112 is configured to read a BD from a CPU memory after receiving a BD update message from the CPU, and generate a write instruction according to the data size of data to be sent stored in the peripheral cache and address information of data to be written in the read BD;
and the data writing module 122 is connected to the uplink channels 112 of the DMA channels 11, and configured to arbitrate the write instructions from the uplink channels 112 of the DMA channels, sequentially read corresponding data from the peripheral cache according to each write instruction according to a sorting sequence obtained by the arbitration, and send the read data to the CPU memory.
By arranging the uplink channel and the downlink channel in the DMA channel and arranging the read data module and the write data module in the data transmission unit, the uplink data processing and the downlink data processing can be distinguished, and the control operation and the data carrying operation of data transmission are distinguished for both downlink data and uplink data, so that the flow operation of the control operation of the uplink data and the downlink data can be effectively formed on the DMA channel side respectively, and the flow operation of the data carrying operation of the uplink data and the downlink data can be formed on the data transmission unit side respectively, further, the data transmission speed of the DMA controller can be improved, and the DMA controller can be suitable for application scenes of high-speed data transmission.
Moreover, because the corresponding functional units are respectively set according to the downlink data and the uplink data in the embodiment of the present invention, the DMA controller provided by the embodiment of the present invention has good tailorability, that is, according to different application scenarios, when only the DMA controller is required to process the downlink data, only the downlink channel may be set in the DMA channel, and the read data module may be set in the data transmission unit, when only the DMA controller is required to process the uplink data, only the uplink channel may be set in the DMA channel, and the write data module may be set in the data transmission unit, and when the DMA controller is required to process the downlink data and the uplink data, the DMA controller as shown in fig. 2 may be set.
The processing of the downstream data and the upstream data by the multi-channel DMA controller shown in fig. 2 will be described in detail below.
(I) Downlink data processing
FIG. 3 is a block diagram of a preferred architecture of the multi-channel DMA controller of FIG. 2, comprising: downstream channel 111 and read data module 121, downstream channel 111 includes: a downlink reading BD module 1111, a downlink instruction generating module 1112 and a downlink write-back module 1113.
1. And the downlink BD reading module 1111 is configured to read a plurality of BDs from the CPU memory after receiving the BD update message from the CPU, and store the plurality of BDs that are read.
Specifically, the downlink BD reading module 1111, after receiving the BD update message from the CPU, sends a downlink BD reading request to the CPU memory, where the downlink BD reading request carries the number of BDs requested to be read, where the number of BDs requested to be read is: the number of BDs with the smallest number among the number of readable BDs indicated in the BD update message from the CPU, the number of BDs indicated by the current BD pointer to the end of the BD ring, and the preset number of read BDs is different according to the application scenario, and thus, it can be seen that the number of BDs requested to be read at each time is variable, and may be one or multiple; and receiving a plurality of BD from the CPU memory according to the downlink BD reading request, and storing the plurality of BD received.
2. A downlink instruction generating module 1112, configured to generate a read instruction according to the read data length information in the BD read by the downlink BD reading module 1111 and the data size of the received data stored in the peripheral cache;
specifically, the downlink instruction generating module 1112 performs the following operations: reading current BD operation, judging operation, generating read instruction operation and sending the read instruction operation; wherein,
(1) the reading of the current BD operation includes: in the current time slice, when the downlink instruction generating module 1112 has a free storage space, the downlink instruction generating module 1112 obtains a BD from the downlink BD reading module 1111 as a current BD; when there is no free storage space in the downlink instruction generating module 1112, the downlink instruction generating module 1112 continues to wait until there is a free storage space, and acquires a BD from the downlink BD reading module 1111 as a current BD;
(2) and the judging operation comprises: judging whether a comparison condition is satisfied, wherein the comparison condition is as follows: comparing the data length indicated by the read data length information in the current BD with the sum of the data lengths indicated by the read data length information in each BD stored in the downlink instruction generating module 1112 and corresponding to the generated read instruction, to determine whether the sum is smaller than the size of the free storage space in the peripheral cache corresponding to the downlink channel of the DMA channel, and if the comparison condition is satisfied, executing the operation of generating the read instruction, otherwise, continuing to wait until the comparison condition is satisfied, that is, waiting for the data in the peripheral cache to be read out, and releasing the storage space in the peripheral cache to satisfy the comparison condition;
(3) and generating a read instruction operation comprises: generating a reading instruction corresponding to the current BD, wherein the reading instruction carries the length information of the reading data in the current BD and the address information of the reading data in the current BD; and, keep the present BD, preferably, can adopt the first-in first-out queue to keep the BD that has already produced the read command correspondingly;
(4) issue read command operation: the generated read command corresponding to the current BD is sent to the read data module 121.
3. A data reading module 121, connected to the downlink instruction generating module 1112 of each downlink channel 111, configured to, for a current read instruction in the sorting order obtained by arbitration, read data of a corresponding length from a storage space of a corresponding address in the CPU memory according to address information and read data length information in the current read instruction, and send the read data to a storage space corresponding to a DMA channel that sends the current read instruction in the peripheral cache;
specifically, the read data module 121 arbitrates the read instructions from the downlink channels 111 of the DMA channels 11, for example, according to a Round Robin (Round Robin) scheduling principle, and sends a read data request to the CPU memory for the current read instruction in the obtained arbitration sorting sequence according to the address information and the read data length information in the current read instruction, where the read data request includes the address information and the read data length information in the current read instruction; receiving a data packet aiming at a read data request from a CPU memory, and sending the received data to a storage space corresponding to a DMA channel for sending a current read instruction in a peripheral cache;
when polling the current read instruction, the read data module 121 feeds back a read response to the downstream channel of the DMA channel that sends the current read instruction (i.e., the downstream instruction generating module 1112 of the downstream channel 111); after reading out the data from the CPU memory and sending the data to the peripheral cache, feeding back a read completion response to the downlink channel of the DMA channel that sends the current read instruction (i.e., the downlink instruction generating module 1112 of the downlink channel 111);
accordingly, the downlink instruction generating module 1112 is further configured to: after receiving the read response from the read data module 121, the current BD is saved; after receiving the read completion response from the read data module 121, one BD out of the BDs stored in the downlink instruction generating module 1112 is sent to the downlink write-back module 1113; preferably, as described above, the downlink instruction generating module 1112 stores BDs that have generated corresponding read instructions in a first-in-first-out queue, where a BD is fetched from the head of the first-in-first-out queue and sent to the downlink write-back module 1113.
4. A downstream write-back module 1113 configured to: the control right information in the received BD is rewritten to the CPU, and the rewritten BD is transmitted to the CPU memory. Specifically, the downstream write-back module 1113 stores the rewritten BD, and counts a predetermined write-back period when it is determined that the rewritten BD is stored in the downstream write-back module 1113; and in a timing period, when the number of the stored rewritten BD is larger than or equal to the preset number, taking the preset number of the rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory, and when the number of the stored rewritten BD is smaller than the preset number, when the timing is up, taking the stored rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory.
Fig. 4 shows a work flow chart of the downlink instruction generating module 1112 in fig. 3, that is, fig. 4 shows an operating principle of a control operation of downlink channel for downlink data transmission, which includes the following processing procedures:
specifically, when it is determined that the comparison condition is satisfied, that is, the sum of the data length indicated by the read data length information in the current BD and the data length indicated by the read data length information in each BD corresponding to the generated read instruction stored in the downlink instruction generating module 1112 is smaller than the size of the free storage space in the peripheral cache corresponding to the downlink channel of the DMA channel, the read instruction corresponding to the current BD is generated, the read instruction carries the read data length information in the current BD and the address information of the read data in the current BD, and the process proceeds to step 404;
if the comparison condition is not satisfied, if the sum of the data length indicated by the read data length information in the current BD and the data length indicated by the read data length information in each BD corresponding to the generated read instruction, which is stored in the downlink instruction generation module 1112, is greater than or equal to the size of the free storage space in the storage space corresponding to the downlink channel of the DMA channel in the peripheral cache, the process returns to step 403 until the comparison condition is satisfied;
in the comparison conditions, it is necessary to judge: the reason why the sum of the data length indicated by the read data length information in the current BD and the data length indicated by the read data length information in each BD corresponding to the generated read command stored in the downlink command generating module 1112 is compared with the size of the free storage space in the storage space corresponding to the downlink channel of the DMA channel in the peripheral cache is that: as described in step 405 below, after polling a read instruction, the read data module 121 feeds back a read response to the downlink instruction generating module 1112 that sends the read instruction, and at this time, the read data module 121 does not read data from the CPU memory, because it takes a certain time for the read data module 121 to wait for the CPU memory to return data, when the read data module 121 sends the read response to the downlink instruction generating module 1112, the data indicated by the read instruction corresponding to the read response in the downlink instruction generating module 1112 is not actually read, and at this time, the downlink instruction generating module 1112 should store the BD corresponding to the read response, that is, the BD that has generated the read instruction correspondingly is stored; therefore, when the downlink instruction generating module 1112 generates the read instruction, it is determined whether the length of the data to be transported is smaller than the size of the free storage space in the peripheral cache corresponding to the downlink channel of the DMA channel, and the length of the data to be transported includes the sum of the length of the read data in the current BD and the length of the read data in each BD that has generated the read instruction;
Fig. 5 shows a flowchart of processing operation of the read data module 121 in fig. 3 on the downstream data, that is, fig. 5 shows an operation principle diagram of the read data module 121 carrying the downstream data, which includes the following processing steps:
In the above processing procedure, the downlink BD reading module 1111 reads a plurality of BDs from the CPU memory in batch and stores the read BDs, so that the downlink instruction generating module 1112 takes out the BDs one by one and generates a read instruction according to the BDs, so that the data reading module 121 performs data handling according to the read instruction; moreover, the downlink instruction generating module 1112 stores the BD corresponding to the read response according to the read response fed back by the read data module 121, and then generates the read instruction according to the next BD, so that the operation of generating the read instruction performed by the downlink instruction generating module 1112 does not depend on whether the read data module 121 reads data from the CPU memory, and a pipeline operation of controlling the downlink data can be formed; the data reading module 121 arbitrates the read instructions from the downlink channels of the plurality of DMA channels, and performs data carrying operations according to the arbitrated sequencing order and the read instructions in sequence, so as to form a line operation of data carrying operations on downlink data; therefore, the transmission speed of the downlink DMA data transmission can be improved, and the method can be suitable for application scenes of high-speed downlink data transmission.
On the basis of the working principle of the downlink data transmission, in an application scenario adopting a BD ring, the DMA data transmission further includes a processing procedure of downlink BD write-back.
Here, the structure of the BD ring and its operation will be described. The BD ring is an annular structure formed by a plurality of BDs connected end to end, each BD structure can be as shown in table 1 above, the BD ring occupies a continuous storage space in the CPU memory, after the downlink BD reading module 1111 reads a plurality of BDs from the CPU memory, the downlink instruction generating module 1112 sequentially generates read instructions according to the BDs, after the data reading module 121 reads data, the downlink DMA channel 111 should rewrite the BDs, rewrite an Owner field in the BD into information representing the CPU, and then send the rewritten BDs back to the CPU memory, so that the CPU monitors the change of the bus control right.
Fig. 6 shows a work flow chart of the downstream write-back module 1113 in fig. 3, that is, fig. 6 shows the working principle of BD write-back on downstream data, which includes the following processes:
specifically, the downlink write-back module 1113 sends the rewritten BD according to a timing mechanism; the downlink write-back module 1113 rewrites the control right information in the received BD into a CPU and stores the rewritten BD; the downlink write-back module 1113 counts a predetermined write-back period when judging that the self storage space stores the rewritten BD; and in a timing period, under the condition that the number of the stored rewritten BD is greater than or equal to the preset number, taking the preset number of the rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory, under the condition that the number of the stored rewritten BD is less than the preset number, under the condition that the timing is up, taking the stored rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory.
Through the above processing procedure, the downlink write-back module 1113 can write back BDs in batch, thereby reducing the number of times of writing back BDs and reducing the bus bandwidth occupied by writing back BDs, and thus improving the DMA data transmission speed. Furthermore, a timing mechanism is introduced to transmit the rewritten BDs to the CPU memory, and the predetermined number of rewritten BDs can be transmitted to the CPU memory in time when the number of rewritten BDs is greater than or equal to the predetermined number, thereby avoiding BD congestion or BD loss caused when the number of rewritten BDs in the downstream channel 111 increases excessively instantaneously, and when the number of rewritten BDs is smaller than the predetermined number, the rewritten BDs are transmitted to the CPU memory after timing, and avoiding a problem that the time for the CPU to monitor the BD waiting for write-back is too long because the rewritten BDs cannot be returned to the CPU when the number of rewritten BDs is smaller than the predetermined number for a long time, and enabling the CPU to monitor the change of the bus control right in time.
(II) uplink data processing
FIG. 7 is a block diagram of a preferred architecture of the multi-channel DMA controller of FIG. 2, comprising: an upstream channel 112 and a write data module 122, the upstream channel 112 comprising: an uplink reading BD module 1121, an uplink command generating module 1122, and an uplink write-back module 1123.
An uplink BD reading module 1121 configured to, after receiving a BD update message from the CPU, read a plurality of BDs from the CPU memory and store the read BDs; specifically, the uplink BD reading module 1121 sends an uplink BD reading request to the CPU memory, where the uplink BD reading request carries the number of BDs requested to be read; receiving a plurality of BD (disk drives) aiming at the uplink BD reading request from a CPU (Central processing Unit) memory;
an uplink instruction generating module 1122, configured to generate the write instruction according to the data size of the data to be sent stored in the peripheral cache and the address information of the data to be written in the BD read by the uplink BD reading module 1121; specifically, in the current time slice, the uplink instruction generating module 1122 acquires a BD from the uplink BD reading module 1121 as a current BD, generates a write instruction according to the data size of the data to be sent stored in the peripheral cache, and carries the data length information of the data to be sent in the peripheral cache and the address information of the data to be written in the CPU memory in the current BD in the generated write instruction; saving the current BD; the generated write instruction is sent to the write data module 122.
The data writing module 122 is configured to, for a current write instruction in the sorted order obtained by the arbitration, read data of a corresponding length from storage control corresponding to a DMA channel that transmits the current write instruction in an external cache according to data length information in the current write instruction, and transmit the read data to a corresponding storage space in the CPU memory that is pointed by address information in the current write instruction; when polling to the current write command, feeding back a write response to the uplink channel of the DMA channel that sent the current write command (i.e., the uplink command generating module 1122 of the uplink channel 112); after reading out the data from the peripheral cache and sending the data to the CPU memory, feeding back a write completion response to the uplink channel of the DMA channel that sends the current write instruction (i.e., the uplink instruction generating module 1122 of the uplink channel 112);
the uplink instruction generating module 1123 is further configured to: after receiving the write response from the write data module 122, the current BD is saved; after receiving the write completion response from the write data module 122, one BD out of the BDs stored in the uplink command generating module 1122 is sent to the uplink write-back module 1123;
an upstream write-back module 1123 to: rewriting the control right information in the received BD into a CPU, writing the data length information in the writing instruction into the BD, and sending the rewritten BD to a CPU memory; specifically, the upstream write-back module 1123 stores the rewritten BD, and counts a predetermined write-back period when it is determined that the rewritten BD is stored in the upstream write-back module 1123; in the timing cycle, when the number of the saved rewritten BDs is greater than or equal to the predetermined number, the predetermined number of rewritten BDs is used as the BD to be sent, and the BD to be sent is sent to the CPU memory, and when the number of the saved rewritten BDs is smaller than the predetermined number, the saved rewritten BD is used as the BD to be sent, and the BD to be sent is sent to the CPU memory, that is, the BD to be sent is sent to the scheduling unit 13.
Fig. 8 shows a work flow chart of the upstream instruction generating module 1122 in fig. 7, that is, fig. 8 shows an operating principle of a control operation of an upstream channel for upstream data transmission, which includes the following processing procedures:
step 801, after receiving the BD update message from the CPU, the uplink BD reading module 1121 reads a plurality of BDs from the CPU memory, and stores the read BDs; specifically, the uplink BD reading module 1121 sends an uplink BD reading request to the CPU memory, where the uplink BD reading request carries the number of BDs requested to be read; as described above, the number of BDs may be one or more; the uplink BD reading module 1121 receives a plurality of BDs from the CPU memory for the uplink BD reading request, and stores the received BDs;
step 802, in the current time slice, under the condition that the uplink instruction generating module 1122 has a free storage space, the uplink instruction generating module 1122 acquires a BD from the uplink BD reading module 1121 as a current BD; specifically, the uplink instruction generating module 1122 determines that a BD is stored in the uplink BD reading module 1121, and when there is free storage space in the uplink instruction generating module 1122, a BD is obtained from the uplink BD reading module 1121 as a current BD in a current time slice;
step 803, the uplink instruction generating module 1122 generates a write instruction corresponding to the current BD, where the generated write instruction carries data length information of data to be sent in the peripheral cache and address information of data to be written in the CPU memory in the current BD;
step 804, the uplink instruction generating module 1122 sends the generated write instruction to the write data module 122, so that the write data module 122 performs a data handling operation according to the write instruction;
step 805, after receiving the write response from the write data module 122, the uplink instruction generating module 1122 stores the current BD, where the buffer queue for storing the BD is a first-in first-out queue, where the write response is fed back to the uplink instruction generating module 1122 by the write data module 122 when the write data module 122 polls the write instruction sent by the uplink instruction generating module 1122; the process returns to step 803.
Fig. 9 shows a flowchart of processing operation of the write data module 122 in fig. 7 on the upstream data, that is, fig. 9 shows an operation schematic diagram of data transportation of the write data module 122 on the upstream data, which includes the following processing steps:
In the above processing procedure, the uplink BD reading module 1121 reads BDs from the CPU memory in batch and stores the read BDs, so that the uplink instruction generating module 1122 takes out BDs one by one and generates a write instruction according to the BDs, so that the data writing module 122 performs data transfer work according to the write instruction, and after the uplink instruction generating module 1122 stores a BD corresponding to the write response according to the write response fed back by the data writing module 122, the uplink instruction generating module 1122 generates a write instruction according to the next BD, so that the operation of generating the write instruction performed by the uplink BD reading module 1121 is not dependent on whether the data is written into the CPU memory by the data writing module 122, and a pipeline operation of controlling the uplink data can be performed; moreover, the data writing module 122 arbitrates the writing instructions from the uplink channels of the plurality of DMA channels, and performs data carrying operations according to the arbitration sequence and the writing instructions in sequence, so as to form a pipeline operation of data carrying operations on uplink data; therefore, the transmission speed of the uplink DMA data transmission can be improved, and the method can be applied to the application scene of high-speed uplink data transmission.
On the basis of the processing principle of the uplink data transmission, in an application scenario adopting a BD ring, the DMA data transmission further includes a processing procedure of uplink BD write-back.
Fig. 10 shows a work flow diagram of the upstream write-back module 1123 in fig. 7, that is, fig. 10 shows an operation principle of BD write-back on upstream data, which includes the following processes:
Through the above process, the upstream write-back module 1123 can write back BDs in batch, reduce the number of times of writing back BDs, and reduce the bus bandwidth occupied by writing back BDs, thereby increasing the speed of DMA data transmission. It is also possible to avoid BD congestion and BD loss caused when the number of BDs rewritten in the downlink 111 increases excessively instantaneously, and to avoid the situation where the number of BDs rewritten is less than a predetermined number for a long period of time, the BD after rewriting cannot be returned to the CPU.
In summary, according to the technical solution of the embodiments of the present invention, a plurality of DMA channels and a data transmission unit are disposed in a DMA controller, a control operation of data transmission and a data transfer operation of data transmission are separated, that is, the plurality of DMA channels process the control operation of DMA data transmission, specifically, each DMA channel performs a BD management operation and a transmission instruction generation operation, one data transmission unit processes all data transfer operations of DMA data transmission, specifically, the data transmission unit arbitrates transmission instructions from the plurality of DMA channels, and sequentially executes each transmission instruction according to a sorting order obtained by the arbitration, so as to transfer data between a CPU memory and a peripheral cache, it can be seen that the data control operation performed by a DMA channel does not depend on the data transfer operation performed by the data transmission unit, and a pipelining operation of the control operation of data transmission can be formed on the DMA channel side, the data transmission unit sequentially processes transmission instructions from the plurality of DMA channels, and the data transmission unit side forms the flow operation of data carrying operation of data transmission, so that the data transmission speed of the DMA controller can be improved, and the DMA controller can be suitable for application scenes of high-speed data transmission.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A multi-channel direct memory access, DMA, controller, comprising: a plurality of DMA channels and data transmission units;
the DMA channel is used for reading the BD from a CPU memory after receiving a cache identifier BD updating message from a central processing unit CPU, and generating a transmission instruction according to the BD and the data storage condition in the peripheral cache;
and the data transmission unit is used for arbitrating the transmission instructions from the plurality of DMA channels, sequentially executing each transmission instruction according to the sequencing sequence obtained by arbitration, and transmitting data between the CPU memory and the peripheral cache.
2. The multi-channel DMA controller of claim 1, wherein the transfer instruction comprises: a read instruction; then the process of the first step is carried out,
the DMA channel specifically includes: the downlink channel is used for reading the BD from the CPU internal memory after receiving the BD updating message from the CPU, and generating the reading instruction according to the read data length information in the read BD and the data size of the received data stored in the peripheral cache;
the data transmission unit specifically includes: and the data reading module is used for arbitrating the read instructions from the downlink channels of the plurality of DMA channels, sequentially reading corresponding data from the CPU memory according to the read instructions according to the sequencing sequence obtained by arbitration, and sending the read data to the peripheral cache.
3. The multi-channel DMA controller of claim 2, wherein the downstream channel specifically comprises:
the downlink BD reading module is used for reading a plurality of BDs from the CPU memory and storing the read BDs after receiving a BD updating message from the CPU;
and the downlink instruction generating module is used for generating the read instruction according to the read data length information in the BD read by the downlink BD reading module and the data size of the received data stored in the peripheral cache.
4. The multi-channel DMA controller of claim 3, wherein the downlink instruction generating module is specifically configured to: executing current BD reading operation, judging operation, generating read instruction operation and sending read instruction operation; wherein,
read current BD operation: in the current time slice, under the condition that the downlink instruction generating module has a free storage space, acquiring a BD from the downlink BD reading module as a current BD;
and (4) judging operation: judging whether a comparison condition is satisfied, wherein the comparison condition is as follows: comparing the data length indicated by the read data length information in the current BD with the sum of the data lengths indicated by the read data length information in each BD which is stored in the downlink instruction generating module and corresponds to the generated read instruction, and judging whether the sum is smaller than the size of an idle storage space in the peripheral cache, corresponding to the downlink channel of the DMA channel, in the storage space, executing the operation of generating the read instruction under the condition that the comparison condition is satisfied, or else, continuing to wait until the comparison condition is satisfied;
generating a read instruction operation: generating a reading instruction corresponding to the current BD, wherein the reading instruction carries the length information of the reading data in the current BD and the address information of the reading data in the current BD; and storing the current BD in the downlink instruction generating module;
sending a read instruction operation: and sending the generated reading instruction corresponding to the current BD to the data reading module.
5. The multi-channel DMA controller of claim 4 wherein the read data module is specifically configured to:
and for the current read instruction in the sequencing sequence obtained by arbitration, reading data with corresponding length from the storage space of the corresponding address in the CPU memory according to the address information and the read data length information in the current read instruction, and sending the read data to the storage space corresponding to the DMA channel for sending the current read instruction in the peripheral cache.
6. The multi-channel DMA controller of claim 4 wherein the read data module is further to: when the current read instruction in the sequencing sequence obtained by arbitration is polled to the current read instruction, feeding back a read response to a downlink channel of a DMA channel sending the current read instruction; after reading out the data from the CPU memory and sending the data to the peripheral cache, feeding back a read completion response to a downlink channel of a DMA channel sending the current read instruction; then the process of the first step is carried out,
the downlink channel further comprises: a downstream write-back module; wherein,
the downlink instruction generating module is further configured to: after receiving the read response from the read data module, saving the current BD in the downlink instruction generating module; after receiving a read completion response from the read data module, taking out a BD from BDs stored in the downlink instruction generating module and sending the BD to the downlink write-back module;
the downlink write-back module is configured to: and rewriting the control right information in the received BD to a CPU, and sending the rewritten BD to the CPU memory.
7. The multi-channel DMA controller of claim 6 wherein the downstream write-back module is specifically configured to:
saving the rewritten BD, and timing a predetermined write-back period when the rewritten BD is judged to be stored in the downlink write-back module; and in a timing period, when the number of the stored rewritten BD is greater than or equal to the preset number, taking the preset number of the rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory, and when the number of the stored rewritten BD is less than the preset number, taking the stored rewritten BD as the BD to be sent and sending the BD to be sent to the CPU memory after timing.
8. The multi-channel DMA controller of claim 1, wherein the transfer instruction comprises: a write instruction; then the process of the first step is carried out,
the DMA channel specifically includes: the uplink channel is used for reading the BD from the CPU memory after receiving the BD updating message from the CPU, and generating the writing instruction according to the data size of the data to be sent stored in the peripheral cache and the address information of the data to be written in the read BD;
the data transmission unit specifically includes: and the data writing module is used for arbitrating the writing instructions from the uplink channels of the plurality of DMA channels, sequentially reading corresponding data from the peripheral cache according to the ordering sequence obtained by arbitration and according to each writing instruction, and sending the read data to the CPU memory.
9. The multi-channel DMA controller of claim 8, wherein the upstream channel specifically comprises:
the uplink BD reading module is used for reading a plurality of BDs from the CPU memory and storing the read BDs after receiving a BD updating message from the CPU;
and the uplink instruction generating module is used for generating the write instruction according to the data size of the data to be sent stored in the peripheral cache and the address information of the data to be written in the BD read by the uplink BD reading module.
10. The multi-channel DMA controller of claim 9, wherein the upstream instruction generation module is specifically configured to:
in the current time slice, under the condition that the uplink instruction generating module has free storage space, acquiring a BD from the uplink BD reading module as a current BD;
generating a write instruction corresponding to the current BD, wherein the generated write instruction carries data length information of data to be sent in the peripheral cache and address information of data to be written in a CPU memory in the current BD;
saving the current BD in the uplink instruction generating module;
and sending the generated write command to the write data module.
11. The multi-channel DMA controller of claim 10, wherein the write data module is specifically configured to:
and for the current write instruction in the sequencing sequence obtained by arbitration, reading data with corresponding length from the storage control corresponding to the DMA channel for sending the current write instruction in the peripheral cache according to the data length information in the current write instruction, and sending the read data to a corresponding storage space in the CPU memory indicated by the address information in the current write instruction.
12. The multi-channel DMA controller of claim 11, wherein the write data module is further configured to: when the current write command is polled, feeding back a write response to an uplink channel of a DMA channel which sends the current write command; after reading out data from the peripheral cache and sending the data to the CPU memory, feeding back a write completion response to an uplink channel of a DMA channel which sends a current write instruction; then the process of the first step is carried out,
the uplink channel further comprises: an upstream write-back module; wherein,
the uplink instruction generating module is further configured to: after receiving a write response from the write data module, saving the current BD in the uplink instruction generating module; after receiving a write completion response from the write data module, taking out one BD from the BDs stored by the uplink instruction generating module and sending the BD to the uplink write-back module;
the upstream write-back module is configured to: and rewriting the control right information in the received BD to a CPU, writing the data length information in the writing command into the BD, and sending the rewritten BD to the CPU memory.
13. The multi-channel DMA controller of claim 12, wherein the upstream write-back module is specifically configured to:
saving the rewritten BD; under the condition that the rewritten BD is judged to be stored in the uplink write-back module, timing a preset write-back period; and in a timing period, when the number of the stored rewritten BD is greater than or equal to the preset number, taking the preset number of the rewritten BD as the BD to be sent, and sending the BD to be sent to the CPU memory, and when the number of the stored rewritten BD is less than the preset number, taking the stored rewritten BD as the BD to be sent and sending the BD to be sent to the CPU memory after timing.
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