CN103064695A

CN103064695A - Dynamic loading system of field-programmable gate array and loading method thereof

Info

Publication number: CN103064695A
Application number: CN2011103240677A
Authority: CN
Inventors: 尹龙
Original assignee: GULFSTREAM INSTRUMENT TECHNOLOGIES Ltd
Current assignee: GULFSTREAM INSTRUMENT TECHNOLOGIES Ltd
Priority date: 2011-10-21
Filing date: 2011-10-21
Publication date: 2013-04-24

Abstract

The invention discloses a dynamic loading system of a field-programmable gate array and a loading method of the dynamic loading system of the field-programmable gate array. The dynamic loading system comprises an upper computer, a Peripheral Component Interconnect (PCI) interface, a Complex Programmable Logic Device (CPLD) and a memorizer. The upper computer is connected with a Field Programmable Gate Array (FPGA), and the FPGA is connected with the CPLD. The CPLD is connected with the memorizer. The dynamic loading system of the field-programmable gate array and the loading method of the dynamic loading system of the field-programmable gate array can update content in the memorizer in different loading environments and therefore meets different system requirements.

Description

The dynamic loading system of field programmable gate array and loading method thereof

Technical field

The present invention relates to communication field, particularly dynamic loading system and the loading method thereof of a kind of field programmable gate array (FPGA).

Background technology

Field programmable gate array (Field Programmable Gate Array, FPGA) has flexible in programming and High-Speed Hardware, therefore, is widely used at communication field.The FPGA device has a lot of loading modes, for example: JTAG pattern (Joint Test Action Group Mode, boundary scan technique), PS pattern (Passive Serial mode, passive serial mode), AS pattern (Active Serial mode, initiatively serial mode), programming mode (In-Socket Programming mode) etc. in the socket.In the above-mentioned pattern, the AS pattern is to adopt outside FLASH that FPGA is carried out serial to load.The PS pattern is to adopt external devices to carry out the serial of FPGA is loaded.JTAG, AS, PS are the many loading modes that adopt at present.

By comparing, analyzing, filter out the higher patent information of following degree related to the present invention, information is following to be listed: the patent " a kind of method of online upgrading fpga logic " of China's application, its application number is 201010598499.2, publication number is 102053850A.The loading procedure of this technical scheme is as follows: A, the download bus interface of FPGA is connected by the PCIE bus interface with CPU; B, log in remote machine by the windows remote desktop, the control remote terminal writes logical file and the logical message that will upgrade by the PCIE bus to nonvolatile semiconductor memory member; C, write that upgrade logic carries out verification to the write store content among the complete FPGA; D, write end after, carry out automatic load instructions, finish loading procedure.

The shortcoming of prior art scheme is as follows:

One, in the existing scheme, in the whole system on-line loaded process, CPU intervenes whole loading procedure all the time, and under some occasions without CPU, this scheme can't load FPGA like this.And in the request for proposal, the renewal of load document upgrading is to finish under the Firmware in FPGA controls.Load document can in the situation without CPU, be carried out the dynamic load process of FPGA after upgrading by the steering logic among the CPLD.

Two, in the existing scheme, write complete after, by the upgrade logic among the FPGA content among the PROM is carried out verification, again check results is carried out subsequent operation.And in the application's motion, the not responsible verification content of fpga logic, the expense of logic is less.

Three, in the existing scheme, as run into the damage of PROM misoperation, in the time of can't loading FPGA, without emergency plan, this can cause heavy losses in some scenarios.And this motion has added two allocation plans, and when FLASH can't load, system can automatically switch to the configuration that alternative scheme is carried out FPGA.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of dynamic loading system and loading method thereof of field programmable gate array, and it can upgrade memory content in different loading environments, thereby adapts to different system requirements.

For solveing the technical problem, the invention provides a kind of dynamic loading system of field programmable gate array, it is characterized in that, it comprises host computer, pci interface, CPLD, storer, host computer is by being connected with a FPGA, and FPGA is connected with CPLD, and CPLD is connected with storer.

The present invention also provides a kind of loading method of dynamic loading system of field programmable gate array, it is characterized in that, it may further comprise the steps: A, host computer read load document, then are transferred among the FPGA by pci interface; B, subsequently, the memory write logic control CPLD in the FPGA is in the load document write store of receiving; C, write complete after, the memory read logic among the FPGA will be controlled CPLD the content in the storer will be read out, and be transferred in the host computer by pci interface; The data that D, host computer read from storer and load document data are carried out verification; E, verification succeeds then show in the load document success write store; Unsuccessful such as verification, then again carry out said process; If repeatedly verification is unsuccessful, will produce alerting signal, reminding user carries out subsequent operation; After F, the verification succeeds, carry out warm start and reset; At this moment, the load logic in the CPLD is the load document in the read memory, and by the load logic among the CPLD, FPGA carried out dynamic load; G, fortuitous event cause FPGA can't dynamic load after, can automatically switch to the standby configuration scheme by system and carry out reloading of FPGA; Wherein, fortuitous event is included in power down when upgrading the upgrading load document, loads and repeatedly unsuccessfully wait situation, causes memory content to damage, and can't automatically load; At this moment, after repeated loading was unsuccessful, logic by the gauge tap state, was adjusted the loading mode of FPGA with initiatively switching to standby configuration among the CPLD, enables the start-up loading that spare chip carries out FPGA, load successfully after, CPLD is with the switching attitude loading mode that reverses.

Positive progressive effect of the present invention is:

One, under some environment of intervening without CPU, can carry out the dynamic load of FPGA.Simultaneously, the present invention can make module, joins in the existing system, and is portable high.After the FPGA internal logic is revised, can add the multiple interfaces logic such as logic among the FPGA, can from different equipment, obtain the renewal upgraded version of FPGA load document, can in different loading environments, upgrade the FLASH content, thereby adapt to different system requirements.

Two, cost of the present invention is low, flexibility ratio is high.FPGA is more cheap such as the dilatation of CPLD cost ratio, and the storeies such as FLASH ROM can be selected suitable capacity according to the load document size.The FPGA loading only needs the CPLD logic control need not the CPU intervention, and loading is flexible and cost is low.The each several part degree of association is not strong, can upgrade separately during each parts upgrading, and flexibility ratio is high.

Three, the present invention adds the standby configuration scheme, has added the load mode that gate-controlled switch can be regulated FPGA on the circuit, and when fortuitous event can't carry out dynamic load, by-pass cock was adjusted the FPGA load mode, and FPGA can start again by the standby configuration scheme.

Description of drawings

Fig. 1 is the structural representation of one embodiment of the invention.

Embodiment

The below lifts a preferred embodiment, and comes by reference to the accompanying drawings the clearer the present invention that intactly illustrates.

As shown in Figure 1, the dynamic loading system of field programmable gate array of the present invention comprises host computer, pci interface, CPLD (Complex Programmable Logic Device, the complex programmable device), storer, host computer is by being connected with a FPGA, FPGA is connected with CPLD, and CPLD is connected with storer.Host computer be can operating software processor DSP or the processor of ARM or PowerPC or single-chip microcomputer or universal PC processor or programmable logic device (PLD).Pci interface comprises PCI, PCIE, but is not limited to above two kinds, can be the communication interface between other host computers and the FPGA.Storer can be Nand FLASH or Nor FLASH or EEPROM or other nonvolatile semiconductor memory member.

The function of upper computer software is as follows: one, accept the control signal of FPGA, by PCI correct load document is transferred among the FPGA.Two, according to the FPGA control signal that receives, the file among the FLASH that transmits among the FPGA is carried out verification.Three, verification succeeds then load document be transmitted.If verification is unsuccessful, then again repeat said process.As repeatedly writing not success, then the warning reminding user operates.Logic function in the FPGA comprises: one, PCI logic (or other communication interface logic of PCIE logical OR), responsible and host computer carries out the agreements such as data transmission of PCI.Two, the logic of upper computer software being controlled is responsible for accepting data that software sends over and is sent data in the FLASH in upper computer software.Three, the logic of control CPLD.Be responsible for control CPLD FLASH is carried out read-write operation.Logic function in the CPLD comprises: one, read-write FLASH logic.According to control signal write data among the FLASH or from FLASH reading out data be transferred among the FPGA.Two, FPGA load logic, when being responsible for starting, reading out data carries out load operation to FPGA from FLASH.FLASH is responsible for storing data, selects suitable capacity according to the size of load document.

The loading of the dynamic loading system of field programmable gate array may further comprise the steps: A, host computer read load document, then are transferred among the FPGA by pci interface; B, subsequently, the memory write logic control CPLD in the FPGA is in the load document write store of receiving; C, write complete after, the memory read logic among the FPGA will be controlled CPLD the content in the storer will be read out, and be transferred in the host computer by pci interface; The data that D, host computer read from storer and load document data are carried out verification; E, verification succeeds then show in the load document success write store; Unsuccessful such as verification, then again carry out said process; If repeatedly verification is unsuccessful, will produce alerting signal, reminding user carries out subsequent operation; After F, the verification succeeds, carry out warm start and reset; At this moment, the load logic in the CPLD is the load document in the read memory, and by the load logic among the CPLD, FPGA carried out dynamic load; G, fortuitous event cause FPGA can't dynamic load after, can automatically switch to the standby configuration scheme by system and carry out reloading of FPGA; Wherein, fortuitous event is included in power down when upgrading the upgrading load document, loads and repeatedly unsuccessfully wait situation, causes memory content to damage, and can't automatically load; At this moment, after repeated loading was unsuccessful, logic by the gauge tap state, was adjusted the loading mode of FPGA with initiatively switching to standby configuration among the CPLD, enables the start-up loading that spare chip carries out FPGA, load successfully after, CPLD is with the switching attitude loading mode that reverses.

Although more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, under the prerequisite that does not deviate from principle of the present invention and essence, can make various changes or modifications to these embodiments.Therefore, protection scope of the present invention is limited by appended claims.

Claims

1. the dynamic loading system of a field programmable gate array is characterized in that, it comprises host computer, pci interface, CPLD, storer, and host computer is by being connected with a FPGA, and FPGA is connected with CPLD, and CPLD is connected with storer.

2. the loading method of the dynamic loading system of a field programmable gate array is characterized in that, it may further comprise the steps: A, host computer read load document, then are transferred among the FPGA by pci interface; B, subsequently, the memory write logic control CPLD in the FPGA is in the load document write store of receiving; C, write complete after, the memory read logic among the FPGA will be controlled CPLD the content in the storer will be read out, and be transferred in the host computer by pci interface; The data that D, host computer read from storer and load document data are carried out verification; E, verification succeeds then show in the load document success write store; Unsuccessful such as verification, then again carry out said process; If repeatedly verification is unsuccessful, will produce alerting signal, reminding user carries out subsequent operation; After F, the verification succeeds, carry out warm start and reset; At this moment, the load logic in the CPLD is the load document in the read memory, and by the load logic among the CPLD, FPGA carried out dynamic load; G, fortuitous event cause FPGA can't dynamic load after, can automatically switch to the standby configuration scheme by system and carry out reloading of FPGA; Wherein, fortuitous event is included in power down when upgrading the upgrading load document, loads and repeatedly unsuccessfully wait situation, causes memory content to damage, and can't automatically load; At this moment, after repeated loading was unsuccessful, logic by the gauge tap state, was adjusted the loading mode of FPGA with initiatively switching to standby configuration among the CPLD, enables the start-up loading that spare chip carries out FPGA, load successfully after, CPLD is with the switching attitude loading mode that reverses.