CN103064218A - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
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- CN103064218A CN103064218A CN2012105848164A CN201210584816A CN103064218A CN 103064218 A CN103064218 A CN 103064218A CN 2012105848164 A CN2012105848164 A CN 2012105848164A CN 201210584816 A CN201210584816 A CN 201210584816A CN 103064218 A CN103064218 A CN 103064218A
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Abstract
The invention provides a liquid crystal display device which comprises a first substrate, a second substrate, and a liquid crystal layer. The first substrate is opposite to the second substrate. The liquid crystal layer is stuck between the first substrate and the second substrate. The first substrate comprises a pixel electrode and a first alignment film. The first alignment film, which is opposite to the second substrate, is arranged on the pixel electrode. The second substrate comprises at least one support pillar, a transparent conducting layer and a second alignment film. The support pillar is coated with the transparent conducting layer. The second alignment film, which is opposite to the first substrate, is arranged on the transparent conducting layer. The first alignment film attaches to the second alignment film on the support pillar. According to the design, the support pillar is coated with the pixel electrode or the transparent conducting layer without designing special storage capacitance lines on the first substrate and without widening the width of scanning lines. The liquid crystal display device can not only increase the pixel opening ratio substantially and improve effective light-permeating area, but also shorten manufacture time and lower manufacture cost.
Description
Technical field
The present invention relates to a kind of high transmission rate liquid crystal indicator.
Background technology
The luminosity of liquid crystal indicator is the product of back light source brightness and pixel transmitance, under the certain prerequisite of the luminosity of liquid crystal indicator, improves the brightness that the pixel transmitance can reduce backlight, thereby realizes energy-saving and cost-reducing.Raising pixel aperture ratio, liquid crystal can improve the pixel transmitance through efficient, Polarizer transmitance, colored filter transmitance.Wherein, it is the most common improving pixel aperture ratio, also is effective method.
As depicted in figs. 1 and 2 for having the floor map of common liquid crystal indicator now, the available liquid crystal display device comprises first substrate 10, second substrate 20, and be folded in liquid crystal (not shown) between first substrate 10 and the second substrate 20, each array element 11 of first substrate 10 comprises: data line 12, sweep trace 13, storage capacitance line 14(is called for short the Cs line), transistor 15, and pixel electrode 16, have effective light transmission zone 17 in the pixel electrode 16, pixel aperture ratio refers to remove in the array element 11 data line 11, sweep trace 12, storage capacitance line 14(is called for short the Cs line) etc. the distribution zone, and the light after transistor 15 zones (usually adopting black matrix" to hide) is by the area of part and the ratio between the array element entire area.
Aperture opening ratio is higher, and namely the area in effective light transmission zone 17 is larger among Fig. 1, and the efficient that light passes through is higher.After first substrate 10 and second substrate 20 are fitted, between two substrates, pour into liquid crystal, just form a pixel that can show certain brightness.
In Fig. 1, use special-purpose Cs line 14 and pixel electrode 16 to overlap to form memory capacitance, since the existence of Cs line 14, the effective light transmission zone of obviously having reduced pixel electrode 16.Figure 3 shows that the schematic diagram of the array element structure of using special-purpose Cs line, in array element 11, can be used for the up and down distance of open area of printing opacity and be Lc.Figure 4 shows that the schematic diagram that uses sweep trace to double as the array element structure of memory capacitance, overlap to form memory capacitance with the sweep trace 13 of lastrow array element and the pixel electrode 16 of next line array element exactly, it can be used for the up and down distance of open area of printing opacity for Lg, in the general situation, the length of Lg is greater than the length of Lc.
In array element, can be used for the up and down distance of open area of printing opacity is an important topic that promotes pixel aperture ratio, and an important countermeasure of this problem is to omit the Cs line, perhaps dwindles the width of the sweep trace that doubles as storage capacitor electrode.At present, in high-precision refinement liquid crystal indicator, Figure 5 shows that common FFS(Fringe Field Switching, fringe field switching) schematic diagram of dot structure, the FFS liquid crystal indicator comprises: first substrate 10, the first Polarizer 41 at first substrate 10 downsides, second substrate 20, at the second Polarizer 42 and the liquid crystal layer 30 between first substrate 10 and second substrate 20 of second substrate 20 upsides sequentially are provided with transparency conducting layer 43, insulation course 44 and pixel electrode 45 on the first substrate 10.
The advantage of FFS structure is that the pixel transmitance is high, and namely effective light transmission region area shown in Figure 1 is larger, and reason is in the FFS structure, replaces metal Cs lines with transparency conducting layer 43 that can printing opacity.Although replace metal Cs line to improve pixel aperture ratio because omitting the Cs line with transparency conducting layer, but transparency conducting layer itself is not 100% printing opacity, if with ITO as transparency conducting layer, transmittance is generally about 90%-93%, so this FFS structure is not utilized the area of original Cs line part fully.And, because transparency conducting layer need to use special film forming, photoetching, etching technics, increased manufacturing cost and prolonged manufacturing time.
Summary of the invention
The invention provides a kind of liquid crystal indicator of implementation method of new memory capacitance, it not only can significantly increase pixel aperture ratio, improves the effective light transmission region area, can also shorten manufacturing time and reduce manufacturing cost.
The invention provides a kind of liquid crystal indicator, comprise relative first substrate and second substrate and be folded in first substrate and second substrate between liquid crystal layer, described first substrate comprises: pixel electrode, be positioned at the first alignment film on the pixel electrode, this first alignment film is positioned at a side relative with second substrate; Described second substrate comprises: at least one support column, coat support column transparency conducting layer, be positioned at the second alignment film on the transparency conducting layer, this second alignment film is positioned at a side relative with first substrate, wherein, described the first alignment film and the second alignment film are fit-state in the position of support column.
Wherein, described first substrate is array base palte, and described second substrate is color membrane substrates, and described second substrate comprises look resistance layer and black matrix", and described support column is positioned at look resistance layer below.
Wherein, described first substrate is array base palte, and described second substrate is color membrane substrates, and described second substrate comprises black matrix", and described support column is positioned at the black matrix" below.
Wherein, the pixel electrode of first substrate and the transparency conducting layer of second substrate form memory capacitance in the zone of support column position, and described pixel electrode and transparency conducting layer are as the parallel-plate electrode of memory capacitance.
Wherein, described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the sweep trace of first substrate and second substrate.
Wherein, described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, and the array element left and right sides of each row is equipped with data line, and pixel electrode covers the data line of both sides; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the data line of first substrate and second substrate.
Wherein, described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, and the array element of each row only has a data lines, and pixel electrode covers two adjacent data lines; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the data line of first substrate and second substrate.
Wherein, described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, the repair line parallel with sweep trace, the parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the repair line of first substrate and second substrate.
Wherein, the face that support column contacts with the electrically conducting transparent of second substrate is second, and second periphery of the support column of memory capacitance and the distance between the pixel electrode edge are greater than the Anawgy accuracy value of first substrate and second substrate.
Wherein, the face that support column contacts with the electrically conducting transparent of second substrate is second, and the distance between second periphery of the support column of pixel electrode edge and memory capacitance is greater than the Anawgy accuracy value of first substrate and second substrate.
Another liquid crystal indicator of the present invention, comprise relative first substrate and second substrate and be folded in first substrate and second substrate between liquid crystal layer, described first substrate comprises: at least one support column, coat support column pixel electrode, be positioned at the first alignment film on the pixel electrode, this first alignment film is positioned at a side relative with second substrate; Described second substrate comprises: transparency conducting layer, be positioned at the second alignment film on the transparency conducting layer, this second alignment film is positioned at a side relative with first substrate, and wherein, described the first alignment film and the second alignment film are fit-state in the position of support column.
Wherein, described first substrate is array base palte; described second substrate is color membrane substrates; and described first substrate also comprise crisscross sweep trace and data line, the gate insulator between sweep trace and the data line, between data line and pixel electrode across the protection insulation course, described support column is positioned on the protection insulation course.
Wherein, described first substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described second substrate also comprises look resistance layer and black matrix", the black matrix" of the corresponding second substrate of support column.
Wherein, the pixel electrode of first substrate and the transparency conducting layer of second substrate form memory capacitance in the zone of support column position, and described pixel electrode and transparency conducting layer are as the parallel-plate electrode of memory capacitance.
The present invention need to or not to widen the width of sweep trace at the special Cs line of first substrate design by pixel electrode or transparency conducting layer are coated support column yet, compares with the FFS structure, need to be on first substrate specialized designs layer of transparent conductive layer.The present invention not only can significantly increase pixel aperture ratio, improves the effective light transmission region area, can also shorten manufacturing time and reduce manufacturing cost.
Description of drawings
Fig. 1 is the floor map of the first substrate of existing common liquid crystal indicator;
Fig. 2 is the floor map of the second substrate of existing common liquid crystal indicator;
Fig. 3 is the existing schematic diagram that uses the array element structure of special-purpose Cs line;
Fig. 4 is the existing schematic diagram that uses sweep trace to double as the array element structure of memory capacitance;
Fig. 5 is the schematic diagram of existing FFS structure;
Fig. 6 is the structural representation of the array element of liquid crystal indicator of the present invention;
Fig. 7 is the part-structure schematic diagram of the array element of first substrate shown in Figure 6;
Fig. 8 is the cut-open view in the A-A direction shown in Figure 7;
Fig. 9 is the structural representation of the second embodiment of liquid crystal indicator of the present invention;
Figure 10 is another structural representation of the second embodiment of liquid crystal indicator of the present invention;
Figure 11 is the structural representation of the 3rd embodiment of liquid crystal indicator of the present invention;
Figure 12 is the structural representation of the 4th embodiment of the Double Data line design of liquid crystal indicator of the present invention;
Figure 13 is the structural representation of the 5th embodiment of the forms data line design of liquid crystal indicator of the present invention;
Figure 14 is the structural representation that liquid crystal indicator of the present invention increases the 6th embodiment of repair line.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
Fig. 6 to Fig. 8 is the structural representation of liquid crystal indicator the first embodiment of the present invention, as shown in Figure 8, liquid crystal indicator comprise relative first substrate 10, second substrate 20, be folded in the liquid crystal layer between first substrate 10 and the second substrate 20 and be supported on first substrate 10 or second substrate 20 on some support columns 40, described first substrate 10 and second substrate 20 relative surfaces are equipped with alignment film, and the alignment film be located on the first substrate 10 of definition is called the first alignment film 51, and the alignment film of being located on the second substrate 20 is called the second alignment film 52.
Wherein, first substrate 10 is array base palte (TFT substrate), and second substrate 20 is color membrane substrates (CF substrate).
Be illustrated in figure 6 as the structural representation of the array element of liquid crystal indicator, described first substrate 10 is positioned on the first glass substrate 11, it comprises: crisscross some sweep traces 12 and data line 13, pixel electrode 14, thin film transistor (TFT) 15, and be positioned at the first alignment film 51 on the pixel electrode 14, thin film transistor (TFT) 15 comprises the grid (not shown) that is connected with sweep trace 12, the source electrode (not shown) that is connected with data line 13, and the drain electrode (not shown) that is connected with pixel electrode 14, electricity between drain electrode and the pixel electrode 14 connects by the contact hole (not shown), in the present embodiment, spatially there is not the overlapping region between pixel electrode 14 and the data line 13.Wherein, between sweep trace 12 and the data line 13 across gate insulator 16, between data line 13 and the pixel electrode 14 across protection insulation course 17, because gate insulator 16 and protection insulation course 17 are hyaline layer, and whole distribution, therefore do not mark at Fig. 6.
As shown in Figure 8, in the present embodiment, be divided into viewing area and shading region on the second substrate 20, described support column 40 is positioned at the shading region of second substrate 20.In the present embodiment, second substrate 20 is positioned on the second glass substrate 21, and it comprises: look resistance layer 23 and black matrix" 23, the support column 40 that is positioned at look resistance layer 22 belows, transparency conducting layer 24 and the second alignment film 52.
In other embodiments, second substrate 20 also may not comprise the look resistance layer, and support column 40 is located immediately at the below of black matrix".
The film that transparency conducting layer 24 is made for tin indium oxide (ITO) or Graphene (Graphene) or the transparent conductive materials such as carbon nano-tube (CNT) or nano silver wire (Ag nano wire), the transmitance of transparency conducting layer 24 (@550nm) is not less than 80%, and surface resistance is not higher than 10
3Ω/sqm, transmitance all once 〉=90%.
When second substrate 20 is made, form black matrix" 23 at the second glass substrate 21 first, form the look resistance layer at black matrix" 23 again, 23, be positioned at support column 40 in 22 formation of look resistance layer again, cover again transparency conducting layer 24, form at last the second alignment film 52, by such manufacture process, transparency conducting layer 24 parts of second substrate 20 cover on the support column 40, and a part covers on the look resistance layer 22; The second alignment film 52 covers transparency conducting layer 24, that is: support column 40 is covered by in transparency conducting layer 24 and the second alignment film 52.
In this way, the first alignment film 51 of first substrate 10 and the second alignment film 52 of second substrate 20 are the state of fitting tightly in support column 40 positions, and formation overlapping region 100 as shown in Figure 8, this overlapping region 100 is positioned at the top of the sweep trace 12 of first substrate 10, and this overlapping region 100 is between the black matrix" 22 of the sweep trace 12 of first substrate 10 and second substrate 20.
Suppose and Figure 7 shows that the sweep trace 122,123 that m-1 is capable and m is capable, the schematic diagram of the capable data line 132 of n, the pixel electrode 143 of the array element of m horizontal scanning line 123 correspondences extends up on the m-1 bar sweep trace 122, pixel electrode 143 and m-1 bar sweep trace 122 overlap, and form the memory capacitance Csg(Cs on Gate of first) 18.
This overlapping region 100 of overlapping region 100(shown in Figure 8 be positioned at sweep trace 12 above), across the first alignment film 51 of first substrate 10 sides and the second alignment film 52 of second substrate 20 sides, form second portion memory capacitance Cscc(Cs on CF COM between the transparency conducting layer 24 of the pixel electrode 143 of first substrate 10 and second substrate 20 sides), described pixel electrode 14 and transparency conducting layer 24 are as the parallel-plate electrode of memory capacitance.
The face that the face that support column 40 contacts with the look resistance layer 23 of second substrate 20 is first surface 41, contact with the transparency conducting layer 24 of second substrate 20 is second 42, and second portion memory capacitance Cscc is the overlapping area of the pixel electrode 143 of second 42 of support column 40 and first substrate; Second portion memory capacitance Cscc is positioned at lightproof area, and the both sides of relative two parallel-plate electrodes (pixel electrode 14 and transparency conducting layer 24) of second portion memory capacitance Cscc corresponding be the sweep trace of first substrate 10 and the black matrix" 22 of second substrate 20.
For m-1 bar sweep trace 122, Csg and Cscc are the signal delay time that the form of connecting affects m--1 bar sweep trace 122.So the existence of Cscc can't additionally increase the condensance of m-1 bar sweep trace 122.When actual design, except controlling the capacitance of Cscc by the different value of design support column 40 areas, can also be by adjusting the alignment film gross thickness between the Cscc, the capacitance of control Cscc.
The present invention is by being coated on support column 40 in transparency conducting layer 24 and the second alignment film 52, thereby omitted public electrode wire (Cs line), compared with prior art, can be used in the array element printing opacity the open area up and down the distance for Lcc(as shown in Figure 6) much larger than Lc(such as Fig. 3).The effective light transmission region area of pixel is much larger than structure shown in Figure 3.Equally, because the present invention does not have structure shown in Figure 4 harsh to the width requirement of sweep trace, use scanning line width of the present invention can do littlely than structure shown in Figure 4, so compare with dot structure shown in Figure 4, can be used in the array element printing opacity the open area up and down the distance for Lcc obviously greater than Lg.
Fig. 9 and the structural representation that Figure 10 shows that the second embodiment of the present invention, because there are certain contraposition deviations (unit is um) in first substrate 10 and second substrate 20 when fitting, be not subjected to the impact of contraposition deviations for the second portion memory capacitance Cscc capacitance that guarantees all pixels in the liquid crystal indicator, can carry out such as Fig. 9 or capacitance compensation design shown in Figure 10 Cscc.In Fig. 9, the edge of support column 40 first surfaces 41 peripheries and Edge Distance a, b, c, the d of pixel electrode 14 must satisfy: a〉σ, b〉σ, c〉σ, d〉σ, that is: namely: the distance between second 42 of support column 40 second portion memory capacitance Cscc(Cs on CF COM) periphery and pixel electrode 14 edges is greater than the Anawgy accuracy value of first substrate and second substrate; For scheme shown in Figure 10, Edge Distance a ', the b ' of second 42 periphery of the edge of pixel electrode and support column 40, c ', d ' must satisfy: a '〉σ; B '〉σ; C '〉σ; D '〉σ, that is: pixel electrode 14 edges and second portion memory capacitance Cscc(Cs on CF COM) second 42 periphery of support column 40 between distance greater than the Anawgy accuracy value of first substrate and second substrate.
Figure 11 shows that the structural representation of the third embodiment of the present invention; the difference of this 3rd embodiment and above-mentioned the first embodiment is: support column 40 is arranged on the first substrate 10; support column 40 is positioned at the top of protection insulation course 17; and then at support column 40 covering pixel electrodes 14; lay the first alignment film 51 at pixel electrode 14 at last, same like this so that the second alignment film 52 of the first alignment film 51 of first substrate 10 and second substrate 20 fits tightly in support column 40 positions.Under the support of support column 40, form memory capacitance Cscc between the transparency conducting layer 24 of pixel electrode 14 and second substrate 20 sides, the effect of this 3rd embodiment is identical with above-mentioned the first embodiment, therefore repeated description not.
Suppose that the face that support column 40 contacts with the pixel electrode 14 of first substrate 10 is first surface 41, the face that contacts with the protection insulation course 17 of first substrate 10 is second 42, memory capacitance Cscc is the overlapping area of the transparency conducting layer 24 of the first surface 41 of support column 40 and second substrate; Second portion memory capacitance Cscc is positioned at lightproof area, and the both sides of relative two parallel-plate electrodes (pixel electrode 14 and transparency conducting layer 24) of second portion memory capacitance Cscc corresponding be the sweep trace of first substrate 10 and the black matrix" 22 of second substrate 20.
Figure 12 shows that the structural representation of the fourth embodiment of the present invention, when protection insulation course 17 film thicknesses of first substrate 10 reach micron level, as the thickness of protecting insulation course 17 is when being 2um or 3um, this array element structure is: the array element of each row all adopts the left and right sides all to be provided with data line 13, pixel electrode 14 covers on the data line 13 of both sides, and the pixel electrode to the up-downgoing array element carries out interval driving input, support column 40 is above between adjacent two data lines 14, by forming second portion memory capacitance Cscc(Cs on CF COM with the pixel electrode of data line 13 tops that are stacked in adjacent two array elements and the transparency conducting layer of second substrate), what the both sides of two parallel-plate electrodes that second portion memory capacitance Cscc is relative (pixel electrode 14 and transparency conducting layer 24) were corresponding is the data line 13 of first substrate 10 and the black matrix" 22 of second substrate 20, support column 40 can be positioned at second substrate 20 1 sides, concrete generation type such as above-mentioned the first embodiment; Support column 40 also can be positioned at first substrate 10 1 sides, and therefore concrete generation type such as above-mentioned the 3rd embodiment are repeated description not.
Figure 13 shows that the structural representation of the fifth embodiment of the present invention, what this 5th embodiment and above-mentioned the 4th embodiment distinguished is: the array element of each row only has a data lines 13 to carry out separately the signal input, pixel electrode 14 also is to cover on the two adjacent data lines 13, with the transparency conducting layer 24 formation second portion memory capacitance Cscc(Cs on CF COMs of the pixel electrode 14 that is stacked in data line 13 tops with second substrate), what the both sides of two parallel-plate electrodes that second portion memory capacitance Cscc is relative (pixel electrode 14 and transparency conducting layer 24) were corresponding is the data line 13 of first substrate 10 and the black matrix" 22 of second substrate 20, other are all identical with above-mentioned the 4th embodiment for this 5th embodiment, therefore repeated description not.
Figure 14 shows that the structural representation of the sixth embodiment of the present invention, in order to make things convenient for the reparation of point defect or line defect, in array element, increase the repair line 19 parallel with sweep trace 12, form second portion memory capacitance Cscc(Cs on CF COM by the transparency conducting layer 24 with the pixel electrode 14 that is stacked in repair line 19 tops and second substrate 20), what the both sides of two parallel-plate electrodes that second portion memory capacitance Cscc is relative (pixel electrode 14 and transparency conducting layer 24) were corresponding is the repair line 19 of first substrate 10 and the black matrix" 22 of second substrate 20, repair line 19 is as the Cs line, when needs are repaired, be connected wherein one section isolation or connection of carrying out electrology characteristic with laser dotting with cut.Other are all identical with above-mentioned the 4th embodiment for this 6th embodiment, therefore repeated description not.
The present invention does not need the special Cs line of design on the first substrate by pixel electrode or transparency conducting layer are coated support column again, does not need to widen the width of sweep trace yet, compares with the FFS structure, need to be on first substrate specialized designs layer of transparent conductive layer.The present invention not only can significantly increase pixel aperture ratio, improves the effective light transmission region area, can also shorten manufacturing time and reduce manufacturing cost.
Claims (14)
1. liquid crystal indicator, comprise relative first substrate and second substrate and be folded in first substrate and second substrate between liquid crystal layer, it is characterized in that:
Described first substrate comprises: pixel electrode, be positioned at the first alignment film on the pixel electrode, this first alignment film is positioned at a side relative with second substrate;
Described second substrate comprises: at least one support column, coat support column transparency conducting layer, be positioned at the second alignment film on the transparency conducting layer, this second alignment film is positioned at a side relative with first substrate, wherein, described the first alignment film and the second alignment film are fit-state in the position of support column.
2. liquid crystal indicator according to claim 1, it is characterized in that: described first substrate is array base palte, and described second substrate is color membrane substrates, and described second substrate comprises look resistance layer and black matrix", and described support column is positioned at look resistance layer below.
3. liquid crystal indicator according to claim 1, it is characterized in that: described first substrate is array base palte, and described second substrate is color membrane substrates, and described second substrate comprises black matrix", and described support column is positioned at the black matrix" below.
4. according to claim 2 or 3 liquid crystal indicators of stating, it is characterized in that: the pixel electrode of first substrate and the transparency conducting layer of second substrate form memory capacitance in the zone of support column position, and described pixel electrode and transparency conducting layer are as the parallel-plate electrode of memory capacitance.
5. the liquid crystal indicator of stating according to claim 4 is characterized in that: described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the sweep trace of first substrate and second substrate.
6. the liquid crystal indicator of stating according to claim 4 is characterized in that: described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, and the array element left and right sides of each row is equipped with data line, and pixel electrode covers the data line of both sides; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the data line of first substrate and second substrate.
7. the liquid crystal indicator of stating according to claim 4 is characterized in that: described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, and the array element of each row only has a data lines, and pixel electrode covers two adjacent data lines; The parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the data line of first substrate and second substrate.
8. the liquid crystal indicator of stating according to claim 4 is characterized in that: described second substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described first substrate also comprises crisscross sweep trace and data line, the repair line parallel with sweep trace, the parallel-plate electrode of described memory capacitance is positioned at lightproof area, and the parallel-plate electrode of memory capacitance is between the black matrix" of the repair line of first substrate and second substrate.
9. the liquid crystal indicator of stating according to claim 4, it is characterized in that: the face that support column contacts with the electrically conducting transparent of second substrate is second, and second periphery of the support column of memory capacitance and the distance between the pixel electrode edge are greater than the Anawgy accuracy value of first substrate and second substrate.
10. the liquid crystal indicator of stating according to claim 4, it is characterized in that: the face that support column contacts with the electrically conducting transparent of second substrate is second, and the distance between second periphery of the support column of pixel electrode edge and memory capacitance is greater than the Anawgy accuracy value of first substrate and second substrate.
11. a liquid crystal indicator, comprise relative first substrate and second substrate and be folded in first substrate and second substrate between liquid crystal layer, it is characterized in that:
Described first substrate comprises: at least one support column, coat support column pixel electrode, be positioned at the first alignment film on the pixel electrode, this first alignment film is positioned at a side relative with second substrate;
Described second substrate comprises: transparency conducting layer, be positioned at the second alignment film on the transparency conducting layer, this second alignment film is positioned at a side relative with first substrate, and wherein, described the first alignment film and the second alignment film are fit-state in the position of support column.
12. liquid crystal indicator according to claim 1; it is characterized in that: described first substrate is array base palte; described second substrate is color membrane substrates; and described first substrate also comprise crisscross sweep trace and data line, the gate insulator between sweep trace and the data line, between data line and pixel electrode across the protection insulation course, described support column is positioned on the protection insulation course.
13. the liquid crystal indicator of stating according to claim 11 is characterized in that: described first substrate is provided with viewing area and lightproof area, and described support column is located in the lightproof area; Described second substrate also comprises look resistance layer and black matrix", the black matrix" of the corresponding second substrate of support column.
14. the liquid crystal indicator of stating according to claim 12, it is characterized in that: the pixel electrode of first substrate and the transparency conducting layer of second substrate form memory capacitance in the zone of support column position, and described pixel electrode and transparency conducting layer are as the parallel-plate electrode of memory capacitance.
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| CN103235437A (en) * | 2013-04-27 | 2013-08-07 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display device and manufacturing method thereof |
| CN103488005A (en) * | 2013-09-29 | 2014-01-01 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal panel |
| CN103744230A (en) * | 2013-12-31 | 2014-04-23 | 南京中电熊猫液晶显示科技有限公司 | LCD (Liquid Crystal Display) panel and manufacturing method |
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| CN108957892A (en) * | 2018-08-31 | 2018-12-07 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| WO2019041954A1 (en) * | 2017-08-30 | 2019-03-07 | 京东方科技集团股份有限公司 | Display panel, manufacturing method therefor, and display device |
| WO2019095459A1 (en) * | 2017-11-17 | 2019-05-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
| CN111047986A (en) * | 2019-11-27 | 2020-04-21 | 南京中电熊猫平板显示科技有限公司 | Display panel |
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| CN103488005B (en) * | 2013-09-29 | 2016-05-25 | 南京中电熊猫液晶显示科技有限公司 | A kind of liquid crystal panel |
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| CN106464809A (en) * | 2014-05-29 | 2017-02-22 | 奥林巴斯株式会社 | Image pickup apparatus and image processing method |
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| CN107203063A (en) * | 2016-03-18 | 2017-09-26 | Jsr株式会社 | Substrate for display device, the manufacture method of substrate for display device and display element |
| CN107203063B (en) * | 2016-03-18 | 2022-04-05 | Jsr株式会社 | Substrate for display element, method for manufacturing substrate for display element, and display element |
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| US11127803B2 (en) | 2017-08-30 | 2021-09-21 | Boe Technology Group Co., Ltd. | Display panel and display device |
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| US11079639B2 (en) | 2018-08-31 | 2021-08-03 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel |
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