CN103051336B - Frequency Synthesizer and Frequency Synthesis Method - Google Patents

Abstract

A frequency synthesizer includes an oscillator for providing a radio frequency clock, a phase shifter for phase-shifting a frequency reference clock to provide a shifted reference clock, and a time-to-digital converter for quantizing a time difference between the radio frequency clock and the shifted reference clock to generate a digital conversion output; wherein, the range covered by the time-to-digital converter is less than a complete period of the RF clock. The invention also provides a frequency synthesis method. The invention can effectively reduce the complexity of hardware.

Description

Frequency Synthesizer and Frequency Synthesis Method

【Technical field】

The present invention relates to a frequency synthesizer and a frequency synthesis method, and in particular to a frequency synthesizer and a frequency synthesis method including time-to-digital conversion supporting peripheral mechanisms.

【Background technique】

Various communication systems, such as radio frequency (RF, Radio Frequency) wireless communication systems, have been widely used in modern information society and play an important role. One of the core technologies of modern communication systems is frequency (and/or clock) synthesis, which generates a variable clock with a desired frequency based on a frequency reference clock, so that the stability, accuracy and spectral purity of the variable clock Both are related to the behavior of the frequency reference clock. In the transmitter of the communication system, the variable clock provided by a local frequency synthesizer can be used as a local oscillator carrier to up-convert the baseband or intermediate-frequency (IF, Intermediate-Frequency) signal ) frequency shift to form a corresponding radio frequency signal. On the other hand, in the receiver, the variable clock provided by a local frequency synthesizer can be used as a local oscillator carrier to down-convert the RF signal to an IF/baseband signal.

【Content of invention】

In view of this, it is necessary to provide a frequency synthesizer and a frequency synthesis method.

An embodiment of the present invention provides a frequency synthesizer comprising a frequency reference input for receiving a frequency reference clock, a trimmed oscillator for providing a radio frequency clock, a frequency reference input coupled to the frequency reference input, A phase shifter for changing the phase of the frequency reference clock, and a time-to-digital converter coupled to the phase shifter and the trimmed oscillator to generate a digital conversion output; wherein, the time-to-digital converter needs to cover A range is less than a full cycle of the RF clock.

In one embodiment, the phase shifter is a digital-to-time converter for delaying the frequency reference clock in response to a switching digital control. In one embodiment, the switching digital control is set in response to an accumulated value of a frequency command character, and the phase shifter changes the phase of the frequency reference clock in response to the accumulated value (eg, fractional portion) of the frequency command character.

In one embodiment, the frequency synthesizer further includes a translation controller, a variable phase accumulator and a reference phase accumulator. The variable phase accumulator is coupled to the fine-tuned oscillator for accumulating the number of cycles of the radio frequency clock to provide a variable phase signal. The reference phase accumulator is used for accumulating frequency command characters in response to each cycle of the frequency reference clock, and accordingly providing an accumulated value of the frequency command characters. The translation controller is coupled to the phase translator and is used for providing a translation control signal (such as the conversion digital control) and an auxiliary fractional error correction signal in response to the accumulated value of the frequency command character. A phase shifter is used to change the phase of the frequency reference clock in response to a shift control signal, and a trimmed oscillator is used to adjust the period of the RF clock based on the accumulated value of the digital conversion output, the auxiliary fractional error correction signal, the variable phase signal, and the frequency command character .

In one embodiment, the phase shifter changes the phase of the frequency reference clock and accordingly provides a shifted reference clock such that the time difference between a transition of the shifted reference clock and a previous transition of the radio frequency clock is less than one of the radio frequency clock transitions. full cycle. In one embodiment, for the range of time-to-digital conversion, the time-to-digital converter responds when the transition of the RF clock and the transition of the translation reference clock occur close to the range, and when the transition of the RF clock There is no response when the transition to the shift reference clock does not occur close to this range.

An embodiment of the present invention provides a frequency synthesizer, including an oscillator, a phase shifter, a time-to-digital converter, a translation controller, a reference phase accumulator and a variable phase accumulator. The oscillator is used to provide a variable clock. The phase shifter is used to provide a shifted reference clock whose phase is different from that of a frequency reference clock by a phase shift amount. The difference in time is less than one period of the variable clock. The time-to-digital converter is coupled to the phase shifter for quantizing the time difference to provide a first fractional error correction signal.

The reference phase accumulator is used to accumulate a frequency command character in response to each cycle of the frequency reference clock, and accordingly provide a reference phase signal; the variable phase accumulator is coupled to the oscillator, and is used to accumulate the number of cycles of the variable clock to provide a variable phase signal. The translation controller is coupled to the phase shifter for providing a translation control signal and a second fractional error correction signal in response to the reference phase signal, so that the phase shifter responds to the translation control signal to set the phase shift amount, and the oscillator is based on the first The period of the variable clock is adjusted by the first fractional error correction signal, the second fractional error correction signal, the reference phase signal and the variable phase signal.

An embodiment of the present invention provides a frequency synthesizer, including an oscillator, a time-to-digital converter, a translation controller, a phase shifter, a reference phase accumulator and a variable phase accumulator. The oscillator is used to provide a variable clock, and according to a first fractional error correction signal provided by the time-to-digital converter, a second fractional error correction signal provided by the translation controller, a variable phase signal provided by the variable phase accumulator and the reference phase A reference phase signal provided by the accumulator adjusts the period of the variable clock. a time-to-digital converter for quantizing the time difference between a shifted reference clock and the variable clock, wherein the phase of the shifted reference clock differs from the phase of a frequency reference clock by a phase shift amount and thereby providing a first fractional error correction signal . The translation controller is used for providing a second fractional error correction signal in response to an accumulated value of a frequency command.

An embodiment of the present invention provides a method for synthesizing a frequency by providing a variable clock, including: generating a variable clock in response to an oscillator adjustment signal; shifting the phase of a frequency reference clock by a phase shift amount to obtain a shift a reference clock; and, digitizing the time difference between the variable clock and the translational reference clock, the digitization covering a range less than a full period of the variable clock.

In one embodiment, the method of the present invention further includes: adjusting the phase shift amount, so that the time difference between the first transition of the translation reference clock and the previous transition of the variable clock is less than or equal to the first transition of the frequency reference clock and the variable clock The time difference between the previous transitions of .

In one embodiment, the method of the present invention further includes: accumulating a frequency command character according to each cycle of the frequency reference clock to obtain the cumulative value of the frequency command character, and adjusting the phase shift amount according to the fractional part of the cumulative value of the frequency command character; The digitization obtains a first fractional error correction signal, obtains a second fractional error correction signal according to the phase shift, and adjusts the oscillator adjustment signal according to the first and second fractional error correction signals.

The above frequency synthesizer and frequency synthesis method can effectively reduce hardware complexity.

【Description of drawings】

FIG. 1 illustrates an embodiment of digitally tracking the phase of a variable clock and a frequency reference clock.

Figure 2 illustrates an embodiment of a time-to-digital converter.

3 and 4 respectively illustrate a frequency synthesizer and its operation according to an embodiment of the present invention.

5 and 6 respectively illustrate a frequency synthesizer and its operating principle according to an embodiment of the present invention.

FIG. 7 and FIG. 8 respectively show a frequency synthesizer and its operation according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a frequency synthesizer according to an embodiment of the present invention.

FIG. 10 schematically shows an embodiment of the power management circuit of the present invention shown in FIG. 9 .

FIG. 11 schematically shows an embodiment of the power management circuit of the present invention shown in FIG. 9 .

FIG. 12 illustrates various operations of the power management circuit in schematic diagram 11 according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of implementing the level sensing circuit in FIG. 11 according to an embodiment of the present invention.

【detailed description】

Please refer to FIG. 1 , which illustrates a conceptual embodiment of digitally tracking the phases of two clocks CKV and FREF, so that the frequency of the clock CKV is the frequency of the clock FREF multiplied by a frequency command character FCW. That is, by setting a corresponding frequency command character FCW, a clock CKV with a desired frequency can be generated based on the clock FREF. Clock FREF is a frequency reference clock with period Tr. The clock CKV is a variable clock with a period Tv, which is generated by an oscillator 10, such as a digitally controlled oscillator (DCO, Digitally Controlled Oscillator). For frequency synthesis, the oscillator 10 is fine-tuned so that the clock CKV is locked to a clock CKR, and the frequency of the clock CKV approaches the product of the clock FREF and the frequency command character FCW, that is, the average period Tv is equal to Tr/FCW. The frequency command character FCW can generally refer to a real number, which has an integer part and a fractional part; in the example in Figure 1, the frequency command character FCW is 9/4, its integer part is 2, and its fractional part is then equal to 1 /4.

In order to measure the phase of the clock CKV digitally, a signal (eg a digital character) PHV[i] is provided. Signal PHV[i] can be viewed as a variable phase signal that accumulates a unit count at each key transition (eg rising edge) of clock CKV; that is, PHV[i+1]=PHV[i]+ 1. The subscript i is a timing mark, representing the i-th key transition point of the clock CKV. That is to say, as time goes by, the variable phase signal PHV[i] accumulates the number of cycles of the clock CKV to reflect the phase of the clock CKV in units of cycle Tv. The value of the signal PHV[i] is an integer because it is accumulated by integers.

In order to digitally measure the phase of the clock FREF, the phase information of the clock FREF will be presented synchronously at the critical transition of the clock CKV, so that the phase information of the clock FREF can be compared with the signal PHV[i], because the signal PHV[i] It is also updated at key transitions of the clock CKV. Therefore, the clock FREF is retimed to the clock CKR by a retimer 12 (eg, a flip-flop). The retimer 12 is used to retime the clock FREF at each key transition of the clock CKV, thereby providing the clock CKR (i.e. a retiming reference clock), so that each transition of the clock CKR will be consistent with one of the clock CKV Alignment at key transitions. In response to the toggling of clock CKR, a signal PHR[k] may be provided to digitally reflect the phase of clock FREF. The signal PHR[k] is a reference phase signal, which accumulates the frequency command character FCW at each key transition of the clock CKR, that is, PHR[k+1]=PHR[k]+FCW, and the subscript k is a timing mark , representing the kth key transition of the clock CKR.

According to the expected relationship of frequency synthesis, the period Tr of the clock FREF should be the period Tv of the clock CKV multiplied by the frequency command character FCW. Therefore, the accumulated frequency command character FCW in each period of the clock CKR is used to reflect the cycle Tv as a unit. Phase of clock FREF. Since the frequency command character FCW can have a fractional part, the signal PHR[k] can also have a fractional part.

Because the clock CKR is retimed by the clock CKV, each key transition of the clock CKR will be aligned with a key transition of the clock CKV, and the signal PHV[k], that is, the signal PHV[i] is at the kth of the clock CKR The value at a key transition point can be compared with the signal PHR[k]. In the example of FIG. 1 , the signal PHV[i0] is aligned with the signal PHR[k0], the signal PHV[i0+3]=PHV[k0+1] is synchronized with the signal PHR[k0+1], and so on. As shown in Fig. 1, retiming the clock FREF to the clock CKR under the trigger of the clock CKV will cause an error e[k], which represents a key transition of the clock FREF to the next key transition of the clock CKV (ie The time difference (phase error) between the closest clock CKV key transition) after this key transition of clock FREF.

In the example of FIG. 1, when the clock CKV locks the clock FREF according to the predicted relationship Tv=Tr/FCW, every four periods Tr will be aligned with nine periods Tv, because FCW=9/4. That is, accumulating the frequency command character FCW four times is equal to accumulating the unit count nine times, because FCW*4=(9/4)*4=1*9. Assuming that the key transitions of the clock FREF and CKV are aligned at the time mark k0 so that the signals PHR[k0] and PHV[i0] are equal, then after four cycles of the clock CKR, the key transitions of the clock FREF and CKV will be again Alignment, and the value of the signal PHR[k0+4] will also conform to the value of the signal PHV[i0+9] (ie PHV[k0+4]), because PHR[k0+4]=PHR[k0]+FCW*4 , and PHV[i0+9]=PHV[i0]+1*9. On the other hand, since the frequency command character FCW has a fractional part, even though the clock CKV has locked the clock FREF, at each time mark k between the time mark k0 and (k0+4), a key transition of the clock FREF The time difference to the next critical transition of the clock CKV will still be non-zero; this time difference will be reflected as the difference between the values of the signals PHV[k] and PHR[k]. For example, when the clock CKV locks the clock FREF, at the time mark (k0+1), the key transition of the clock FREF will be ahead of the next key transition of the clock CKV by a time difference of (3/4)*Tv , and the numerical difference (PHV[k0+1]-PHR[k0+1])=(3-9/4)=3/4 between the signal PHV[k0+1] and PHR[k0+1] reflects This time difference. Similarly, the misaligned time difference (1/2)*Tv between clock FREF and key transitions of CKV at time stamp (k0+2) is reflected as (PHV[k0+2]-PHR[k0+ 2])=(5−18/4)=2/4=1/2.

As the time mark k advances with time, the difference between the signal PHV[k] and PHR[k] (PHV[k]-PHR[k]) will change periodically and regularly, reflecting the clock FREF and CKV in units of period Tv The deterministic (non-random) time difference between two clocks (that is, the time difference between the key transitions of two clocks) (phase error). Therefore, the difference (PHV[k]−PHR[k]) becomes a deterministic part of the error e[k], which reflects the regular phase difference caused by the fractional part of the frequency command character FCW. That is, when the clock CKV is locked to the clock FREF, the error e[k] will be equal to (PHV[k]-PHR[k]), or equivalently, PHR[k]+e[k]-PHV[k]=0 .

The regular misalignment difference between the key transition of clock FREF to the next key transition of clock CKV will fall within the range of one period Tv; equivalently, the difference (PHV[k]-PHR[k ]), the deterministic part of the error e[k], will be a fractional number (or equal to zero). Since the signal PHV[k] is an integer, the deterministic part of the error e[k] will be related to the fractional part of the signal PHR[k]. In terms of practical application, the error e[k] also includes a variable part of random nature, which reflects the random phase error caused by noise (such as the noise of the oscillator 10 ).

More generally, assuming that the frequency command character can be expressed as Nv/Nr, Nv and Nr are both integers but Nv is not an integer multiple of Nr, then the deterministic part of the error e[k] will be in every Nr cycles of the clock CKR Repeat regularly, that is, the deterministic part of the error e[k] is equal to e[k+Nr], and can be based on the fractional part of the cumulative value of the frequency command character FCW (that is, the signal PHR[k]) and The signal PHV[k] is predicted. Assuming that the signal PHV[k0] is equal to PHR[k0] at the time mark k0, if the oscillator 10 is adjusted so that the integer part of the signal PHR[k] is separated by Nr cycles of the clock CKR (that is, at the time mark k0, ( k0+Nr) and so on) coincide with the integer signal PHV[k], implying the achievement of frequency locking. However, since the Nr periods of the clock CKR cover many periods of the clock CKV, if the error e[k] cannot be completely monitored in every Nr periods of the clock CKR, the period Tv of the clock CKV will drift. In order to achieve fine phase locking, a time-to-digital converter can be used to digitally detect the error e[k] at each cycle of the clock CKR, so that the oscillator 10 can be adjusted according to the digital conversion output of the time-to-digital converter , to ensure that (PHR[k]+e[k]-PHV[k]) approaches zero at each time stamp k.

Please refer to FIG. 2 , which illustrates an embodiment of a time-to-digital converter 20 . The time-to-digital converter 20 is coupled to the two input terminals 22 a and 22 b to receive two signals TDC_in and REF_in respectively; the time-to-digital converter 20 also outputs a signal et[k] as a digital conversion output. When the time-to-digital converter 20 is used to detect the error e[k] in FIG. 1 , the clocks FREF and CKV are received as signals REF_in and TDC_in, respectively. Preferably, the time-to-digital converter 20 is used to digitize (quantize) the time difference dt between a key transition point 16b of the signal REF_in and the next key transition point 16c of the signal TDC_in, so that the error e[k] can be determined by the digital signal et[k] stands for . In one embodiment, the time-to-digital converter 20 is a causal system; therefore, it cannot predict the next rising edge 16c of the signal TDC_in after the rising edge 16b of the signal REF_in. Thus, the desired error measurement is achieved indirectly by subtracting the time tr from the period Tv. In one embodiment, the rise time tr between the key transition point 16a of the signal TDC_in and the subsequent key transition point 16b of the signal REF_in will be measured and quantified; since dt=(Tv-tr), the error e[k] It can be deduced as: e[k]=(dt/Tv)=(1-(tr/Tv)). In this embodiment, the time-to-digital converter 20 does not directly generate the error e[k], but the quantized value of the time tr, which is divided by the period Tv, or multiplied by 1/Tv_avg, where the average period Tv_avg is the long-term average of the period Tv of the variable clock CKV. Therefore, the direct output of the time-to-digital conversion is the quantized value of tr/Tv, which corresponds to the negative value of the error e[k]. As will be appreciated by those skilled in the art, negative-valued operations are readily accomplished by changing the sign at the input to adder 50 (discussed in FIG. 3 ). Thus, minimizing the difference time tr between the two input signals REF_in and TDC_in is equivalent to maximizing the error e[k] (but its value will not be greater than 1). In the formula (1-e[k]), since the constant 1 can be easily absorbed in the phase-locked loop system (PLL system), (1-e[k]) can be conveniently written as (-e[k] ]). That is, for the key transition point 16b of the signal REF_in and the two adjacent key transition points 16a and 16c of the signal TDC_in, the time difference between the key transition point 16b and the subsequent key transition point 16c can be represented by the error e[k] , the time difference between the key transition point 16b and the previous key transition point 16a can be represented by the error (-e[k]), both of which can be used to track the time difference (phase difference) between the signal REF_in and TDC_in, so it can be Depending on the convenience of the application, choose to use it.

An embodiment of the time-to-digital converter 20 includes a plurality (L) of delay units 18 (such as inverters) connected in series, a plurality of flip-flops 24 triggered by the signal REF_in, and a code edge detector (code edge detector) 26. Each delay unit 18 can introduce a unit delay time t_inv into the signal TDC_in, and output to a corresponding flip-flop 24 and the next delay unit 18 . When the important transition of the signal REF_in triggers each flip-flop 24 to obtain a number formed by bits Q(1), Q(2)...Q(L), the occurrence of the important transition 16a will be reflected as A code edge between bits Q(1) to Q(L); accordingly, the code edge detector 26 will quantize the rising time tr with the unit delay time t_inv, and output it as a signal et[k ]. That is, the time quantization resolution of the time-to-digital converter 20 depends on the unit delay time t_inv of each delay unit 18 . The total number L of delay units 18 determines the measurement range of the time-to-digital converter 20 , and the time-to-digital conversion range can be estimated as L*t_inv. Time intervals shorter than the time-to-digital conversion range can be detected, while time intervals longer than the time-to-digital conversion range cannot be detected by the time-to-digital converter 20 . When the time-to-digital converter 20 is used to detect the error e[k] in FIG. 1 , the range of the time-to-digital converter should completely cover a period Tv.

In order to detect the error e[k] with a finer resolution to improve the characteristics of the clock CKV, the unit delay time t_inv should be much smaller than the period Tv. Concurrently, the total number L of delay units 18 required by the time-to-digital converter 20 becomes extremely large, so that the time-to-digital conversion range is sufficient to cover the period Tv. For example, to cover a period of 2.4 GHz at 7 ps (1 ps is a millionth of a millionth of a second), about 60 delay units 18 are needed to implement the time-to-digital converter 20 . The more delay units 18 are used, the more power is consumed, and the resulting power supply disturbance (such as variation and/or reduction of supply voltage) is also more serious. To stabilize severe power supply disturbances, large-area decoupling capacitors are required, which increases the area required to implement an effective time-to-digital converter. Furthermore, severe power supply disturbance will also reduce the linearity of the time-to-digital conversion, because the unit delay time t_inv will drift with the supply voltage variation. Therefore, supporting peripheral technologies are needed to reduce the number of required delay units and improve the linearity of time-to-digital conversion.

Please refer to FIG. 3 , which shows a frequency synthesizer 30 according to an embodiment of the present invention. The frequency synthesizer 30 includes a frequency command character input 32a for receiving a frequency command character FCW, a frequency reference input 32b for receiving a frequency reference clock FREF, a reference phase accumulator 34, a variable phase accumulator device 36 , a loop filter 38 , an oscillator 10 , a phase shifter 46 , a shift controller 42 , a time-to-digital converter 40 , an adder 50 and a retimer 12 . The oscillator 10 is used to provide a variable clock CKV according to an oscillator adjustment character OTW, such as a radio frequency clock, so that the frequency of the variable clock CKV will be equal to the frequency command character FCW multiplied by the frequency when the variable clock CKV is locked to the frequency reference clock FREF Reference clock FREF.

The retimer 12 is coupled to the oscillator 10 and the frequency reference clock FREF for retiming the frequency reference clock FREF at critical transitions (eg rising edges) of the variable clock CKV to provide a retiming reference clock CKR. The reference phase accumulator 34 is coupled to the frequency reference clock FREF via the frequency reference input terminal 32b, and is used for accumulating the frequency command character FCW according to each cycle of the frequency reference clock FREF (for example, at each key transition of the retiming reference clock CKR), Accordingly, a reference phase signal PHR[k] is provided. In FIG. 3 , the reference phase signal PHR[k] can be decomposed into a fractional part PHRf[k] and an integer part PHRi[k]. The variable phase accumulator 36 is coupled to the oscillator 10 for accumulating the number of periods of the variable clock CKV to provide a variable phase signal PHV[k].

The phase shifter 46 is coupled to the oscillator 10 and the shift controller 42, and is used for changing the phase of the variable clock CKV according to a shift control signal SEL, so as to provide a shifted variable clock CKV'. Alternatively, the phase shifter 46 can select one of multiple phases of the variable clock CKV to change the phase. The multiple phases can be generated inside the phase shifter 46 . The function of the time-digital converter 40 is similar to that of the time-digital converter 20 shown in FIG. ' are received as signals REF_in and TDC_in respectively, and provide a fractional error correction signal PHF1[k] according to the time difference between the frequency reference clock FREF and the shift variable clock CKV'. That is, the time-to-digital converter 40 is used to detect (quantize) the time difference between a key transition of the frequency reference clock FREF and the previous key transition of the translation variable clock CKV', and use a signal et[k ] reflects the detected time difference; and the fractional error correction signal PHF1[k] measures the time difference in units of the period Tv of the variable clock CKV, which is obtained by normalizing the signal et[k] to an average period Tv_avg; Wherein, the average period Tv_avg is the long-term average of the period Tv of the variable clock CKV, because the period Tv can generally refer to a temporal variable.

To cooperate with the phase shifter 46 , the shift controller 42 is coupled to the phase shifter 46 for providing the shift control signal SEL and another fractional error correction signal PHF2 [k]. The adder 50 is coupled to the variable phase accumulator 36, the reference phase accumulator 34, the translation controller 42 and the time-to-digital converter 40, and is used for correcting the fractional error according to the reference phase signal PHR[k], the variable phase signal PHV[k] The numerical combination of signals PHF1[k] and PHF2[k] (PHR[k]+PHF1[k]+PHF2[k]−PHV[k]) provides a signal PHE[k]. The loop filter 38 is coupled between the oscillator 10 and the adder 50 for providing the oscillator adjustment character OTW according to the signal PHE[k]. Through the oscillator adjustment character OTW, the oscillator 10 is equivalent to adjusting the variable clock CKV according to the reference phase signal PHR[k], the variable phase signal PHV[k], and the fractional error correction signals PHF1[k] and PHF2[k] the length of the cycle.

Please refer to FIG. 4 , which illustrates the time-to-digital conversion operation of the frequency synthesizer 30 according to an embodiment of the present invention. The phase shifter 46 (FIG. 3) is used to introduce a phase shift PHoffset between the variable clock CKV and the shifted variable clock CKV'. Due to this phase shift amount PHoffset, the error (1-e[k]) between the frequency reference clock FREF and the previous variable clock CKV will be reduced to a smaller error (1-e'[k]), that is, the frequency will be reduced The difference time between the reference clock FREF and the shift variable clock CKV'; where -e[k]=-e'[k]+PHoffset. In other words, the phase shift amount PHoffset is used to make the time difference between the key transition point of the frequency reference clock FREF and the previous key transition point of the translation variable clock CKV' much smaller than one period Tv of the variable clock CKV; that is, to make the error - e'[k] will not be greater than a fraction of the period Tv. Since the translational variable clock CKV' and the frequency reference clock FREF are respectively received as signals TDC_in and REF_in, the time-to-digital converter only needs to quantize an error -e'[k] which is significantly smaller than the period Tv. That is, the time-to-digital conversion range of the time-to-digital converter 40 only needs to cover a part of a single period Tv, and does not need to completely cover the entire period Tv. Equivalently speaking, the time-to-digital converter 40 responds only when a key transition of the translation variable clock CKV' and a key transition of the frequency reference clock FREF occur close to the time-to-digital conversion range; When an important transition of the translation variable clock CKV' and an important transition of the frequency reference clock FREF do not occur close to the time-to-digital conversion range, the time-to-digital converter does not need to respond. Since the time-to-digital conversion range can be reduced, the time-to-digital converter 40 only needs a smaller number of delay units; therefore, without sacrificing the resolution of the time-to-digital conversion, the hardware complexity, power consumption, and occupied space of the time-to-digital converter 40 The layout area, power supply interference and nonlinearity can also be effectively reduced.

As discussed in FIG. 1, the error e[k] includes a time-varying but predictable deterministic component, corresponding to (PHR[k]-PHV[k]). Based on the deterministic part of the regular change in the error-e[k], the translation controller 42 will dynamically set the phase translation amount PHoffset with the translation control signal SEL, so that the phase translation amount can be determined from the error-e[k] Partially subtracted to form the error -e'[k]. For example, when the deterministic part of the error -e[k] is expected to fall in the range of 1/4 (equivalent to a phase of 90 degrees) to 1/2 (180 degrees), the phase shift amount PHoffset can be It is set to 90 degrees (equivalent to 1/4), so that the error -e'[k] will be maintained in the range of 0 to 1/4. Similarly, as time goes by, when the deterministic part of the error -e[k] will enter the range of 1/2 to 3/4, the phase shift amount PHoffset is also set to 180 degrees (that is, the period 1/2 of Tv), so that the error -e'[k] is still maintained in the range of 0 to 1/4. In order to compensate for the subtracted phase shift amount PHoffset, the translation controller 42 will inject a fractional error correction signal PHF2[k] into the adder 50 to reflect the phase shift amount PHoffset; since the fractional error correction signal PHF1[k] represents the quantization error -e'[k], so the error -e[k] can be calculated as: -e[k]=(PHF1[k]+PHF2[k]), corresponding to -e[k]=(-e'[k ]+PHoffset). Thus, when the oscillator 10 adjusts the period of the variable clock CKV to minimize the signal PHE[k] (that is, (PHR[k]-PHV[k]+e[k])=(PHR[k]-PHV When [k]+PHF1[k]+PHF2[k]) is minimized, the second type of phase-locked loop is assumed here), frequency synthesis can be achieved. In other words, the frequency synthesizer 30 can be compared to an All-Digital Phase Lock Loop (ADPLL, All-Digital Phase Lock Loop).

In one embodiment, the integer variable phase signal PHV[k] is a fixed point digital character formed by WI bits. The reference phase signal PHR[k] is also a fixed-point digital character, formed by (WI+WF) bits, including an integer part of WI bits and a fractional part of WF bits. The two decimal error correction signals PHF1[k] and PHF2[k] can respectively use fixed-point numeric characters of WF bits to represent decimals. The signal PHE[k] is a signed fixed-point digital character with (WI+WF) bits, including an integer part of WI bits and a fractional part of WF bits.

Please refer to FIG. 5 , which illustrates a phase shifter 46 according to an embodiment of the present invention. In FIG. 5 , the phase shifter 46 includes a frequency divider 44 and a phase selector 48 . The frequency divider 44 is coupled to the oscillator 10 to divide the frequency of the variable clock CKV to provide a plurality of candidate translation clocks CKVp(1), CKVp(2), . . . , CKVp with different phases according to the variable clock CKV (n) to CKVp(Np). For example, the phase of the candidate translation clock CKVp(n) may differ from the phase of the candidate translation clock CKVp(1) by (n−1)*360/Np degrees. The phase selector 48 is coupled to the frequency divider 44 and the translation controller 42, and is used for selecting one of the candidate translation clocks CKVp(1) to CKVp(Np) as the translation according to the translation control signal SEL of the translation controller 42. Variable clock CKV'.

In one embodiment, the frequency divider 44 is used to divide the frequency of the variable clock CKV by two, so as to provide four candidate translation clocks CKVp(1) to CKVp(4) of quadrature phase; that is, The phase shift between the candidate shifted clock CKVp(n) and the variable clock CKV is 90*(n−1) degrees, for n=1 to 4. Please refer to FIG. 6 , which illustrates the quadrature-based TDC operation. Originally, the complete distribution range of the error -e[k] is 360 degrees (that is, one period Tv of the variable clock CKV), but since one of the four quadrature phases will be selected as the translational variable clock CKV', the error -e The range of [k] is mapped to a smaller range of error -e'[k], which is only 90 degrees, ie a quarter of the period Tv.

For example, when it is predicted that the error -e[k] will enter the range S0 from 0 to 90 degrees according to the fractional part PHRf[k] of the reference phase signal PHR[k], the translation controller 42 will select the candidate translation clock CKVp(1) is selected as the translation variable clock, so that the error -e'[k] will also be in the range of 0 to 90 degrees; the translation controller 42 will also correct the decimal error signal PHF2[k] equivalent to 0 degrees into the adder 50. When the error -e[k] is expected to enter the range S1 from 90 degrees to 180 degrees, the translation controller 42 will instead select the candidate translation clock CKVp(2) with a phase of 90 degrees as the translation variable clock CKV', so that the error -e' [k] is still limited to the range of 0 to 90 degrees. Correspondingly, the translation controller 42 also injects a fractional error correction signal PHF2 [k] equivalent to 90 degrees (1/4 when the period Tv is used as a unit) to the adder 50 .

Similarly, when the error -e[k] is about to enter the range S2 of 180 to 270 degrees, the candidate translation clock CKVp(3) which is 180 degrees different from the candidate translation clock CKVp(1) will be selected, so that the error - e′[k] remains in the range of 0 to 90 degrees; the fractional error correction signal PHF2[k] equivalent to 180 degrees (value 1/2) is also injected into the adder 50 . When the error -e[k] is expected to enter the range S3 from 270 degrees to 360 degrees, the candidate translation clock CKVp(4) which is 270 degrees different from the candidate translation clock CKVp(1) will be selected, so that the error -e' [k] can still be maintained in the range of 0 to 90 degrees; to compensate for the 270 degree phase shift subtracted from the error -e[k], the fractional error correction signal PHF2[k] equivalent to 270 degrees will be into the adder 50.

As shown in FIG. 5, since the time-to-digital converter 40 is used to detect the error -e'[k] instead of the error -e[k], the time-to-digital conversion range of the time-to-digital converter 40 only needs to cover 0 to 90 degrees , that is, a quarter of the period Tv of the variable clock CKV, not a complete period Tv.

From the embodiments shown in FIGS. 3 to 6 , it can be seen that the present invention can provide supporting peripherals for the time-to-digital converter 40 , including a phase shifter 46 and a shift controller 42 . Since the regularly time-varying deterministic part of the error -e[k] can be predicted based on the fractional part of the reference phase signal PHR[k], a corresponding phase shift PHoffset can be dynamically set, and its Subtracting from the error -e[k] provides another error -e'[k] such that the error -e'[k] is spread over less than a full period Tv. Therefore, the time-to-digital conversion range required by the time-to-digital converter 40 can be reduced, so that the time-to-digital converter 40 can benefit from lower hardware complexity (such as fewer delay units and/or decoupling capacitors), lower Low power consumption, small layout area, low power supply interference, and can improve the linearity of time-to-digital conversion without sacrificing the resolution of time-to-digital conversion. The translation controller 42 can be implemented with digital logic circuits.

Please refer to FIG. 7 , which shows a frequency synthesizer 60 according to an embodiment of the present invention. Similar to the frequency synthesizer 30 shown in Figure 3, the frequency synthesizer 60 in Figure 7 includes a frequency command character input 32a for receiving a frequency command character FCW, a frequency for receiving a frequency reference clock FREF Reference input 32b, a reference phase accumulator 34, a variable phase accumulator 36, a loop filter 38, an oscillator 10, a translation controller 62, a phase shifter 66, a time-to-digital converter 40, a An adder 50 and a retimer 12 . The oscillator 10 provides a variable clock CKV according to an oscillator adjustment character OTW, such as a radio frequency clock, so that the frequency of the variable clock CKV is equal to the frequency command character FCW multiplied by the frequency reference clock FREF when the variable clock CKV locks the frequency reference clock FREF frequency. In the frequency synthesizer 60, the operation and function of the reference phase accumulator 34, the variable phase accumulator 36, the time-to-digital converter 40, the adder 50 and the retimer 12 can be deduced from the same elements in the frequency synthesizer 30 of FIG. 3 Know. The variable phase accumulator 36 is coupled to the oscillator 10 for accumulating a unit count at each key transition of the variable clock CKV to provide a variable phase signal PHV[k]. According to the retiming reference clock CKR of the retimer 12, the reference phase accumulator 34 accumulates the frequency command character FCW in response to key transitions of the retiming reference clock CKR to provide a reference phase signal PHR[k].

The phase shifter 66, such as a digital-to-time converter (DTC, digital-to-time converter), is coupled to the frequency reference input terminal 32b and the time-to-digital converter 40, and is used for delaying the frequency reference clock FREF according to a translation control signal SEL (or change its phase), so as to provide a shift reference clock FREF'. The variable clock CKV and the translational reference clock FREF' are respectively input to the time-to-digital converter 40 as signals TDC_in and REF_in, so the time-to-digital converter 40 detects (quantizes) a key transition point between the translational reference clock FREF' The error -e'[k] (time difference) from the previous critical transition of the variable clock CKV, and accordingly provides a fractional error correction signal PHF1[k] as a response. In order to cooperate with the phase shifter 66, the shift controller 62 (for example, a digital time conversion compensator) is coupled to the phase shifter 66 and the adder 50 to operate according to the fractional part PHRf[ of the reference phase signal PHR[k]. k] to provide a translation control signal (such as a conversion digital control) SEL and another fractional error correction signal PHF2[k]. With the support of the translation controller 62 and the phase shifter 66, the time-to-digital conversion range of the time-to-digital converter 40 is smaller than a part of the period Tv of the variable clock CKV.

Please refer to FIG. 8 , which illustrates the coordinated operation of the phase shifter 66 , the shift controller 62 and the time-to-digital converter 40 . There is an error-e[k] between a key transition of the frequency reference clock FREF and the previous key transition of the variable clock CKV, and phase locking requires the relevant information of this error-e[k]; for this, The translation controller 62 dynamically adjusts the translation control signal SEL and the fractional error correction signal PHF2[k] according to the fractional part of the reference phase signal PHR[k], so that the translation control signal SEL and the fractional error correction signal PHF2[k] can follow The deterministic part of error-e[k] is updated. The phase shifter 66 is used to change the phase of the frequency reference clock FREF (equivalently delay) a phase shift amount PHdelay; this phase shift amount PHdelay is set according to the shift control signal SEL, which is used to shift the reference clock The error -e'[k] between an important transition of FREF' and the previous important transition of the variable clock CKV is less than a fraction of the period Tv and is also less than or equal to the error -e[k]. Equivalently, the phase shift amount PHdelay will be subtracted from the error -e[k] to form the error -e'[k]. Because the time-to-digital converter 40 only needs to quantize the smaller error-e'[k] rather than the error-e[k], the time-to-digital converter 40 can benefit from a smaller time-to-digital conversion range. The fractional error correction signal PHF2[k] is used to compensate the subtracted phase shift amount PHdelay, as shown in FIG. 7 and FIG. 8 .

For example, when the error -e[k] is in the range of 1/4 to 1/2, the translation controller 62 can preferably set the phase translation amount PHdelay as (1/4)*Tv, so that the time digital The error -e'[k] required to be measured by the converter 40 ranges from 0 to 1/4. When the error -e[k] is in the range of 1/2 to 3/4, the translation controller 62 can change the phase translation amount PHdelay to be preferably set to (1/2)*Tv, so that the time-to-digital converter 40 The required measurement error -e'[k] is still maintained in the range of 0 to 1/4 instead of the full range of 0 to 1. Because the time-to-digital converter 40 responds when a transition of the variable clock CKV and a transition of the translational reference clock FREF' occur close to the time-to-digital conversion range, when a transition of the variable clock CKV is at the same time as When a transition of the translation reference clock FREF' does not occur near the time-to-digital conversion range, no response is performed, so the hardware complexity of the time-to-digital converter 40 (such as the number of delay units required) can be effectively reduced, and there is Contributes to reduced power consumption, reduced power supply disturbance, and improved linearity.

In one embodiment, the frequency of the frequency reference clock FREF is much lower than that of the radio frequency variable clock CKV, so the phase shifter 66 only needs to operate at a low speed. In one embodiment, the phase shifter 66 is implemented as a digital-to-time converter for converting the digital shift control signal SEL (that is, converting digital control) into a phase shift value PHdelay (that is, a delay time). The digital-to-time converter can be implemented with a digitally programmable delay line. To ensure proper immunity against process, supply voltage, and temperature variations, frequency synthesizer 60 may include associated calibration mechanisms and/or routines for digital-to-time converters.

In the embodiments of Figs. 3, 5 and 7, oscillator 10 is a trimmed oscillator; it is tuned so that variable clock CKV tracks frequency reference clock FREF. The signal PHE[k] provided by the adder 50 is fed back to the oscillator 10 through the loop filter 38, so that the variable clock CKV can be further fine-tuned. In one embodiment, the loop filter 38 is a digital low pass filter. The loop filter 38 can be constructed by combining a finite impulse response (FIR, Finite Impulse Response) filter and an infinite impulse response (IIR, Infinite Impulse Response) filter. For example, in one embodiment, the loop filter 38 linearly combines the signal PHE and the accumulated value of the signal PHE to provide an oscillator tuning signal, making the frequency synthesizer a type-two loop.

In the embodiments of FIG. 3 , FIG. 5 and FIG. 7 , the time-to-digital converter 40 receives the high-speed translational variable clock CKV' (FIG. 3 and FIG. 5) or the variable clock CKV (FIG. 7) as the signal TDC_in, and receives the low-speed The frequency reference clock FREF (FIGS. 3 and 5) or the translation reference clock FREF' (FIG. 7) serves as the signal REF_in. The time-to-digital converter 40 quantizes the time difference between the signals TDC_in and REF_in, and updates the fractional error correction signal PHF1[k] at each key transition of the signal REF_in. However, no matter whether the update of the fractional error correction signal PHF1[k] is triggered or not, the time-to-digital converter 40 will continue to receive the high-speed toggling signal TDC_in. High-speed thixotropy consumes a lot of power, causing severe power supply disturbances, and consequently degrading the linearity of time-to-digital conversion. In order to solve this difficulty, the present invention uses a power management mechanism to suppress unnecessary pulses in the signal TDC_in, and only retains the closest single pulse at the next key transition ahead of the signal REF_in, thereby reducing power consumption and power supply interference, The normal time-to-digital conversion is also unaffected.

Please refer to FIG. 9 , which shows a frequency synthesizer 70 according to an embodiment of the present invention. Similar to the frequency synthesizers 30 and 60, the frequency synthesizer 70 includes a frequency command character input 32a for receiving a frequency command character FCW, a frequency reference input 32b for receiving a frequency reference clock FREF, and for generating a variable The oscillator 10 of the clock CKV is used to retime the frequency reference clock FREF at each key transition of the variable clock CKV to provide a retimer 12 for retiming the reference clock CKR, accumulating frequency command characters according to the retiming reference clock CKR FCW provides a reference phase accumulator 34 of a reference phase signal PHR[k], accumulates unit counts at each key transition of the variable clock CKV to provide a variable phase accumulator 36 of a variable phase signal PHV[k], for A time-to-digital converter 80 for quantizing the time difference between the signals TDC_in and REF_in to provide a fractional error correction signal PHF1[k], an adder 50 for providing the signal PHE[k], and a loop filter 38 for responding to The signal PHE[k] provides an oscillator adjustment character OTW to the oscillator 10 .

Furthermore, the frequency synthesizer 70 further includes a variable clock input 78a for receiving a signal TDC_in0, a frequency reference input 78b for receiving a signal REF_in0, a translation controller 72, a phase shifter 76 and a power management circuit 74 . The translation controller 72 is used to provide another fractional error correction signal PHF2[k] and a translation control signal SEL according to the fractional part PHRf[k] of the reference phase signal PHR[k], so that the adder 50 can convert the value difference ( PHR[k]-PHV[k]) is added to the numerical sum (PHF1[k]+PHF2[k]) to provide signal PHE[k]. The phase shifter 76 is coupled to the shift controller 72 for changing the phase of the variable clock CKV or the frequency reference clock FREF, and the signals TDC_in0 and REF_in0 are respectively provided according to the variable clock CKV and the frequency reference clock FREF. Power management circuit 74 is coupled to variable clock input 78a and frequency reference input 78b, and outputs signals REF_in and TDC_in; wherein signal TDC_in is provided as a single pulse in signal TDC_in0 that precedes the next key transition of signal REF_in place.

In one embodiment, the cooperative operation of the translation controller 72 and the phase shifter 76 is similar to the cooperative operation of the translation controller 42 and the phase shifter 46 ( FIG. 3 ); the phase shifter 76 responds to the translation control signal SEL to change the variable clock CKV The phase of is changed by a phase shift amount PHoffset, and accordingly a shift variable clock CKV' is provided as the signal TDC_in0. The shift controller 72 injects the fractional error correction signal PHF2[k] to compensate the phase shift PHoffset, and the frequency reference clock FREF is supplied to the power management circuit 74 as the signal REF_in0 .

In another embodiment, the cooperative operation of the translation controller 72 and the phase shifter 76 is similar to the cooperative operation of the translation controller 62 and the phase shifter 66 ( FIG. 7 ); the phase shifter 76 changes the frequency according to the translation control signal SEL The reference clock FREF is delayed by a phase shift amount PHdelay, thereby providing a shifted reference clock FREF' as the signal REF_in0. The shift controller 72 injects the fractional error correction signal PHF2[k] to compensate the phase shift PHdelay, and the variable clock CKV is provided to the power management circuit 74 as the signal TDC_in0 .

Through the cooperative operation of the translation controller 72 and the phase shifter 76, the time difference between the signals TDC_in0 and REF_in0 (that is, the error -e'[k]) is distributed within a range less than a complete period Tv.

Please refer to FIG. 10 , which shows a power management circuit 74A according to an embodiment of the present invention, which can be used to implement the power management circuit 74 shown in FIG. 9 . The power management circuit 74A includes two logic gates 82a and 82b, and a delayer (delay element) 82c. The logic gate 82 a is coupled to the signals REF_in0 and REF_in at two input terminals, and is used for providing a gating signal CON according to the result of a logical operation between the signals REF_in0 and REF_in (such as an inverse AND operation on the signal REF_in0 and the signal REF_in). The delayer 82c is coupled to the signal REF_in0 and the logic gate 82a for delaying the signal REF_in0 for a delay time Tdelay to provide the signal REF_in. The two input ends of the logic gate 82b are respectively coupled to the latch signal CON and the signal TDC_in0 for providing the signal TDC_in according to the result of the sum operation between the signal TDC_in0 and the latch signal CON.

When the signal REF_in0 transitions from logic 0 to logic 1 at a key transition point 84a, the logic gate 82a is used to set the latch signal CON to logic 1; when the signal REF_in transitions from logic 0 to logic 1 at the key transition point 84b 1. The logic gate 82a is used to set the latch signal CON back to logic 0. In this way, the latch signal CON will maintain a window of logic 1 during the delay time Tdelay between key transitions 84a and 84b. When the latch signal CON is logic 0, the logic gate 82b is used to suppress the pulse in signal TDC_in0; when the latch signal CON is logic 1, the logic gate 82b is used to follow the signal TDC_in0 to provide a single pulse 86a for the signal TDC_in, which will lead At 84b at the next key transition. In other words, when the signal TDC_in is provided according to the signal TDC_in0, only the single pulse 86a remains in the signal TDC_in, and other unnecessary pulses in the signal TDC_in0, such as pulses 86b and 86c, are suppressed by the latch signal CON. The signals REF_in and TDC_in are transmitted to the time-to-digital converter 80, and when the time-to-digital converter 80 detects (quantizes) the time interval THA between the key transition 84c of the pulse 86a and the next key transition 84b of the signal REF_in ) corresponding to the time difference, the error -e'[k] can be obtained.

By suppressing unnecessary pulses and retaining a single pulse before the next important transition of the signal REF_in, high-speed thixotropy to the time-to-digital converter 80 can be avoided, and the normal function of the time-to-digital converter 80 will not be affected; therefore , the power consumption can be effectively reduced, and the linearity of time-to-digital conversion will also be improved due to the suppression of power supply interference. Whether or not another pulse (or several) other pulses (such as pulse 86d) appear in signal TDC_in after the key transition 84b of signal REF_in, the correct operation of time-to-digital converter 80 will not be affected because time interval THA Will be measured (updated) before key transition 86d. However, other pulses in the signal TDC_in will have a negative impact on the operation of the voltage supply network, so these pulses are not ideal and should be blocked as much as possible.

Due to the coordinated operation of the translation controller 72 and the phase shifter 76, the length of the error -e'[k] between the signals TDC_in0 and REF_in0 will fall within the time-to-digital conversion range shorter than one cycle Tv, and the delay time Tdelay can be determined by It is set to be smaller than the period Tv. Conversely, if the length of the error-e'[k] is distributed in a complete cycle Tv, the delay time Tdelay must be longer than the cycle Tv, so as to ensure that the window of the delay time Tdelay can be longer in the error-e'[k] At least one key transition can still be captured in the signal TDC_in under the duration condition. However, if the delay time Tdelay is longer than the period Tv, its window will tend to catch multiple pulses in the signal TDC_in, and the linearity of the time-to-digital conversion will thus be reduced, because the redundant pulse before the important transition 84b will be in the measurement The time interval THA results in higher power supply disturbances.

For an appropriate setting value of the delay time Tdelay, the lower limit of the delay time Tdelay is the time-to-digital conversion range, and the upper limit is set to avoid excessive pulses before the critical transition point 84b. Therefore, the allowable variation of the delay time Tdelay is plus or minus (Tv/2-Tc)/2, where Tc represents the time-to-digital conversion range.

Please refer to FIG. 11 and FIG. 12 ; FIG. 11 illustrates another power management circuit 74B according to an embodiment of the present invention, and FIG. 12 illustrates the operation of the power management circuit 74B under two different conditions. The power management circuit 74B can be used to implement the power management circuit 74 shown in FIG. 9 . The power management circuit 74B includes two logic gates 82a and 82b, a delayer 82c and a level sensing circuit 82d. The two input terminals of the logic gate 82a are respectively coupled to the signals REF_in0 and REF_in for providing a latch signal CON according to the result of the logic operation between the signals REF_in0 and REF_in. The delayer 82c is coupled to the signal REF_in0 and the logic gate 82a for delaying the signal REF_in0 for a delay time Tdelay to provide the signal REF_in. Two input terminals of the level sensing circuit 82d are coupled to the signal TDC_in0 and the latch signal CON for providing another latch signal CON' according to the signal TDC_in0 and the latch signal CON. The two input terminals of the logic gate 82b are coupled to the latch signal CON' and the signal TDC_in0 for providing the signal TDC_in according to the result of an AND operation between the signal TDC_in0 and the latch signal CON'.

As shown in FIG. 12, when the signal REF_in0 changes from a logic 0 to a logic 1 at the key transition point 84a, the logic gate 82a is used to set the latch signal CON to a logic 1; 0 is turned into a logic 1, and the logic gate 82a is used to set the latch signal CON back to a logic 0. As shown in situation 1 of FIG. 12, when the latch signal CON changes from logic 0 to logic 1 at the transition point 90a, if the signal TDC_in0 is logic 0, the level sensing circuit 82d is used to set The latch signal CON' is set to logic 1. On the other hand, as shown in situation 2 of FIG. 12, when the latch signal CON changes from logic 0 to logic 1 at the transition point 90a, if the signal TDC_in0 is logic 1, the level sensing circuit 82d will wait for the signal TDC_in0 The latch signal CON' is set to a logic 1 at transition 90c only at a later transition back to a logic 0. The level sensing circuit 82d is further used to set the latch signal CON' back to logic 0 when the latch signal CON transitions back to logic 0. In other words, in the window when the latch signal CON is turned on during the delay time Tdelay, when the signal TDC_in0 is logic 0, the level sensing circuit 82d turns on a second window in the latch signal CON'.

When the latch signal CON' is logic 0, logic gate 82b is used to suppress pulses in signal TDC_in0, such as pulses 88a and 88b. When the latch signal CON' is logic 1, the logic gate 82b is used to follow the signal TDC_in0 to provide a single pulse 86a for the signal TDC_in, so that the signal TDC_in will only have a single key transition of the pulse 86a before the key transition point 84b of the signal REF_in State at 84c. The time-to-digital converter 80 can measure the time period between key transitions 84c and 84b to detect the error -e'[k]. In the signal TDC_in, since there is only a single pulse 86a before the critical transition point 84b, unnecessary tripping of the time-to-digital converter 80 can be avoided, and the linearity of the time-to-digital converter 80 can be improved.

As shown in situation 2 of FIG. 12 , if the pulse in the signal TDC_in0 is gated by the gate signal CON, there will be an extra pulse included in the signal TDC_in between the critical transition point 90a and the falling edge transition point 90d , and this extra pulse will degrade the linearity of the time-to-digital converter 80 . However, since the level sensing circuit 82d will adaptively avoid the period when the signal TDC_in0 is logic 1, the narrower window of the gate signal CON' can be used to eliminate redundant pulses; in this way, it can be ensured that there is only a single pulse to maintain linearity. Under the operation of the level sensing circuit 82d, the power management circuit 74B will be more robust and have better immunity to the delay time variation of the delay device 82c, because the allowable delay variation of the delay time Tdelay will be enlarged to be positive or negative (Tv-Tc)/2.

Please refer to FIG. 13 , which shows an example of the level sensing circuit 82d, which includes an inverter 94 and an SR latch formed by two NAND gates 92a and 92b. Two input terminals and an output terminal of the NAND gate 92 a are respectively coupled to the signal TDC_in0 , the node n0 and the node n1 . Two input terminals and an output terminal of the NAND gate 92b are respectively coupled to the latch signal CON, the node n1 and the node n0. The inverter 94 is coupled between the NAND gate 92b and the logic gate 82b. When the signal TDC_in0 is logic 1, the latch signal CON' is latched as logic 0, and when the signal TDC_in0 is logic 0, the latch signal CON' is released to follow the latch signal CON.

In conclusion, the present invention provides related supporting peripherals for the time-to-digital converter in the digital frequency synthesizer. When the time difference (phase error) between the variable clock and the frequency reference clock is monitored by a digital frequency synthesizer, the phase of one of the variable clock and the frequency reference clock will be shifted adaptively according to the accumulated value of the frequency command character, so that all The time difference can be maintained within a partial period of the variable clock, and the time-to-digital conversion range can be set shorter than a full period of the variable clock. Furthermore, unnecessary high-frequency thixotropic pulses fed to the time-to-digital converter can also be gated out without affecting the normal function of the time-to-digital converter. Smaller time-to-digital conversion range and thixotropic gate removal can bring many advantages to the frequency synthesizer, such as improving the linearity of time-to-digital conversion, reducing hardware complexity, reducing power consumption, reducing layout area, and reducing decoupling capacitance requirements and suppress power supply disturbances.

Claims (26)

1. a frequency synthesizer, it is characterised in that this frequency synthesizer comprises:

One frequency reference input, in order to receive a frequency reference clock；

One trimmed agitator, in order to provide a radio frequency clock；

One phase shifter, couples this frequency reference input, in order to change the phase place of this frequency reference clock； And

One time-to-digit converter, in order to produce a numeral conversion output, this time-to-digit converter is coupled to This phase shifter and this trimmed agitator；

Wherein, a time figure conversion range of this time-to-digit converter is complete less than the one of this radio frequency clock Cycle.

2. frequency synthesizer as claimed in claim 1, it is characterised in that wherein this time-to-digit converter In order to the frequency reference clock after receiving this change phase place with this radio frequency clock to produce the conversion output of this numeral, And the conversion output of this numeral is at a transition of the frequency reference clock after quantifying this change phase place and this radio frequency A time difference between the previous transition of clock and obtain.

3. frequency synthesizer as claimed in claim 1, it is characterised in that wherein this phase shifter is Digit time, transducer, digital control and postpone this frequency reference clock in order to respond a conversion.

4. frequency synthesizer as claimed in claim 3, it is characterised in that wherein this conversion is digital control is Respond the aggregate-value of a frequency instruction character and be set.

5. frequency synthesizer as claimed in claim 3, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of a frequency instruction character and There is provided this conversion digital control.

6. frequency synthesizer as claimed in claim 5, it is characterised in that wherein this translational controller is more used There is provided an auxiliary decimal error correction signal to respond the aggregate-value of this frequency instruction character, and this is trimmed When agitator more adjusts this radio frequency in order to respond the conversion output of this numeral and this auxiliary decimal error correction signal The cycle of clock.

7. frequency synthesizer as claimed in claim 1, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of a frequency instruction character and One auxiliary decimal error correction signal is provided；

Wherein, this trimmed agitator is more in order to according to the conversion output of this numeral and this auxiliary decimal error correction Signal and adjust the cycle of this radio frequency clock.

8. frequency synthesizer as claimed in claim 7, it is characterised in that wherein this translational controller is more used There is provided a conversion digital control to respond the aggregate-value of this frequency instruction character, and this phase shifter in order to Respond this conversion digital control and change the phase place of this frequency reference clock.

9. frequency synthesizer as claimed in claim 1, it is characterised in that this frequency synthesizer further includes:

One variable phase accumulation device, couples this trimmed agitator, in order to the periodicity of this radio frequency clock accumulative And a variable phase signal is provided according to this；And

One fixed phase integrating instrument, adds up a frequency instruction in order to respond each cycle of this frequency reference clock Character also provides the aggregate-value of this frequency instruction character according to this；

Wherein, this phase shifter changes this frequency reference in order to respond the aggregate-value of this frequency instruction character The phase place of clock, and this trimmed agitator in order to according to this numeral conversion output, this variable phase signal and The aggregate-value of this frequency instruction character and adjust the cycle of this radio frequency clock.

10. frequency synthesizer as claimed in claim 9, it is characterised in that this frequency synthesizer further includes:

One retimer, in order to retime to carry to this frequency reference clock at the transition of this radio frequency clock Reference clock when resetting for one；

Wherein, add up this frequency at this fixed phase integrating instrument transition in order to the reference clock when this resets to refer to Make character.

11. frequency synthesizers as claimed in claim 9, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of this frequency instruction character and One auxiliary decimal error correction signal is provided；

Wherein, this trimmed agitator more adjusts this radio frequency clock according to this auxiliary decimal error correction signal Cycle.

12. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter changes The phase place of this frequency reference clock offer according to this translation reference clock, make one turn of this translation reference clock Time difference at state and between the previous transition of this radio frequency clock is less than a complete week of this radio frequency clock Phase.

13. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter is used for The phase place changing this frequency reference clock translates reference clock with offer one, and this time-to-digit converter is to work as Occur at this time figure conversion range with at the transition of this translation reference clock at the transition of this radio frequency clock Respond time at proximity, and do not send out at the transition of this translation reference clock at the transition of this radio frequency clock Then it is not responding to when life is at the proximity of this time figure conversion range.

14. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter in order to Respond the decimal part of the aggregate-value of a frequency instruction character and offset the phase place of this frequency reference clock.

15. 1 frequency synthesizers, it is characterised in that this frequency synthesizer comprises:

One agitator, in order to provide a variable clock；

One phase shifter, in order to provide a translation reference clock, makes the phase place and of this translation reference clock The phase one phase shift amount of frequency reference clock, wherein this phase shift amount makes this translation reference clock A transition at and the previous transition of this variable clock between a time difference less than of this variable clock Cycle；

One time-to-digit converter, couples this phase shifter, in order to quantify this time difference to provide one first Decimal error correction signal；And

One variable phase accumulation device, couples this agitator, in order to add up the periodicity of this variable clock to provide One variable phase signal；

Wherein, this agitator adjusts the cycle of this variable clock according to this variable phase signal.

16. frequency synthesizers as claimed in claim 15, it is characterised in that this frequency synthesizer further includes:

One fixed phase integrating instrument, for responding each cycle of this frequency reference clock with an accumulative frequency instruction Character, and a reference phase signal is provided according to this；

Wherein, this phase shifter is in order to respond this reference phase signal to set this phase shift amount, and this shakes Swing device and more adjust the cycle of this variable clock according to this reference phase signal.

17. frequency synthesizers as claimed in claim 16, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, provides one in order to respond this reference phase signal Two decimal error correction signals；

Wherein, this agitator is more in order to repair with this second decimal error according to this first decimal error correction signal Positive signal and adjust the cycle of this variable clock.

18. 1 frequency synthesizers, it is characterised in that this frequency synthesizer comprises:

One agitator, in order to provide a variable clock；

One time-to-digit converter, in order to quantify time difference between a translation reference clock and this variable clock also One first decimal error correction signal, the wherein phase place of this translation reference clock and a frequency reference are provided according to this The phase one phase shift amount of clock；One translational controller, in order to respond a frequency instruction character Aggregate-value and one second decimal error correction signal is provided；And

One variable phase accumulation device, couples this agitator, in order to the periodicity according to this of this variable clock accumulative One variable phase signal is provided；

Wherein this agitator is more in order to according to this first decimal error correction signal and this second decimal error correction The aggregate-value of signal, this variable phase signal and this frequency instruction character adjusts the cycle of this variable clock.

19. frequency synthesizers as claimed in claim 18, it is characterised in that this frequency synthesizer further includes:

One phase shifter, couples this frequency reference clock, in order to change the phase place of this frequency reference clock with This translation reference clock is provided.

20. frequency synthesizers as claimed in claim 18, it is characterised in that this frequency synthesizer further includes:

One fixed phase integrating instrument, adds up this frequency instruction in order to respond each cycle of this frequency reference clock Character, and the aggregate-value of this frequency instruction character is provided according to this.

21. 1 kinds of frequency combining methods, it is characterised in that this frequency combining method comprises:

Respond an agitator to adjust signal and produce a variable clock；

By the phase offset one phase shift amount of a frequency reference clock to obtain a translation reference clock；And

By the time difference digitized between this variable clock and this translation reference clock, this time difference digitized One scope is less than a cycle of this variable clock.

22. frequency combining methods as claimed in claim 21, it is characterised in that this time difference is this translation Time difference at reference clock one transition and between the previous transition of this variable clock.

23. frequency combining methods as claimed in claim 22, it is characterised in that this frequency combining method is more Comprise:

Adjust this phase shift amount, make this time difference be less than or equal at a transition of this frequency reference clock and be somebody's turn to do Time difference between the previous transition of variable clock.

24. frequency combining methods as claimed in claim 23, it is characterised in that this frequency combining method is more Comprise:

A frequency instruction character is added up to obtain this frequency instruction character according to each cycle of this frequency reference clock Aggregate-value；And

This phase shift amount is adjusted according to the decimal part of the aggregate-value of this frequency instruction character.

25. frequency combining methods as claimed in claim 24, it is characterised in that this frequency combining method is more Comprise:

One first decimal error correction signal is obtained according to this digitized；And

Adjust this agitator according to this first decimal error correction signal and adjust signal.

26. frequency combining methods as claimed in claim 25, it is characterised in that this frequency combining method is more Comprise:

One second decimal error correction signal is measured to obtain according to this phase shift；

More adjust this agitator according to this second decimal error correction signal and adjust signal.