CN103051331A - Phase locking circuit for ultrasonic power supply - Google Patents

Abstract

The invention relates to a phase-locked circuit for an ultrasonic power supply, which includes a first comparator and a second comparator, and the voltage and current synchronous square wave signal generated by the output of the comparator is connected to the first to fourth monostable triggers, And XOR gate and the second D flip-flop and the third D flip-flop. The outputs of the first to fourth monostable flip-flops and XOR gates are connected to the second and third D flip-flops, and the two-way pulse signals output by the second and third D flip-flops respectively pass through the first and third D flip-flops with the same parameters. The second RC filter circuit is input to the third comparator, and the output of the third comparator can determine the direction of frequency increase and decrease. The phase-locking circuit disclosed by the invention can be used for voltage and current synchronous square wave signals with different duty ratios to achieve the purpose of phase-locking frequency tracking.

Description

A phase-locked circuit for ultrasonic power supply

technical field

The invention relates to a phase-locked circuit for ultrasonic power supply

Background technique

The ultrasonic power supply is usually called the ultrasonic generating source, and its function is to convert electrical energy into a high-frequency alternating current signal that matches the ultrasonic transducer. Ultrasonic power supplies generally must have a frequency tracking system. When the transducer works at the resonant frequency point, its efficiency is the highest and the work is the most stable. However, the resonant frequency point of the transducer will change due to assembly reasons and work aging, which is called the resonant frequency point. Drift, the function of the frequency tracking system is to make the output AC signal always work at the resonant frequency of the transducer, so that the transducer works with the highest efficiency.

At present, the frequency tracking system of ultrasonic power supply often adopts phase-locked frequency tracking, and the traditional phase-locked frequency tracking method is suitable for the case where the output voltage and current synchronization signal duty ratios are equal, and when the duty ratio of the output voltage and current synchronization signals When the ratio is different, such as the PS-PWM control method that controls the output voltage by changing the phase shift angle, the duty cycle of the output voltage and current synchronization signal is not equal. If the traditional phase-locked frequency tracking method is still used, the output voltage cannot be reached. The purpose of the current in phase.

Contents of the invention

The purpose of the invention is to overcome the shortcomings of the prior art, and disclose a phase-locked circuit for ultrasonic power supply. The invention discloses a phase-locked circuit for an ultrasonic power supply, which is suitable for realizing the effect of phase-locked frequency tracking under the condition that the duty ratios of output voltage and current synchronous square wave signals are not equal. The phase-locked circuit of the ultrasonic power supply samples the time when the output voltage and current synchronous square wave signals are at different levels, and expresses them in the form of pulses. By controlling the pulse width of the two pulse signals output by the D flip-flop link to be equal, the purpose of frequency phase-locked tracking is achieved.

Object of the present invention can adopt following technical scheme to realize:

A phase-locked circuit for ultrasonic power supply, which includes two comparators, exclusive OR gates, four monostable flip-flops, three D flip-flops and two RC filter circuits, wherein the output of the first comparator The second monostable flip-flop and the third monostable flip-flop are connected, the output terminal of the second comparator is connected to the first monostable flip-flop and the fourth monostable flip-flop, the first comparator and the second The output terminal of the comparator is also connected with the input of the XOR gate and the first D flip-flop, and the outputs of the first to fourth monostable flip-flops and the XOR gate are connected to the second D flip-flop and the third D flip-flop, The two pulse signals output by the second D flip-flop and the third D flip-flop respectively pass through an RC filter circuit, and are finally input into the third comparator.

Further optimized, the positive input pin of the first comparator and the positive input pin of the second comparator are respectively connected to the voltage and current sampling signals, and the negative input pin of the first comparator and the negative input pin of the second comparator Both are grounded; the output terminal pin of the first comparator is connected to the first input terminal pin of the exclusive OR gate, and the output terminal pin of the second comparator is connected to the second input terminal pin of the exclusive OR gate. The output terminal pin of the first comparator is connected to the clock terminal pin of the first D flip-flop, and the output terminal pin of the second comparator is connected to the D input port pin of the first D flip-flop.

For further optimization, the Q non-output end of the first D flip-flop is suspended, and the output pins of the first comparator are respectively connected to the rising edge pin of the second monostable trigger and the falling edge pin of the third monostable trigger. The output pins of the two comparators are respectively connected to the rising edge pin of the first monostable trigger and the falling edge pin of the fourth monostable trigger, and the Q output pin of the first monostable trigger is connected to the second monostable trigger The Q output pins of the flip-flop are respectively connected to the clock port pins of the second D flip-flop through a diode; the Q output pins of the third monostable flip-flop and the Q output pins of the fourth monostable flip-flop are respectively Input to the clock pin of the third D flip-flop through a diode; the falling edge input terminals of the first monostable trigger and the second monostable trigger are grounded, and the third monostable trigger and the fourth monostable The rising edge input of the flip-flop is grounded; the Q non-output of the first to fourth monostable flip-flops is suspended; the output of the XOR gate is respectively connected to the D input pin of the second D flip-flop and the third D flip-flop D input terminal pin; the output of the second D flip-flop and the third D flip-flop are respectively input to the negative input terminal pin and the positive input terminal pin of the third comparator through the first and second RC filter circuits with the same parameters; 2. The Q non-output end of the third D flip-flop is suspended.

Further optimized, among the two RC filter circuits, the first RC filter circuit is composed of a first resistor and a first capacitor, and the second RC filter circuit is composed of a second resistor and a second capacitor.

For further optimization, the parameters of the first RC filter circuit and the second RC filter circuit are the same.

Further optimized, the Q output terminals of the first to fourth monostable flip-flops are respectively connected to the clock terminals of the second and third D flip-flops through a diode.

Further optimized, the output voltage and current are in phase by controlling the pulse widths of the two pulse signals output by the second and third D flip-flops to be equal.

Compared with the prior art, the present invention has the following advantages:

The ultrasonic power supply phase-locked circuit proposed by the present invention is different from the traditional phase-locked circuit. The traditional phase-locked circuit makes the first rising edge of the output voltage and current synchronous square wave signal synchronized, so as to achieve the same phase of voltage and current. Effect. This method is only applicable to the case where the duty ratios of the voltage and current synchronous square wave signals are equal. This method will encounter problems if the duty ratios of the voltage and current synchronous square wave signals are different.

The ultrasonic power supply phase-locked circuit proposed by the present invention is suitable for situations where the duty ratios of output voltage and current synchronous square wave signals are not equal. In one cycle, the voltage and current sampling signals respectively pass through the first and second comparators, XOR gates, first to fourth monostable flip-flops and second and third D flip-flops in the phase-locked circuit Two output pulse signals can be obtained. As long as the pulse widths of the two pulse signals are controlled to be equal, the phase-locked frequency tracking effect can be achieved when the duty ratios of the output voltage and current synchronous square wave signals are not equal.

Description of drawings

FIG. 1 is a schematic structural diagram of the phase-locked circuit.

FIG. 2 is a schematic structural diagram of a traditional phase-locked circuit.

Fig. 3 is the output waveform of the XOR gate XOR1 and the output waveform of the Q output terminal of the first and second D flip-flops.

Fig. 4 is a synchronous square wave waveform of the output voltage and current of the ultrasonic power supply when the phase-locked circuit is applied.

Fig. 5 is a sampling waveform of the output voltage and current of the phase-locked circuit applied to an ultrasonic power supply.

Fig. 6 shows the synchronous square wave waveform and the output voltage and current waveforms when the traditional phase-locked circuit is applied to the ultrasonic power supply, and the duty ratio of the output voltage and current synchronous square wave is different.

Detailed ways

The implementation of the present invention will be further described in detail below in conjunction with the accompanying drawings, but the implementation and protection scope of the present invention are not limited thereto.

The phase-locked circuit disclosed in the present invention is mainly used in the case where the synchronous square wave signals of the output voltage and current have different duty ratios. As shown in FIG. 1 , the voltage sampling signal and the current sampling signal respectively pass through the first comparator COMP1 and the second comparator COMP2 to obtain a square wave signal synchronized with the voltage and current. First, input the synchronous signal into the XOR gate XOR1. When the voltage and current synchronous signals are at different levels, the XOR1 gate will output a high level, so that a series of pulse signals can be obtained, corresponding to the voltage and current synchronous signals at different levels. time. Then connect the output signal of the XOR1 gate to the D input terminals of the second D flip-flop DFF2 and the third D flip-flop DFF3, and then connect the synchronization signal of voltage and current to the first ~ fourth units according to the wiring method in the figure. Steady-state flip-flops (MONO5, MONO6, MONO7, MONO8), connect the Q output terminals of the first to fourth monostable flip-flops to the second D flip-flop DFF2 and the third D flip-flop DFF3 according to the wiring method in the figure In this way, one pulse output by the XOR gate XOR1 can be divided into two pulse signals corresponding to the geometric center point of the output current and voltage signal. As shown in Figure 3, the XOR gate output signal V11 passes through the first and second After the two-D flip-flop link, two separate pulse signals of V43 and V44 can be obtained. As long as the pulse widths of the two pulse signals of V43 and V44 are controlled to be equal, the effect of voltage and current phase-locked synchronization can be obtained. Therefore, the two pulse signals are passed through the first and second RC filter circuits with equal parameters, as shown in Figure 1, a DC voltage signal proportional to the pulse width can be obtained, and the magnitude of the two voltage signals can be controlled to be equal. The effect of equal pulse width is obtained. As shown in Figure 4, V8 and V9 are square wave signals with synchronous voltage and current. It can be seen that their geometric center points are relatively synchronous. Figure 5 shows the sampling signal of voltage and current, VP7 is the sampling signal of voltage, and V7 is the sampling signal of current. In order to compare the voltage and current signals clearly, the current signal of V7 is amplified. It can be seen that the phase lock is still relatively good.

The connection relationship of the circuit components is shown in Figure 1: the voltage and current sampling signals are respectively connected to the positive input terminal pin 3 of the first comparator COMP1 and the positive input terminal pin 1 of the second comparator COMP2, and the positive input terminal pin 1 of the first comparator COMP1. Both the negative input pin 4 and the negative input pin 2 of the second comparator COMP2 are grounded. The output pin 6 of the first comparator COMP1 is connected to the first input pin 8 of the exclusive OR gate XOR1, and the output pin 5 of the second comparator COMP2 is connected to the second input pin 7 of the exclusive OR gate XOR1. The output terminal pin 6 of the first comparator COMP1 is connected to the clock terminal pin 9 of the first D flip-flop DFF1, and the output terminal pin 5 of the second comparator COMP2 is connected to the D input port pin 10 of the first D flip-flop DFF1. The Q non-output terminal of the first D flip-flop is suspended. The output pin 6 of the first comparator COMP1 is respectively connected to the rising edge pin 12 of the second monostable flip-flop MONO6 and the falling edge pin 13 of the third monostable flip-flop MONO7. The output pin 5 of the second comparator COMP2 is respectively connected to the rising edge pin 11 of the first monostable flip-flop MONO5 and the falling edge pin 14 of the fourth monostable flip-flop MONO8. The Q output pin 15 of the first monostable flip-flop MONO5 and the Q output pin 16 of the second monostable flip-flop MONO6 are respectively connected to the clock port pin 20 of the second D flip-flop DFF2 through a diode. The Q output terminal pin 17 of the third monostable flip-flop MONO7 and the Q output terminal pin 18 of the fourth monostable flip-flop MONO8 are respectively input to the clock terminal pin 22 of the third D flip-flop DFF3 through a diode. The falling edge input ends of the first monostable flip-flop MONO5 and the second monostable flip-flop MONO6 are grounded, and the rising edge input ends of the third monostable flip-flop MONO7 and the fourth monostable flip-flop MONO8 are grounded. The Q non-outputs of the first to fourth monostable flip-flops are suspended. The output terminal of the XOR gate XOR1 is connected to the D input terminal pin 19 of the second D flip-flop DFF2 and the D input terminal pin 21 of the third D flip-flop DFF3 respectively. The Q outputs of the second D flip-flop DFF2 and the third D flip-flop DFF3 are respectively input to the negative input pin 26 and the positive input pin 25 of the third comparator COMP11 through the first and second RC filter circuits with the same parameters. The Q non-output terminals of the second and third D flip-flops are suspended. Among the two RC filter circuits, the first RC filter circuit is composed of a first resistor R34 and a first capacitor C34, and the second RC filter circuit is composed of a second resistor R35 and a second capacitor C35.

The traditional phase-locking circuit is shown in Figure 2. The voltage sampling signal and the current sampling signal pass through the fourth comparator C1 and the fifth comparator C2 respectively to generate a square wave signal synchronized with the voltage and current signals. The voltage-synchronized square wave signal output by C1 is connected to the clock terminal of the D flip-flop, and the voltage signal output by C2 is connected to the D input terminal of the D flip-flop. When the voltage signal and the current signal have different phases, the XOR gate can output a pulse signal with the same pulse width as the phase difference. The output level of the D flip-flop Q output terminal obtained by the traditional phase-locked circuit is used to determine whether to increase or decrease the frequency, and the XOR output pulse width is used to determine the speed of frequency change to achieve transducer resonance the goal of. It is only synchronized according to the rising edge of the synchronization signal of current and voltage to achieve the purpose of synchronization of current and voltage signals. If the pulse width of the voltage and current synchronous signal is not equal, the rising edge of the synchronous signal is synchronous, and the voltage and current in-phase effect cannot be achieved, especially in the case of the PS-PWM control method.

The PS-PWM control method is to change the effective value of the output voltage by changing the phase shift angle of the phase shift full bridge, so as to achieve the purpose of voltage regulation. Therefore, the bridge arm voltage output regulated by the PS-PWM method is not a standard square wave signal, but a square wave output with an adjustable duty cycle. The bridge arm signal is applied to the transducer system, and its resonant current is a sinusoidal signal, so the synchronous signal of the sinusoidal current is a standard square wave signal with a duty ratio of 0.5. If the traditional phase-locked circuit is used, the purpose of the same phase of voltage and current cannot be achieved.

If the traditional control method is used to synchronize the first rising edge of the first voltage and current signals, the output voltage and current are shown in Figure 6. Therefore, the traditional control method cannot make the output voltage and current of the PS-PWM control method same phase. Among them, VP1 and V7 are sampling waveforms of output voltage and output current respectively, and V8 and V9 are synchronous square wave waveforms of current and voltage respectively.

Claims (7)

1. A phase-locked circuit for ultrasonic power supply, characterized in that it comprises two comparators, exclusive OR gates, four monostable flip-flops, three D flip-flops and two RC filter circuits, wherein the first The output of the comparator (COMP1) is connected to the second monostable flip-flop and the third monostable flip-flop, and the output of the second comparator (COMP2) is connected to the first monostable flip-flop and the fourth monostable flip-flop flip-flop, the output terminals of the first comparator and the second comparator are also connected with the input of the XOR gate and the first D flip-flop (DFF1), and the outputs of the first to fourth monostable flip-flops are connected with the XOR gate Input the second D flip-flop (DFF2) and the third D flip-flop (DFF3), the two pulse signals output by the second D flip-flop and the third D flip-flop respectively pass through an RC filter circuit, and finally input to the third comparator device (COMP11). 2. A kind of phase-locked circuit for ultrasonic power supply according to claim 1, it is characterized in that the positive input terminal pin of the first comparator and the positive input terminal pin of the second comparator are respectively connected to voltage and current sampling signals, Both the negative input pin of the first comparator and the negative input pin of the second comparator are grounded; the output pin of the first comparator is connected to the first input pin of the XOR gate, and the output pin of the second comparator Connect to the second input pin of the XOR gate; The output terminal pin of the first comparator is connected to the clock terminal pin of the first D flip-flop, and the output terminal pin of the second comparator is connected to the D input port pin of the first D flip-flop. 3. A kind of phase-locked circuit for ultrasonic power supply according to claim 2, it is characterized in that the Q non-output end of the first D flip-flop is suspended in the air, and the output terminal pins of the first comparator are respectively connected to the second monostable state The rising edge pin of the flip-flop and the falling edge pin of the third monostable trigger, the output pins of the second comparator are respectively connected to the rising edge pin of the first monostable trigger and the falling edge pin of the fourth monostable trigger , the Q output terminal pin of the first monostable trigger and the Q output terminal pin of the second monostable trigger are respectively connected to the clock port pin of the second D flip-flop through a diode; the third monostable trigger The Q output pin of the fourth monostable flip-flop and the Q output pin of the fourth monostable trigger are respectively input to the clock pin of the third D flip-flop through a diode; the first monostable trigger and the second monostable flip-flop The falling edge input terminal is grounded, the rising edge input terminals of the third monostable flip-flop and the fourth monostable flip-flop are grounded; the Q non-output of the first to fourth monostable flip-flops is suspended; the output of the XOR gate Respectively connect the D input pin of the second D flip-flop and the D input pin of the third D flip-flop; the output of the second D flip-flop and the third D flip-flop respectively pass through the first and second RC with the same parameters The filtering circuit is input to the negative input terminal pin and the positive input terminal pin of the third comparator; the Q non-output terminals of the second and third D flip-flops are suspended. 4. according to claim 2 or 3 described a kind of phase-locked circuit for ultrasonic power supply, it is characterized in that in two RC filter circuits, the first RC filter circuit is made up of the first resistor and the first capacitor, The second RC filter circuit is composed of a second resistor and a second capacitor. 5. The phase-locked circuit for ultrasonic power supply according to claim 1, characterized in that the parameters of the first RC filter circuit and the second RC filter circuit are the same. 6. The phase-locked circuit for ultrasonic power supply according to claim 1 or 2, characterized in that the Q output terminals of the first to fourth monostable triggers are connected to the second through a diode respectively. , the clock terminal of the third D flip-flop. 7. A phase-locked circuit for an ultrasonic power supply according to claim 1, wherein the pulse width of the two pulse signals output by controlling the second and third D flip-flops is equal to make the output voltage , The current is in phase.

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