CN103049063A - Computer crash resetting device - Google Patents
Computer crash resetting device Download PDFInfo
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- CN103049063A CN103049063A CN2012105450405A CN201210545040A CN103049063A CN 103049063 A CN103049063 A CN 103049063A CN 2012105450405 A CN2012105450405 A CN 2012105450405A CN 201210545040 A CN201210545040 A CN 201210545040A CN 103049063 A CN103049063 A CN 103049063A
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Abstract
The invention provides a computer crash resetting device. The computer crash resetting device comprises a first circuit and a second circuit, wherein the first circuit has no computer crash state; the second circuit has the computer crash state and a normal work state; the first circuit monitors the state of the second circuit; and when the second circuit is in the computer crash state, the first circuit controls the second circuit to recover the normal work state. In comparison with the prior art, the computer crash resetting device has a simple resetting way and is easy to operate as the first circuit monitors the state of the second circuit, and the first circuit controls the second circuit to recover the normal work state when the second circuit is in the computer crash state, and therefore brings about better user experience to users.
Description
[technical field]
The present invention relates to circuit design field, particularly a kind of system-halted reset device.
[background technology]
Various intelligence system of the prior art, for example, bluetooth earphone, panel computer, smart mobile phone, intelligent television, PC, notebook computer, individual Medical Devices etc., the processors that adopt are controlled more.At present, widely used processor has low-power consumption ARM (Advanced RISC Machine, abbreviation ARM) nuclear, intel CPU (Center Processor Unit), AMD CPU or MIPS (Million Instructions PerSecond) system etc., such as, ARM-A8.These processors may occur crashing when some abnormality.For example, when occurring serious lower a jumping on its supply voltage, when error in address appearred in access memory during perhaps owing to variations such as neighbourhood noise or temperature, perhaps owing to falling when causing some circuit moment loose contact, processor all may crash.And after the processor deadlock, usually need to start shooting again and could recover by the plug battery.And the smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, the dismounting of inconvenient domestic consumer, unloading process very easily causes the physical unit loss, and therefore, domestic consumer generally can't dismantle battery.Although it is very little that the probability of deadlock occurs, if occur, consequence is very serious.Because battery is built-in, be inconvenient to dismantle, system is in the deadlock state always like this, until after the electric weight of battery depleted fully, charge, the deadlock state could be resetted so again.Because present popular low power dissipation design all, battery is given out light voluntarily and is taken for a long time, like this so that customer experience is very bad.
Therefore be necessary to provide a kind of improved technical scheme to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of system-halted reset device, when it the deadlock state occurs, can realize automatically reseting, recover normal operating conditions, thereby bring better user to experience to the client.
In order to address the above problem, the invention provides a kind of system-halted reset device, it comprises the first circuit and second circuit, described the first circuit state that do not crash, described second circuit has deadlock state and normal operating conditions, described the first circuit is monitored the state of described second circuit, and when the deadlock state appearred in described second circuit, described the first circuit was controlled described second circuit and recovered normal operating conditions.
Further, be provided with communication channel between described the first circuit and the described second circuit, described the first circuit regularly sends status request information to second circuit by described communication channel, if second circuit is replied the normal operation identification information by described communication channel, judge that then second circuit is in normal operating conditions, if second circuit is not replied the normal operation identification information, judge that then second circuit is in the deadlock state; Also be provided with reset passages between described the first circuit and the described second circuit, when the deadlock state appearred in described second circuit, described the first circuit was controlled described second circuit by this reset passages and is recovered normal operating conditions.
Further, when the second circuit continuous several times is not replied the normal operation identification information, judge that just the deadlock state appears in second circuit.
Further, described communication channel comprises serial data line and the serial clock circuit that is arranged between described the first circuit and the second circuit, described serial clock circuit links to each other with power supply by the first resistance, and described tandem data circuit links to each other with power supply by the second resistance.
Further, described reset passages connects the reset signal output terminal of the first circuit and the reset terminal of second circuit, when judging that second circuit is in the deadlock state, the first circuit enters normal operating conditions by the reset terminal of reset signal output terminal output reset signal to second circuit to reactivate second circuit.
Further, described the first circuit is electric power management circuit, and described second circuit is processor, and described system-halted reset device is used for bluetooth earphone.
Further, described reset passages connects the power output end of the first circuit and the power end of second circuit, described the first circuit provides power supply for second circuit, and when the deadlock state appearred in described second circuit, the power supply that the first circuit will offer second circuit restarted.
Further, described the first circuit is electric power management circuit, and described second circuit is processor, and described system-halted reset device is used for bluetooth earphone.
Compared with prior art, system-halted reset device among the present invention is monitored the state of second circuit by the first circuit, when the deadlock state appears in described second circuit, described the first circuit is controlled described second circuit and is recovered normal operating conditions, its reset mode is simple, easy to operate, thereby brings better user to experience to the client.
[description of drawings]
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the structural representation of the system-halted reset device among first embodiment of the present invention;
Fig. 2 a is the structural representation of the system-halted reset device among second embodiment of the present invention;
Fig. 2 b is the structural representation of the system-halted reset device among the 3rd embodiment of the present invention,
Fig. 3 a is the structural representation of the system-halted reset device among the 4th embodiment of the present invention; With
Fig. 3 b is the structural representation of the system-halted reset device among the 5th embodiment of the present invention.
[embodiment]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Alleged " embodiment " or " embodiment " refer to be contained in special characteristic, structure or the characteristic at least one implementation of the present invention herein.Different local in this manual " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.Unless stated otherwise, herein connection, the word that the expression that links to each other, join is electrically connected all represents directly or indirectly to be electrical connected.
System-halted reset device among the present invention communicates by first circuit that can not crash and the second circuit that may crash, monitor with the state to second circuit, when finding that request that second circuit sends the first circuit can't respond, can judge that namely second circuit is in the deadlock state, then control described second circuit by described the first circuit and recover normal operating conditions, its reset mode is simple, easy to operate, thereby brings better user to experience to the client.
Please refer to shown in Figure 1ly, it is the circuit diagram of the system-halted reset device among first embodiment of the present invention.Described system-halted reset device comprises the first circuit 110 and second circuit 120, described the first circuit 110 state that do not crash, described second circuit 120 has deadlock state and normal operating conditions, the state of 110 pairs of described second circuits 120 of described the first circuit is monitored, when the deadlock state appearred in described second circuit 120, the described second circuit 120 of described the first circuit 110 controls recovered normal operating conditions.
In the present embodiment, be provided with communication channel between described the first circuit 110 and the described second circuit 120, described the first circuit 110 regularly sends status request information to second circuit 120 by described communication channel, if second circuit 120 is replied the normal operation identification information by described communication channel, judge that then second circuit 120 is in normal operating conditions, if second circuit 120 is not replied the normal operation identification information, judge that then second circuit 120 is in the deadlock state.For avoiding misinterpretation deadlock state, described the first circuit 110 can continuous several times send status request information to second circuit 120, when second circuit 120 continuous several times are not replied the normal operation identification information, judges that just the deadlock state appears in second circuit 120.
In the embodiment shown in fig. 1, also be provided with reset passages between described the first circuit 110 and the described second circuit 120, when the deadlock state appearred in described second circuit 120, described the first circuit 110 was controlled described second circuit 120 by this reset passages and is recovered normal operating conditions.
Please refer to shown in Fig. 2 a, it is the circuit diagram of the system-halted reset device among second embodiment of the present invention.In the present embodiment, the standard I 2C agreement that adopts described communication channel realizes the communication between the first circuit 110 and the second circuit 120, be that described communication channel comprises the serial data line SDA(Serial Data that is arranged between described the first circuit 110 and the second circuit 120) and serial time clock line SCL(Serial Clock), described serial time clock line SCL links to each other with power supply VH by the first resistance R ph1, and described serial data line SDA links to each other with power supply VH by the second resistance R ph2.The first resistance R ph1 and the second resistance R ph2 are the pull-up resistor of I2C protocol requirement, its resistance can for 100 ohm to the value between 100K ohm.For simplified characterization, the present invention omits about described communication channel and adopts the principle of work of standard I 2C agreement to describe.In other embodiments, communication channel between the first circuit 110 and the second circuit 120 also can adopt any communication protocol of prior art, also can any type of communicating requirement of self-defining, send status request information as long as can realize the first circuit 110 to second circuit 120, when second circuit 120 is in normal operating conditions (not being in the deadlock state), can replys the normal operation identification information to the first circuit 110 and get final product.For example, described communication channel can be only realized communication between the first circuit 110 and the second circuit 120 by a signal line, such as, the first circuit 110 sends 4 bit serial binary data to second circuit 120 and represents status request information, and second circuit 120 is replied these serial datas and added 1 result and represent identification information working properly.If second circuit 120 is not replied correct data (normal operation identification information), then be determined the deadlock state that is in.
In the embodiment shown in Fig. 2 a, described reset passages connects the reset signal output terminal POR of the first circuit 110 and the reset terminal RST of second circuit 120.When judging that second circuit 120 is in the deadlock state, the first circuit 110 enters normal operating conditions by the reset terminal RST of reset signal output terminal POR output reset signal to second circuit 120 to reactivate second circuit 120.
Please refer to shown in Fig. 2 b, it is the circuit diagram of the system-halted reset device among the 3rd embodiment of the present invention.Its communication mode is identical with Fig. 2 a.The difference of itself and Fig. 2 a is, described reset passages connects the power output end VO of the first circuit 110 and the power end VDD of second circuit 120.That is to say, described the first circuit 110 provides power supply for second circuit 120, and when the deadlock state appearred in described second circuit 120, the power supply that the first circuit 110 will offer second circuit 120 restarted, so that second circuit 120 recovers normal operating conditions.The process of wherein restarting the supply voltage VDD of second circuit 120 is that the first circuit 110 is closed first the supply voltage VDD of second circuit 120, then controls the supply voltage VDD of second circuit 120 again from zero start to the normal voltage value.
The smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, when it the deadlock state occurs, domestic consumer's inconvenience resets to it by the mode of plug battery, therefore, above-mentioned system-halted reset device can be applied to the smart machines such as bluetooth earphone, panel computer.
Please refer to shown in Fig. 3 a, it is the circuit diagram of the system-halted reset device among the 4th embodiment of the present invention, and this deadlock resetting means is used for bluetooth earphone.The difference of itself and Fig. 2 a is, the first circuit is the electric power management circuit (Power Management Unit is called for short PMU) 310 in the Bluetooth earphone system, and second circuit is the processor 320 in the Bluetooth earphone system, for example, and ARM-A8.Because electric power management circuit 310 does not exist such as complex state machine such as ARM, therefore, it the deadlock state can not occur.And processor 320 is when some abnormality, may occur crashing, for example, when occurring serious lower a jumping on its supply voltage, perhaps in some situation because when error in address appears in access memory during the variations such as neighbourhood noise or temperature, perhaps owing to falling when causing some circuit moment loose contact, processor 320 all may crash.
For the ease of understanding, below specifically introduce the course of work of the system-halted reset device shown in Fig. 3 a.
Communication channel between electric power management circuit 310 and the processor 320 adopts standard I 2C agreement.Reset passages between electric power management circuit 310 and the processor 320 connects the reset signal output terminal POR of electric power management circuit 310 and the reset terminal RST of processor 320.Electric power management circuit 310 regularly sends status request information to processor 320 by described communication channel, if processor 320 is in normal operating conditions (not being in the deadlock state), it should reply electric power management circuit 310 1 fix informations (identification information namely works) by reset passages, if namely processor 320 is replied the normal operation identification information by described communication channel, then decision processor 320 is in normal operating conditions; If processor 320 is in the deadlock state, it should reply the normal operation identification information by described communication channel according to pre-provisioning request, does not namely reply the normal operation identification information when processor 320, and then decision processor 320 is in the deadlock state.At this moment, electric power management circuit 310 is given the reset terminal RST of described processor 320 by its reset signal output terminal POR output reset signal, described processor 320 is resetted, and namely reactivates described processor 320 and enters normal operating conditions.
Please refer to shown in Fig. 3 b, it is the circuit diagram of the system-halted reset device among the 5th embodiment of the present invention.This deadlock resetting means is used for bluetooth earphone.The difference of itself and Fig. 3 a is, the reset passages between electric power management circuit 310 and the processor 320 connects the power output end VO of electric power management circuit 310 and the power end VDD of processor 320.That is to say, described electric power management circuit 310 provides power supply for processor 320, when the deadlock state appearred in described processor 320, the power supply that described electric power management circuit 310 will offer processor 320 restarted, so that processor 320 recovers normal operating conditions.
In sum, system-halted reset device among the present invention communicates by first circuit 110 that can not crash and the second circuit 120 that may crash, so that the state of second circuit 120 is monitored, when finding that request that 120 pairs of the first circuit 110 of second circuit send can't respond, can judge that namely second circuit 120 is in the deadlock state, then recover normal operating conditions by the described second circuit 120 of described the first circuit 110 controls, its reset mode is simple, easy to operate, thereby brings better user to experience to the client.
Those of ordinary skill in the affiliated field can be understood that, above only be that the system-halted reset device among the present invention is applied to Bluetooth earphone system, in fact also the system-halted reset device among the present invention can be applied in other intelligent processor, so that its reset mode is simple, easy to operate, thereby bring better user to experience to the client.
In the present invention, the word that the expression such as " connection ", " linking to each other ", " company ", " connecing " is electrically connected if no special instructions, then represents direct or indirect electric connection.CLK in the accompanying drawing is clock signal, and DATA is data-signal.
It is pointed out that and be familiar with the scope that any change that the person skilled in art does the specific embodiment of the present invention does not all break away from claims of the present invention.Correspondingly, the scope of claim of the present invention also is not limited only to previous embodiment.
Claims (8)
1. a system-halted reset device is characterized in that, it comprises the first circuit and second circuit, described the first circuit state that do not crash, and described second circuit has deadlock state and normal operating conditions,
Described the first circuit is monitored the state of described second circuit, and when the deadlock state appearred in described second circuit, described the first circuit was controlled described second circuit and recovered normal operating conditions.
2. system-halted reset device according to claim 1 is characterized in that,
Be provided with communication channel between described the first circuit and the described second circuit,
Described the first circuit regularly sends status request information to second circuit by described communication channel, if second circuit is replied the normal operation identification information by described communication channel, judge that then second circuit is in normal operating conditions, if second circuit is not replied the normal operation identification information, judge that then second circuit is in the deadlock state;
Also be provided with reset passages between described the first circuit and the described second circuit, when the deadlock state appearred in described second circuit, described the first circuit was controlled described second circuit by this reset passages and is recovered normal operating conditions.
3. system-halted reset device according to claim 2 is characterized in that, when the second circuit continuous several times is not replied the normal operation identification information, judges that just the deadlock state appears in second circuit.
4. system-halted reset device according to claim 2, it is characterized in that, described communication channel comprises serial data line and the serial clock circuit that is arranged between described the first circuit and the second circuit, described serial clock circuit links to each other with power supply by the first resistance, and described tandem data circuit links to each other with power supply by the second resistance.
5. arbitrary described system-halted reset device according to claim 2-4, it is characterized in that, described reset passages connects the reset signal output terminal of the first circuit and the reset terminal of second circuit, when judging that second circuit is in the deadlock state, the first circuit enters normal operating conditions by the reset terminal of reset signal output terminal output reset signal to second circuit to reactivate second circuit.
6. system-halted reset device according to claim 5 is characterized in that, described the first circuit is electric power management circuit, and described second circuit is processor, and described system-halted reset device is used for bluetooth earphone.
7. arbitrary described system-halted reset device according to claim 2-4, it is characterized in that, described reset passages connects the power output end of the first circuit and the power end of second circuit, described the first circuit provides power supply for second circuit, when the deadlock state appearred in described second circuit, the power supply that the first circuit will offer second circuit restarted.
8. system-halted reset device according to claim 7 is characterized in that, described the first circuit is electric power management circuit, and described second circuit is processor, and described system-halted reset device is used for bluetooth earphone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105450405A CN103049063A (en) | 2012-12-14 | 2012-12-14 | Computer crash resetting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105450405A CN103049063A (en) | 2012-12-14 | 2012-12-14 | Computer crash resetting device |
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| CN103049063A true CN103049063A (en) | 2013-04-17 |
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| CN2012105450405A Pending CN103049063A (en) | 2012-12-14 | 2012-12-14 | Computer crash resetting device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105204954A (en) * | 2015-09-17 | 2015-12-30 | 广东欧珀移动通信有限公司 | Method and terminal for processing dead halt state |
| CN105743468A (en) * | 2014-12-09 | 2016-07-06 | 联想(北京)有限公司 | Circuit module, electronic equipment, and information processing method |
| CN114095820A (en) * | 2021-10-28 | 2022-02-25 | 歌尔科技有限公司 | TWS earphone control method, TWS earphone and readable storage medium |
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| US20010054160A1 (en) * | 2000-04-21 | 2001-12-20 | Chiaki Hashimoto | Power on/off circuit apparatus having a reset function |
| CN102004535A (en) * | 2009-09-02 | 2011-04-06 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
| CN102377445A (en) * | 2010-08-10 | 2012-03-14 | 希姆通信息技术（上海）有限公司 | Wireless communication module and self-recovery method thereof |
| CN202995613U (en) * | 2012-12-14 | 2013-06-12 | 无锡中星微电子有限公司 | Crash resetting device |
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Patent Citations (4)
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| US20010054160A1 (en) * | 2000-04-21 | 2001-12-20 | Chiaki Hashimoto | Power on/off circuit apparatus having a reset function |
| CN102004535A (en) * | 2009-09-02 | 2011-04-06 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
| CN102377445A (en) * | 2010-08-10 | 2012-03-14 | 希姆通信息技术（上海）有限公司 | Wireless communication module and self-recovery method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105743468A (en) * | 2014-12-09 | 2016-07-06 | 联想(北京)有限公司 | Circuit module, electronic equipment, and information processing method |
| CN105743468B (en) * | 2014-12-09 | 2020-02-21 | 联想(北京)有限公司 | Circuit module, electronic equipment and information processing method |
| CN105204954A (en) * | 2015-09-17 | 2015-12-30 | 广东欧珀移动通信有限公司 | Method and terminal for processing dead halt state |
| CN105204954B (en) * | 2015-09-17 | 2019-02-22 | Oppo广东移动通信有限公司 | A method and terminal for handling a crash state |
| CN114095820A (en) * | 2021-10-28 | 2022-02-25 | 歌尔科技有限公司 | TWS earphone control method, TWS earphone and readable storage medium |
| CN114095820B (en) * | 2021-10-28 | 2024-07-30 | 歌尔科技有限公司 | TWS earphone control method, TWS earphone and readable storage medium |
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Application publication date: 20130417 |