CN103035779A - Photovoltaic device - Google Patents

Abstract

Provided are a photovoltaic device and a manufacturing method thereof. Here, the base portion and the emitter portion are formed on the surface of the semiconductor substrate. An insulating layer is formed on the base portion and the emitter portion. The insulating layer has a plurality of through holes to partially expose the base portion and the emitter portion. The first electrode is formed to contact an area of the emitter portion through at least one via hole, and the second electrode is formed to contact an area of the base portion through at least another via hole. Then, a cutting line is provided at the bus electrode portion of the second electrode, and the semiconductor substrate is divided into at least two photovoltaic devices at the base portion along the cutting line.

Description

Photovoltaic installation

This application claims the benefit of and priority to U.S. Provisional Application No. 61/544,111, filed October 6, 2011 in the United States Patent and Trademark Office, the entire disclosure of which application is hereby incorporated by reference.

technical field

One or more embodiments of the invention relate to photovoltaic devices.

Background technique

In order to manufacture a photovoltaic device, a p-n junction is formed by doping n-type impurities (or p-type impurities) into a p-type substrate (or n-type substrate), thus forming an emitter. Electron-hole pairs formed through the reception of light are separated. Here, electrons are collected by electrodes in the n-type region, and holes are collected by electrodes in the p-type region. Thus, electricity is generated.

The photovoltaic device may have a structure in which electrodes are respectively arranged on a front surface which is a light receiving surface and on a rear surface. Here, if the electrodes are arranged on the front surface, the area receiving light is reduced by as much as the area of the electrodes. In order to solve the area reduction problem, a back-contact structure in which electrodes are arranged only on the rear surface of the substrate is employed.

Contents of the invention

Aspects of embodiments of the invention relate to photovoltaic devices and methods of manufacturing the photovoltaic devices.

An aspect of an embodiment of the present invention relates to a method of manufacturing a photovoltaic device, wherein a dicing line is provided at a base portion of a semiconductor substrate (ie, at a base portion of a semiconductor wafer), and the semiconductor substrate is diced along the dicing line .

An aspect of embodiments of the invention relates to a photovoltaic device having a first electrode contacting a region of an emitter portion of the photovoltaic device and a second electrode contacting a region of a base portion of the photovoltaic device. Here, the second electrode is a cut electrode, the photovoltaic device having only two trimmed corner portions at its emitter portion.

Embodiments of the invention provide a method of manufacturing a photovoltaic device. The method includes: forming a semiconductor substrate having a first surface and a second surface, the second surface facing away from the first surface; forming a base portion and an emitter portion at the first surface; forming an insulating layer on the base portion and the emitter portion; forming a plurality of via holes in the insulating layer to partially expose the base portion and the emitter portion; forming a first electrode to pass through At least one via hole contacts an area of the emitter portion; forming a second electrode to contact an area of the base portion through at least another via hole; setting a cutting line at the base portion; and The dicing wire cuts the semiconductor substrate.

In one embodiment, the step of setting the cutting line includes: setting the cutting line at the base portion and away from the emitter portion; and the step of cutting the semiconductor substrate includes: The semiconductor substrate is cut at the region of the emitter portion.

In one embodiment, the step of forming the first electrode includes: forming the first electrode including a first bus bar and a plurality of first finger electrodes extending from the first bus bar; and the step of forming the second electrode includes : forming a second electrode comprising a second bus bar and a plurality of second finger electrodes arranged to extend across the center of the first surface, the plurality of second finger electrodes extending from The second bus bar extends and intersects with the first finger electrode. In addition, setting the cut line at the base portion may include forming an opening extending across a center of the second bus bar to be the cut line.

In one embodiment, the step of forming a semiconductor base comprises forming said semiconductor base from a single semiconductor wafer by trimming at least two corner portions of said semiconductor wafer. Here, a plurality of photovoltaic devices may be formed from the single semiconductor wafer. In addition, the step of forming the first electrode may include: forming in each photovoltaic device a first electrode including a first bus bar and a plurality of first finger electrodes extending from the first bus bar in each photovoltaic device and the step of forming the second electrode may include: forming a second electrode including a second bus bar and a plurality of second finger electrodes extending from the second bus bar in each photovoltaic device.

In one embodiment, the method further includes: forming at least one of a passivation layer and an anti-reflection layer at the second surface of the semiconductor substrate.

In one embodiment, the method further comprises: texturing the second surface of the semiconductor substrate.

In one embodiment, each of the base portion and the emitter portion is formed to have a bar shape.

In one embodiment, each of the base portion and the emitter portion is formed as a plurality of discrete regions. Here, each discrete area may have a point shape, an ellipse, a circle, or a polygon shape.

In one embodiment, the second surface is formed as a front surface configured to face the light source, and the first surface is formed as a rear surface configured to face away from the light source.

Embodiments of the present invention provide a photovoltaic device. The photovoltaic device includes: a semiconductor substrate having a first surface and a second surface oppositely facing away from the first surface; a base portion and an emitter portion at the first surface; an insulating layer , located on the base portion and the emitter portion, the insulating layer has a plurality of through holes; the first electrode contacts the region of the emitter portion through at least one through hole; and the second electrode contacts the region of the emitter portion through at least one through hole; Another via contacts a region of the base portion. Here, the second electrode is a cut electrode, and the semiconductor substrate has only two trimmed corner portions at the emitter portion.

In one embodiment, the semiconductor substrate is formed from a semiconductor wafer and is about half (1/2) the size of the semiconductor wafer. Here, a portion of the second electrode may extend across the center of the semiconductor wafer.

In one embodiment, the first electrode includes a first bus bar extending between the two trimmed corner portions along the first edge of the semiconductor substrate and multiple bus bars extending from the first bus bar. a first finger electrode; and the second electrode includes a second bus bar extending along a second edge opposite to the first edge and extending from the second bus bar and connected to the first finger electrode A plurality of second finger electrodes spaced apart from each other.

In one embodiment, the photovoltaic device further includes: at least one of a passivation layer and an anti-reflection layer at the second surface of the semiconductor substrate.

In one embodiment, each of the base portion and the emitter portion is formed to have a bar shape.

In one embodiment, each of the base portion and the emitter portion is formed as a plurality of discrete regions.

In one embodiment, the insulating layer includes a first layer and a second layer of a material different from the first layer.

Description of drawings

Figure 1A is a schematic perspective view of a photovoltaic device according to an embodiment of the present invention;

Figure 1B is a cross-sectional view taken along the IB-IB line of Figure 1A;

2A is a rear view of a photovoltaic device showing first and second metal electrodes, an emitter layer, and a base layer, according to an embodiment of the present invention;

2B is a rear view of a photovoltaic device according to another embodiment of the present invention, showing first and second metal electrodes, an emitter layer, and a base layer;

3A is a perspective view of a semiconductor substrate during a process for fabricating a photovoltaic device, according to an embodiment of the present invention;

3B is a perspective view of a semiconductor substrate according to a modification of the embodiment shown in FIG. 3A;

4 is a perspective view of a state in which a passivation layer and an anti-reflection layer are formed during a process of manufacturing a photovoltaic device according to an embodiment of the present invention;

5A is a perspective view of a state in which a passivation layer and an anti-reflection layer are formed during a process of manufacturing a photovoltaic device according to an embodiment of the present invention;

Figure 5B is a cross-sectional view taken along the line VB-VB of Figure 5A;

6A is a perspective view of a state in which an insulating layer is formed during a process of manufacturing a photovoltaic device according to an embodiment of the present invention;

Figure 6B is a cross-sectional view taken along line VIB-VIB of Figure 6A;

7A is a perspective view of a state in which a first metal electrode and a second metal electrode are formed during a process of manufacturing a photovoltaic device according to an embodiment of the present invention;

Figure 7B is a cross-sectional view taken along line VIIB-VIIB of Figure 7A;

Figure 7C is a rear view of Figure 7A;

8A is a perspective view of a state in which a semiconductor substrate is cut along a cutting line C-C of FIG. 7A during a process of manufacturing a photovoltaic device according to an embodiment of the present invention;

Figure 8B is a rear view of Figure 8A;

Figures 9A and 9B show the results of measuring the quantum efficiency (QE) of comparative back-contact photovoltaic devices using the laser beam induced current (LBIC) method;

Figure 10 shows an embodiment of an electrically interconnected photovoltaic device according to an embodiment of the invention;

Figure 11 shows an embodiment of an electrically interconnected photovoltaic device according to another embodiment of the invention;

Figure 12 shows an embodiment of electrically interconnected photovoltaic devices according to another embodiment of the invention.

Detailed ways

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; The range fully conveys to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it means that the features, integers, steps, operations, elements and/or components exist, but does not exclude the existence or addition of one or more Various other features, integers, steps, operations, elements, components and/or groups thereof. Although terms such as 'first', 'second', etc. may be used to describe various components, the components are not limited by the above terms. That is, the above terms may be used only to distinguish one component from another. Like reference numerals refer to like elements throughout.

In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or one or more intervening layers may be disposed therebetween. or intermediate components. In contrast, when an element is referred to as being "directly on" another element or layer, there are no intervening elements or layers present.

FIG. 1A is a schematic perspective view of a photovoltaic device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line IB-IB of FIG. 1A . Figure 2A is a rear view of a photovoltaic device according to an embodiment of the present invention, showing first and second metal electrodes, an emitter layer and a substrate layer, and Figure 2B is a rear view of a photovoltaic device according to another embodiment of the present invention view, showing the first and second metal electrodes, the emitter layer and the base layer.

For ease of explanation, Figures 1A and 1B show the rear surface of the photovoltaic device facing upwards, and Figures 2A and 2B show regions doped with impurities and using dashed lines to form the emitter layer (part) and base layer (part) .

1A and 1B, photovoltaic device 100 includes semiconductor substrate 110, passivation layer 120, anti-reflection layer 130, emitter layer (emitter part) 140, substrate layer (base part) 150, insulating layer 160 and a first The metal electrode 170 and the second metal electrode 180 .

The semiconductor substrate 110 is a light absorbing layer. Here, the edge of the first side 111 of the semiconductor substrate 110 is trimmed, and the edge of the second side 112 of the semiconductor substrate is not trimmed. Typically, four edges of the semiconductor substrate are trimmed. However, according to an embodiment of the present invention, the semiconductor substrate 110 corresponds to half of a general semiconductor substrate, wherein only two of the four edges (ie, only the edges of the two opposite ends of the first side 111 ) are trimmed. The size of the semiconductor substrate 110 may be half or more of a 5" wafer or a 6" wafer.

The semiconductor substrate 110 may include a single crystal silicon substrate or a polycrystalline silicon substrate. The semiconductor substrate 110 may be a single crystal silicon substrate or a polycrystalline silicon substrate doped with n-type impurities. The n-type impurities may include group V elements such as phosphorus (P) and arsenic (As).

Although the semiconductor substrate 110 doped with n-type impurities is employed in the current embodiment, the current embodiment is not limited thereto. For example, the semiconductor substrate 110 may be a single crystal silicon substrate or a polycrystalline silicon substrate doped with p-type impurities. The p-type impurities may include Group III elements such as boron (B), aluminum (Al), or gallium (Ga).

Although not shown, the semiconductor substrate 110 may include a textured structure. The textured structure may reduce reflection of incident light by using internal reflection from the rear surface of the semiconductor substrate 110, increase the length of light traveling within the semiconductor substrate 110, and increase the amount of light absorbed. Therefore, the short-circuit current of the photovoltaic device 100 can be increased.

A passivation layer 120 may be formed on the front surface of the semiconductor substrate 110 . The passivation layer 120 may include amorphous silicon (a-Si) doped with impurities, or may include silicon nitride (SiN _x ). In the case where the passivation layer 120 contains a-Si doped with impurities, the passivation layer 120 may be doped with impurities having the same conductivity type as the impurities of the semiconductor substrate 110 at a concentration higher than that of the semiconductor substrate 110. .

The passivation layer 120 may improve the efficiency of carrier collection by blocking or preventing surface recombination of carriers generated in the semiconductor substrate 110 . For example, the passivation layer 120 may prevent electrons and holes from recombining and being consumed near the front surface of the semiconductor substrate 110 because the passivation layer 120 prevents carriers from moving toward the front surface of the semiconductor substrate 110 .

The anti-reflection layer 130 is formed on the front surface of the semiconductor substrate 110 and may improve efficiency of the photovoltaic device 100 by preventing light absorption loss of the photovoltaic device 100 due to light reflection during incidence of sunlight. The anti-reflection layer 130 may contain a transparent material. For example, the anti-reflection layer 130 may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiO _x N _y ). Alternatively, the anti-reflection layer 130 may contain titanium oxide (TiO _x ), zinc oxide (ZnO) or zinc sulfide (ZnS). The anti-reflection layer 130 may be formed by stacking a single layer or a plurality of layers having different refractive indices.

Although the passivation layer 120 and the anti-reflection layer 130 are represented as separate layers in the presently illustrated embodiment, the present invention is not limited thereto. For example, a silicon nitride (SiN _x ) layer may be formed to function as both the passivation layer 120 and the antireflection layer 130 .

The emitter layer 140 is formed on the rear surface of the semiconductor substrate 110 and forms a p-n junction with the semiconductor substrate 110 . In the case where the semiconductor substrate 110 is doped with n-type impurities, the emitter layer 140 includes p-type impurities. In case the semiconductor substrate 110 is doped with p-type impurities, the emitter layer 140 includes n-type impurities.

Referring to FIG. 2A , the emitter layer 140 is formed by doping p-type impurities (or n-type impurities) into the semiconductor substrate 110, and the diffusion region may be in a stripe shape. That is, in one embodiment, the emitter layer (emitter part) 140 is formed to have a stripe shape.

Alternatively, referring to FIG. 2B , the diffusion region (emitter portion) 140 ′ of p-type impurities (or n-type impurities) may be a dot type having a circular or elliptical shape. The dot type diffusion area 140' may also have a polygonal shape. That is, in one embodiment, emitter portion 140' is formed as a plurality of discrete regions. Here, in one embodiment, each discrete region 140' has a dot shape, an ellipse shape, a circle shape or a polygon shape, as indicated by a dotted line in FIG. 2B.

Referring back to FIGS. 1A , 1B and 2A , the emitter layer 140 is formed along the first side 111 of the semiconductor substrate 110 having two trimmed edges, and is also formed in a direction perpendicular to the first side 111 . That is, in one embodiment, the emitter layer 140 includes a first emitter region 141 formed along the first side 111 and a plurality of second emitter regions 142 formed along a direction substantially perpendicular to the first emitter region 141. . The second emitter regions 142 are spaced apart from each other.

The base layer 150 is formed on the rear surface of the semiconductor substrate 110 and contains the same type of impurities as those of the semiconductor substrate 110 . The base layer 150 is doped with impurities at a concentration higher than that of the semiconductor substrate 110 to form a back surface field (BSF) so that holes and electrons may be prevented from recombining and being consumed near the second metal electrode 180 .

Referring to FIG. 2A , a base layer (base portion) 150 is formed by doping n-type impurities (or p-type impurities) into the semiconductor substrate 110, and the diffusion region may be in a stripe type. That is, in one embodiment, the base layer (base portion) 150 is formed to have a stripe shape.

Alternatively, referring to FIG. 2B , the diffusion region 150 ′ of n-type impurities (or p-type impurities) may be a dot type having a circular or elliptical shape. The dot type diffusion area 150' may also have a polygonal shape. That is, in one embodiment, the diffusion region (base portion) 150' is formed as a plurality of discrete regions. Here, in one embodiment, each discrete region 150' has a dot shape, an ellipse shape, a circle shape or a polygon shape, as indicated by a dotted line in FIG. 2B.

Referring to FIGS. 1A , 1B and 2A , the base layer 150 is formed along the second side 112 of the semiconductor substrate 110 having two untrimmed edges, and is also formed in a direction perpendicular to the second side 112 . That is, in one embodiment, the base layer 150 includes a first base region 151 formed along the second side 112 and a plurality of second base regions 152 formed along a direction substantially perpendicular to the first base region 151 .

The second base body region 152 is arranged between the second emitter regions 142 spaced apart from one another. Accordingly, the second emitter region 142 and the second body region 152 are formed to be alternate with each other on the rear surface of the semiconductor substrate 110 .

An insulating layer 160 is formed on the emitter layer 140 and the base layer 150 and under the first metal electrode 170 and the second metal electrode 180 to prevent (or protect) between components having opposite conductivity types (opposite polarity) (or free from) a short circuit. For example, the insulating layer 160 prevents an electrical short between the first metal electrode 170 and the base layer 150 and prevents an electrical short between the second metal electrode 180 and the emitter layer 140 .

The insulating layer 160 includes via holes (eg, through holes) 165 via (through) the via holes 165 through which the first metal electrode 170 and the second metal electrode 180 may directly contact the emitter layer 140 and the base layer 150 , respectively. Through the through hole 165 , the first metal electrode 170 may be electrically connected to the emitter layer 140 , and the second metal electrode 180 may be electrically connected to the base layer 150 .

The insulating layer 160 may include a first insulating layer 161 and a second insulating layer 162 . For example, the first insulating layer 161 may contain silicon oxide ( _SiOx ), silicon nitride ( _SiNx ), or both _SiOx and _SiNx . The second insulating layer 162 is formed to secure electrical insulation (or to be stronger) after forming the first insulating layer 161 , and may contain polyimide (PI). Alternatively, the second insulating layer 162 may include ethylene vinyl acetate (EVA), polyethylene terephthalate (PET), or polycarbonate (PC).

Although in the current embodiment, the insulating layer 160 includes the first insulating layer 161 and the second insulating layer 162, the present invention is not limited thereto. The second insulating layer 162 may be formed for securing electrical insulation after the first insulating layer 161 is formed, and may be optional, and thus, the insulating layer 160 may include only the first insulating layer 161 .

The first metal electrode 170 is disposed on the insulating layer 160 to correspond to the emitter layer 140 , and may be electrically connected to the emitter layer 140 through the through hole 165 . The first metal electrode 170 may contain silver (Ag), gold (Au), copper (Cu), aluminum (Al), or alloys thereof. The first metal electrode 170 may include a first bus bar 171 and a first finger electrode 172 formed to extend from the first bus bar 171 (for example, formed to be perpendicular to the first bus bar 171 ).

The second metal electrode 180 is disposed on the insulating layer 160 to correspond to the base layer 150 , and may be electrically connected to the base layer 150 through the through hole 165 . The second metal electrode 180 may contain silver (Ag), gold (Au), copper (Cu), aluminum (Al), or alloys thereof. The second metal electrode 180 may include a second bus bar 181 and a second finger electrode 182 formed to extend from the second bus bar 181 (for example, formed to be perpendicular to the second bus bar 181 ).

The first bus bar 171 is formed at the first side 111 of the semiconductor substrate 110 , and the second bus bar 181 is formed at the second side 112 of the semiconductor substrate 110 so as to be substantially parallel to the first bus bar 171 . The first finger electrodes 172 extend toward the second bus bar 181 along a direction perpendicular to the first bus bar 171 , and the second finger electrodes 182 extend toward the first bus bar 171 along a direction perpendicular to the second bus bar 181 . The first finger electrodes 172 and the second finger electrodes 182 are alternately arranged. In other words, the first finger electrode 172 and the second finger electrode 182 may be formed to be spaced apart from each other and collect carriers.

In the case of manufacturing a general back-contact photovoltaic device, even if the light-receiving area is increased, when the current increases according to the increase in the light-receiving area, a power loss proportional to the square of the current is caused, and therefore, relative to The gain in area increase will not be large enough. However, according to an embodiment of the present invention, the photovoltaic device is formed by cutting the wafer in half, and therefore, the voltage can be approximately doubled and the current can be reduced. Therefore, power loss proportional to the square of the current can be reduced. For example, in one embodiment, the second electrode 180 is a cut electrode. That is, in one embodiment, the second bus bar 181 of the second electrode 180 may be formed by cutting a larger bus bar into two parts, as will be described in more detail below.

In addition, since the photovoltaic device according to the embodiment of the present invention is manufactured by cutting the region of the base part (ie, cutting the region of the base part away from the emitter part), it is possible to reduce or prevent power loss during the manufacture of the photovoltaic device. loss.

Hereinafter, a method of manufacturing a photovoltaic device will be described.

3A to 8B schematically illustrate states of a method of manufacturing a photovoltaic device according to an embodiment of the present invention. For ease of explanation, FIGS. 3A to 8B show the rear surface of the photovoltaic device facing upward.

Referring to FIG. 3A , a semiconductor substrate (eg, semiconductor wafer) 310 is provided. The four edges of the semiconductor substrate 310 are trimmed, and the size of the semiconductor substrate (wafer) 310 may be 5 inches, 6 inches or larger. As an example, in one embodiment, a single semiconductor wafer of 5 inches, 6 inches or larger is used to form multiple photovoltaic devices. However, the invention is not so limited and other suitable types or numbers of semiconductor wafers or substrates may be utilized.

The semiconductor substrate 310 may include a single crystal silicon substrate or a polycrystalline silicon substrate. The semiconductor substrate 310 may be a single crystal silicon substrate or a polycrystalline silicon substrate doped with n-type impurities or p-type impurities. In the current embodiment, for convenience of explanation, a case where the semiconductor substrate 310 contains n-type impurities will be described.

A cleaning operation using an acid solution or an alkali solution may be performed to remove physical impurities and/or chemical impurities attached to the surface of the semiconductor substrate 310 .

Referring to FIG. 3B, a semiconductor substrate 310' according to another embodiment of the present invention may have a rough surface formed in a texturing operation. The textured structure may be formed via anisotropic wet etching or plasma dry etching. A passivation layer and an anti-reflection layer described below may be formed on the rough surface formed in the texturing operation.

Hereinafter, for convenience of explanation, a process of manufacturing a photovoltaic device using the semiconductor substrate 310 shown in FIG. 3A will be described.

Referring to FIG. 4, a passivation layer 320 and an anti-reflection layer 330 are formed on the front surface of the semiconductor substrate 310 in the following order. Before forming the passivation layer 320, the semiconductor substrate 310 may be cleaned.

The passivation layer 320 may include a-Si doped with impurities. For example, the passivation layer 320 may be formed on the front surface of the semiconductor substrate 310 as a high-concentration n+ layer, and the passivation layer 320 may form a front surface field (FSF) to reduce losses due to recombination of holes and electrons.

According to another embodiment of the present invention, the passivation layer 320 may include silicon nitride (SiN _x ). The passivation layer 320 may be formed by using a plasma enhanced chemical vapor deposition (PECVD) method.

Since the passivation layer 320 is formed on the light receiving surface of the semiconductor substrate 310, a bandgap may be adjusted to reduce light absorption. For example, additives may be added to increase the bandgap to reduce light absorption and thus allow more incident light to pass into the interior of the semiconductor substrate 310 .

The anti-reflection layer 330 may be formed of silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiO _x N _y ) by using a method such as CVD, sputtering, or spin coating. For example, the anti-reflection layer 330 may be formed as a single silicon oxide (SiO _x ) layer, a single silicon nitride (SiN _x ) layer, or a single silicon oxynitride (SiO _x N _y ) layer, or include silicon oxide (SiO _x ), Composite layer of silicon nitride (SiN _x ) and silicon oxynitride (SiO _x N _y ).

Although the passivation layer 320 and the anti-reflection layer 330 are formed as separate layers in the current embodiment, the present invention is not limited thereto. For example, the passivation layer 320 and the antireflection layer 330 may be integrally formed as a single layer. In other words, a silicon nitride (SiN _x ) layer may be formed for passivation and anti-reflection.

Referring to FIGS. 5A and 5B , a base layer (base portion) 350 and an emitter layer (emitter portion) 340 are formed on the rear surface of the semiconductor substrate 310 . The base layer 350 and the emitter layer 340 may be formed by doping impurities into the semiconductor substrate 310 in the form of stripes.

According to an embodiment of the present invention, the base layer 350 and the emitter layer 340 may be formed by doping impurities of opposite conductivity types into different regions of the rear surface of the semiconductor substrate 310 . First, n-type impurities can be doped into the semiconductor substrate 310 across the central region of the rear surface of the semiconductor substrate 310 to form the first body region 351, and the n-type impurities can be doped in a direction perpendicular to the first body region 351. dopant into the semiconductor substrate 310 to form the second body region 352 . Here, the second body regions 352 doped with n-type impurities are formed to be separated from each other by a set or predetermined interval.

Next, the emitter layer 340 may be formed by doping p-type impurities into the remaining regions (ie, regions other than the region doped with n-type impurities). Thus, regions of emitter layer 340 are formed on two different sides around one region of base layer 350, emitter layer 340 comprising a first emitter region 341 and a second emitter region substantially perpendicular to first emitter region 341. The body region 342 , wherein the second emitter region 342 is formed to be spaced apart from the second body region 352 .

According to another embodiment of the present invention, the base layer 350 is formed to cover the entire rear surface of the semiconductor substrate 310 , and then the emitter layer 340 may be formed by selectively doping impurities into portions of the base layer 350 . For example, after doping the entire rear surface of the semiconductor substrate 310 with n-type impurities, regions of the rear surface of the semiconductor substrate 310 may be doped with a high concentration of p-type impurities to form the emitter layer (portion) 340 . Here, a region doped with a high concentration of p-type impurities is shown as an emitter layer 340 in FIG. 5A.

Although the base layer 350 and the emitter layer 340 are stripe-type doped regions, impurities may also be doped in discrete regions (eg, to form dot shapes). In the case of doping of impurities in discrete regions (for example, to have a dot shape), the body doped regions and emitter doped regions are as described above with reference to FIG. 2B .

Referring to FIGS. 6A and 6B , an insulating layer 360 is formed on the base layer 350 and the emitter layer 340 . The insulating layer 360 may be formed to include two layers. For example, after the first insulating layer 361 including silicon oxide (SiO _x ) and silicon nitride (SiN _x ) is formed by using a CVD method, the second insulating layer 362 may be formed to improve electrical insulation.

The second insulating layer 362 may include polyimide (PI). Alternatively, the second insulating layer 162 may comprise ethylene vinyl acetate (EVA), polyethylene terephthalate (PET) or polycarbonate (PC)

Next, via holes (eg, through holes) 365 are formed in the insulating layer 360 to partially expose the base layer 350 and the emitter layer 340 (see FIG. 7B ). Although not shown, the through hole 365 may be formed by forming an etch mask (not shown) on the insulating layer 360 and etching a portion of the insulating layer 360 exposed by the etch mask.

The base layer 350 may be partially exposed through (through) some of the plurality of through holes 365 , and the emitter layer 340 may be partially exposed through (through) the remaining through holes 365 . Some through-holes 365 are used for electrical connection between the emitter layer 340 and the first metal electrode 370 , while the remaining through-holes 365 are used for electrical connection between the base layer 350 and the second metal electrode 380 .

Referring to FIGS. 7A to 7C , a first metal electrode 370 and a second metal electrode 380 are formed.

First metal electrodes 370 are formed at both opposite ends of the rear surface of the semiconductor substrate 310 . At least a portion of the first metal electrode 370 contacts the doped emitter layer 340 . The first metal electrodes 370 each include a first bus bar 371 and a first finger electrode 372 formed to extend from the first bus bar 371 (eg, in a direction perpendicular to the first bus bar 371 ).

The second metal electrode 380 is formed at the center of the rear surface of the semiconductor substrate 310 . For example, the second metal electrode 380 includes a second bus bar 381 arranged across the center of the semiconductor substrate 310 and second finger electrodes formed at two opposite sides around the second bus bar 381 and extending toward the first metal electrode 370 . 382. For example, the second finger electrode 382 extends in a direction substantially perpendicular to the second bus bar 381 . The second finger electrodes 382 may be formed to be spaced apart from the first finger electrodes 372 and collect carriers.

The first metal electrode 370 may be formed by screen printing a pattern formed of a conductive paste containing silver (Ag), gold (Au), copper (Cu), aluminum (Al), or nickel (Ni) and thermally baking the pattern. and the second metal electrode 380 .

According to another embodiment of the present invention, the first metal electrode 370 and the second metal electrode 380 may be formed by plating. After forming a seed layer contacting the emitter layer 340 and the base layer 350 through (via) the through holes (eg, through holes) 365 , a metal may be plated on the seed layer.

In one embodiment of the present invention, when forming the second metal electrode 380 , an opening (for example, a hole) h at the center of the second bus bar 381 in the length direction is formed (see FIGS. 7A and 7C ). For example, in one embodiment, during the formation of the second metal electrode 380, paste or metal plating is applied at the area other than the area corresponding to the opening h, so that at the center of the second bus bar 381 No metal was formed. A line C-C across the opening h formed at the center of the second bus bar 381 becomes a cutting line. That is, the cutting line may be an opening (eg, a hole) h in the second metal electrode 380 , but the present invention is not limited thereto. However, in another embodiment of the present invention, the cutting line does not have to be an opening or a hole, and may only be a sign where the second metal electrode 380 should be cut (ie, at the base portion 350), and at the No opening or hole is actually formed in the second metal electrode (eg, no hole is formed in the second bus bar 381 of the second metal electrode 380 ).

Referring to FIGS. 8A and 8B , two photovoltaic devices may be formed by cutting the semiconductor substrate 310 along a cutting line (eg, cutting into two separate semiconductor substrate portions). The semiconductor substrate 310 may be cut by using laser scribing. Alternatively, the semiconductor substrate 310 may be cut by using a wire saw. In one embodiment of the invention, possible power losses in the manufacture of photovoltaic devices can be reduced because the cutting is performed relative to (or at) the base portion of the photovoltaic device and away from the emitter region Or it can be minimized. A detailed description thereof will be given below.

9A and 9B show the results of measuring the quantum efficiency (QE) of comparative back-contact photovoltaic devices using the laser beam induced current (LBIC) method.

Referring to FIGS. 9A and 9B , base regions of the base portion are indicated as dark regions D1 and D2 . A dark base area indicates that the current is significantly lower in the corresponding area. In other words, the base area contributes little to the efficiency of the photovoltaic device.

Since according to an embodiment of the present invention, the base area of the base portion is moved toward the center of the semiconductor substrate (wafer) and used as a cutting area, losses due to damaged areas formed during the cutting operation can be reduced or minimized .

As described above, compared with the finger electrodes of the photovoltaic device in the comparison device, the first metal electrode 170 and the second metal electrode 180 of the photovoltaic device according to the embodiment of the present invention may have finger electrodes 172 and 182 with relatively small lengths. , so the power loss can be reduced. In addition, since the thickness of the metal electrodes 170 and 180 can be reduced, costs for forming the first metal electrode 170 and the second metal electrode 180 can be reduced, and warping of the semiconductor substrate 110 can be reduced or prevented.

Also, according to the manufacturing method of the present invention, a plurality of photovoltaic devices can be produced, and the number of processes can be reduced or minimized. For example, two photovoltaic devices can be manufactured by one process cycle (1 cycle) explained with reference to FIGS. 3A to 8B . Thus, high efficiency photovoltaic devices can be produced with reduced or minimized cost and time.

In addition, according to an embodiment of the present invention, a photovoltaic device is formed by cutting one semiconductor wafer in half, and therefore, a voltage can be approximately doubled and a current can be reduced. Therefore, current-related losses can be further reduced.

10 to 12 illustrate embodiments of electrically connected photovoltaic devices according to other embodiments of the present invention.

Referring to Figures 10-12, modules can be fabricated by electrically interconnecting multiple photovoltaic devices using a combination of series and parallel connections using ribbons.

Referring to FIG. 10 , a single module can be formed by using a series connection of a first bus bar 171 arranged at a first end of one photovoltaic device 100 with a ribbon 10 and interconnecting photovoltaic devices 100 in a row in parallel. The second bus bar 181 arranged at the second end of the other photovoltaic device 100 is interconnected.

Referring to FIG. 11 , a single module can be formed by connecting the photovoltaic devices 100 in series using a parallel connection by connecting a second bus bar 181 arranged at the first end of one photovoltaic device 100 with a ribbon 20 . The second bus bar 181 at the first end of the other photovoltaic device 100 is interconnected.

Similarly, referring to FIG. 12 , photovoltaic devices 100 can be connected in series and groups of The photovoltaic devices 100 connected in series are interconnected in parallel to form a single module.

In addition to the embodiments described above, a plurality of photovoltaic devices may also be connected to each other in series and/or in parallel by (via) any of various suitable combinations and arrangements.

According to the above description, embodiments of the present invention provide a method of manufacturing a photovoltaic device. Here, the method includes providing a semiconductor substrate (eg, a semiconductor wafer). Then, a base portion and an emitter portion are formed on the surface of the semiconductor substrate. An insulating layer is formed on the base portion and the emitter portion. The insulating layer has a plurality of through holes to partially expose the base portion and the emitter portion. The first electrode is formed to contact the area of the emitter portion through at least one via hole, and the second electrode is formed to contact the area of the base portion through at least one other via hole. Then, a cutting line is provided at the bus electrode portion of the second electrode, and the semiconductor substrate is divided into two photovoltaic devices at the base portion along the cutting line. Thus, according to an embodiment of the present invention, two photovoltaic devices are formed by cutting one semiconductor wafer in half, so the voltage can be approximately doubled, and the current can be reduced due to two photovoltaic devices formed from one wafer . Therefore, current loss can be reduced.

In addition, since the base region of the base part is used according to the invention as the cutting region, and since the base region hardly contributes to the efficiency of the photovoltaic device, the loss due to the cut or damaged base region formed during the above-mentioned cutting operation Does not significantly affect the formed photovoltaic device.

While the invention has been shown and described with reference to preferred embodiments of the invention, it will be understood by those skilled in the art that changes may be made in form and without departing from the spirit and scope of the invention as defined in the claims. Various changes in details. The described embodiments should be considered in a descriptive sense only and not for purposes of limitation. Therefore, the scope of the invention is defined not by the detailed description of the invention but by the appended claims and their equivalents.

Label description

110, 310: semiconductor substrate 120, 320: passivation layer

130, 330: anti-reflection layer 140, 340: emitter layer (part)

150, 350: substrate layer (part) 160, 360: insulating layer

161, 361: first insulating layer 162, 362: second insulating layer

170, 370: the first metal electrode 171, 371: the first bus bar

172, 372: the first finger electrode 180, 380: the second metal electrode

181, 381: the second bus bar 182, 382: the second finger electrode

Claims (21)

1. method of making photovoltaic devices, described method comprises the steps:

Formation has the semiconductor base of first surface and second surface, and described second surface relatively deviates from described first surface;

Form base stage part and emitter part at described first surface place;

Form insulating barrier in described base stage part and described emitter portion;

In described insulating barrier, form a plurality of through holes, partly to expose described base stage part and described emitter portion;

Form the first electrode, to contact the zone of described emitter portion by at least one through hole;

Form the second electrode, to contact the zone of described base stage part by another through hole at least;

Partly locate to arrange line of cut in described base stage; And

Cut described semiconductor base along described line of cut.

2. method according to claim 1, wherein:

The step that line of cut is set comprises: partly locate and away from described emitter portion described line of cut is set in described base stage; And

The step of cutting semiconductor substrate comprises: the location away from described emitter portion at described semiconductor base is cut described semiconductor base.

3. method according to claim 1, wherein:

The step that forms the first electrode comprises: the first electrode that forms a plurality of the first finger electrodes comprise the first busbar and to extend from described the first busbar; And

The step that forms the second electrode comprises: form the second electrode that comprises the second busbar and a plurality of the second finger electrodes, described the second busbar is arranged to across the center of described first surface and extends, and described a plurality of the second finger electrodes are from described the second busbar extension and alternate each other with described the first finger electrode.

4. method according to claim 3, wherein, the step of partly locating to arrange line of cut in base stage comprises: form the opening that extends across the center of described the second busbar, to become described line of cut.

5. method according to claim 1, wherein, the step that forms semiconductor base comprises: assign to form described semiconductor base from single semiconductor wafer by at least two bights of repairing described semiconductor wafer.

6. method according to claim 5 wherein, forms a plurality of photovoltaic devices from described single semiconductor wafer.

7. method according to claim 6, wherein:

The step that forms the first electrode comprises: the first electrode that is formed on a plurality of the first finger electrodes that comprise the first busbar in each photovoltaic devices and extend from described the first busbar in each photovoltaic devices; And

The step that forms the second electrode comprises: the second electrode that forms a plurality of the second finger electrodes comprise the second busbar and to extend from described the second busbar in each photovoltaic devices.

8. method according to claim 1, described method also comprises the steps:

In the described second surface place of described semiconductor base formation passivation layer and antireflection layer at least one.

9. method according to claim 1, described method also comprises the steps:

Described second surface veining with described semiconductor base.

10. method according to claim 1, wherein, each in described base stage part and the described emitter portion is formed has strip.

11. method according to claim 1, wherein, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.

12. method according to claim 11, wherein, each zone of dispersion has a shape, ellipse, circle or polygonal shape.

13. method according to claim 1, wherein, described second surface is formed the front surface that is configured in the face of light source, and described first surface is formed the rear surface that is configured to deviate from described light source.

14. a photovoltaic devices, described photovoltaic devices comprises:

Semiconductor base has first surface and second surface, and described second surface relatively deviates from described first surface;

Base stage part and emitter portion are positioned at described first surface place;

Insulating barrier is positioned on described base stage part and the described emitter portion, and described insulating barrier has a plurality of through holes;

The first electrode contacts the zone of described emitter portion by at least one through hole; And

The second electrode contacts the zone of described base stage part by another through hole at least,

Wherein, described the second electrode is cutting electrode; And

Wherein, described semiconductor base only has two angle parts that are trimmed at described emitter portion place.

15. photovoltaic devices according to claim 14, wherein, described semiconductor base is formed by semiconductor wafer, and is half of size of described semiconductor wafer.

16. photovoltaic devices according to claim 15, wherein, the part of described the second electrode is extended across the center of described semiconductor wafer.

17. photovoltaic devices according to claim 14, wherein:

Described the first electrode comprises the first busbar that extends along the first edge of described semiconductor base and a plurality of the first finger electrodes that extend from described the first busbar between the angle part of described two finishings; And

Described the second electrode comprise the second busbar of extending along the second edge relative with described the first edge and from described the second busbar extend and with described the first finger electrode alternate a plurality of the second finger electrodes each other.

18. photovoltaic devices according to claim 14, described photovoltaic devices also comprises:

In passivation layer and the antireflection layer at least one is positioned at the described second surface place of described semiconductor base.

19. photovoltaic devices according to claim 14, wherein, each in described base stage part and the described emitter portion is formed has strip.

20. photovoltaic devices according to claim 14, wherein, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.

21. photovoltaic devices according to claim 14, wherein, described insulating barrier comprises the second layer that ground floor and material are different from the material of described ground floor.

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