CN103034562A - Meta data handling within a flash media controller - Google Patents
Meta data handling within a flash media controller Download PDFInfo
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- CN103034562A CN103034562A CN2012102442055A CN201210244205A CN103034562A CN 103034562 A CN103034562 A CN 103034562A CN 2012102442055 A CN2012102442055 A CN 2012102442055A CN 201210244205 A CN201210244205 A CN 201210244205A CN 103034562 A CN103034562 A CN 103034562A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7207—Details relating to flash memory management management of metadata or control data
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Abstract
The invention discloses meta data handling within a flash media controller. A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.
Description
The application requires the right of priority of No. the 13/334th, 599, the U.S. utility application of No. the 61/507th, 659, U.S. Provisional Application submitting on July 14th, 2011 and submission on Dec 22nd, 2011, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates in general to the flash media system, especially, relates to method and/or device for the treatment of the metadata in the flash media controller.
Background technology
Flash memories is attractive in the mass memory environment, because flash memory system does not have the relevant mechanical delay of hard disk.Therefore, flash memory system allows higher performance and relatively low cost, power, heating (heating) and space utilization rate.Yet because some technical restriction, flash memories also is not used for these environment traditionally.First technical matters is writing speed, its may with mechanical hard disk drive on speed 1/10th the same slow of sequential access.Writing speed is owing to data before not long erase cycle can not be written (overwrite) on the nand flash memory device slowly.Because erase cycle directly affects write performance, most of flash memory design moves to reposition with data writing, and postpones to wipe backward.In busy system, until processor is used up the free flash memory page or leaf and must be stopped to create new Hash memory pages, just can make up the erase cycle that is delayed, this affects system performance greatly.Second technical matters be, to 100,000 erase cycle of each Hash memory pages of single stage unit (" SLC ") device and to the concrete restriction in multi-level unit (" MLC ") 10,000 cycles of device.The restricted number of erase cycle has caused the particular problem of data center, and wherein, unpredictable data stream may cause the specific highly memory partition of use to be subject in a large number wiping.The 3rd problem is loss of data.Loss of data may occur because affecting the various factors of flash memory, comprises reading disturbing or the programming interference, loses thereby produce by the contiguous data bit that causes that reads or write that is disturbed the storage unit of unit.The state of flash memory cell also may change because of the passing of time unpredictablely.
In flash memory technology, the flash memory management function is implemented in firmware.The flash memory management function comprises flash memory cache management, defect management, wear leveling.All management functions utilize some flush memory device storeies to come the used ephemeral data of storing firmware or other information.Ephemeral data and information that the firmware of storing in Hash memory pages is used are commonly called metadata at this paper.
Expectation realizes a kind of method and/or the device for the treatment of the metadata in the flash media controller.
Summary of the invention
The present invention relates in a kind of flash media controller for the treatment of the method that is stored in the metadata in the flash memories page or leaf.The method generally comprises: (ⅰ) in each context basis (basis) definition metadata, wherein, context defines based on each page, (ii) when the size of metadata during less than or equal to predetermined threshold, with whole metadata store in context mechanism, and (iii) when the size of metadata during greater than predetermined threshold, definition metadata pointer in context.
Purpose of the present invention; function and advantage comprise method and/or the device that is provided for processing the metadata in the flash media controller; it can (i) define metadata information on each context basis; wherein; context defines based on each page; (ii) when the size of metadata during less than or equal to predetermined threshold; complete metadata information is stored in the context mechanism; (iii) when the size of metadata during greater than predetermined threshold; the pointer of metadata is pointed in definition in context; (iv) distribute with the metadata of host subscriber's data, and/or (v) encode with error recovery; metadata is protected in completeness check and correction.
Description of drawings
From following detail specifications and appended claims and accompanying drawing, above and other purpose, feature and advantage will become apparent, wherein:
Fig. 1 shows the block diagram of the flash media controller of realizing in system-on-a-chip (SOC) environment;
Fig. 2 shows the block diagram according to example flash medium controller (FMC) structure of embodiment of the present invention;
Fig. 3 shows the block diagram according to the example flash channel controller structure of embodiment of the present invention;
Fig. 4 shows the diagram of example submodule of the context manager module of Fig. 3;
Fig. 5 shows the diagram of example submodule of the nude film administration module of Fig. 3;
Fig. 6 shows the diagram of example submodule of the flash disk operation manager module of Fig. 3;
Fig. 7 shows the diagram of example submodule of the data stream manager module of Fig. 3;
Fig. 8 shows the diagram of the example submodule of the context manager module that has realized Fig. 3; And
Fig. 9 shows the diagram that the example of the flash disk operation manager of Fig. 3 is implemented;
Figure 10 shows the diagram according to the contextual layout of example flash medium of embodiment of the present invention;
Figure 11 shows the diagram according to the example partition sections in the Hash memory pages of embodiment of the present invention;
Figure 12 A and Figure 12 B show the diagram according to the example FMC Hash memory pages structure of embodiment of the present invention; And
Figure 13 shows explanation according to the process flow diagram of the processing of embodiment of the present invention.
Embodiment
In an implementation, system according to the present invention can be designed as by various large capacity storage agreements and operates, comprise SAS(" Serial Attached SCSI (SAS) "), FC(" optical-fibre channel ") and FC-AL(" FC-AL road "), all these is based on small computer system interface (" SCSI ") agreement and serial ATA (" SATA ") agreement.Those of ordinary skills should be familiar with these large capacity storage agreements, and therefore, such agreement can further not discussed in this article.Unless calling in the situation of specific protocol, system and method disclosed herein does not rely on the specific protocol of using, and be designed to carry out proper operation by institute's protocols having.In addition, go for using or other similar agreements of in the future exploitation are used at present according to the system and method for embodiment of the present invention, these agreements comprise for the agreement of enterprise-level application and are used for other application protocols such as the final user.System as herein described comprises new method and/or the device for the flash controller hardware structure of realizing flush memory device.
With reference to Fig. 1, it shows the block diagram by the system 100 that realizes according to the flash media controller of embodiment of the present invention.In one example, system's (or structure) 100 can comprise piece (or circuit) 102, a plurality of (or circuit) 104a to 104n, a plurality of (or circuit) 106a to 106n, piece (or circuit) 18, piece (or circuit) 110, piece (or circuit) 112, piece (or circuit) 114, piece (or circuit) 116.Circuit 102 to 116 can represent to be implemented as combination or other module and/or the piece of hardware, firmware, software, hardware, firmware and/or software.
In one example, piece 102 can be realized the flash media controller (FMC) according to embodiment of the present invention.Piece 104a to 104n may be implemented as flash memory spare or the element of the first quantity.Piece 104a can be coupled to the first flash memory passage of piece 102 to piece 104n.The first flash memory passage of piece 102 can be configured to provide independently chip to enable (CE) signal to each piece 104a to 104n.Piece 106a may be implemented as flash storage device or the parts of the second quantity to piece 106n.Piece 106a can be coupled to the second flash memory passage of piece 102 to piece 106n.The second flash memory passage of piece 102 can be configured to provide independently chip to enable (CE) signal to each piece 106a to piece 106n.Although FMC102 is illustrated with the example of two flash memory passages, it will be apparent for a person skilled in the art that and to realize correspondingly that other flash memory passage is to satisfy the design standards of specific implementation.Flush memory device 104a to 104n and 106a to 106n may be implemented as the single flash memory set (flash package) that comprises one or more nude films.Flush memory device 104a to 104n and 106a to 106n are by realizing with NAND and/or NOR flush memory device.Piece 102 can comprise the suitable Physical layer support (PHY) for nand flash memory and/or NOR flash memory.
In one example, the feature that can support of piece 102 comprises: (i) two flash memory passages; (ii) on each flash memory passage up to eight chip enable signal (CE); (ⅲ) flash interface comprises asynchronous normal mode, asynchronous mode of extension, Toggle1.0, ONFI2.3, ONFI2.1, Toggle2.0; (iv) the special-purpose ECC between the configurable a plurality of passages of hardware or sharing E CC(for example realize the parameter characteristic of the soft IP bag of piece 102); (v) 8 bit data on the flash interface; (the vi) DDR speed up to 200MHz on the flash interface of the flash interface standard of Toggle2.0 or ONFI2.3; (vii) part reading order, (viii) reading order at random; (ix) CRC deletion/insertion (strip/insert) option that writes/read about flash memory; (x) to the correction of 4K byte data up to 64; (xii) 512, the configurable n bit correction (n maximal value=64) on 2K, the 4K byte data; (xii) be used for 32 AHB interfaces that register is programmed; (xiii) the externally storage on the storer (such as DRAM or SRAM) of context commands; (xiv) the straight-through impact damper (cut-throughbuffer) in the flash memory channel controller; (xv) provide the independent flash reading and writing data routing of better performance; (xvi) order state of each flash cell number (FUN) being reported; (xvii) read buffer control unit (BC) interface and one for one of the data routing support of each flash memory passage and write the buffer control unit interface; What (xviii) support to be used for context searchig reads the BC interface; What (xix) support to be used for updating context writes the BC interface; (xx) support is used for the read/write BC interface of idling-resource pointer (CFRP).
With reference to figure 2, Fig. 2 shows the more detailed block diagram of the piece 102 of Fig. 1, and this block diagram shows example flash medium controller (FMC) structure according to embodiment of the present invention.In one example, piece 102 can be realized three major function interfaces: buffer control unit (BC) interface, flush memory device interface and processor interface (for example, 32 AHB etc.).Left side and upper left side at block diagram show buffer control unit (BC) interface.In one example, can realize seven buffer control unit interfaces (for example, three fetch interface BC_RD_I/F, three write incoming interface BC_WR_I/F and a read/write interface BC_RD/WR_I/F).Show the flush memory device interface on the right side of block diagram.In one example, can realize two flash memory channel interfaces (for example, FLASH_I/F_0 and FLASH_I/F_1).Show 32 AHB interfaces in the upper right side of block diagram.In one example, 32 AHB interfaces can be used for to the register in the piece 102 programme, reading state and use diagnostic.
In one example, piece 150 can provide the interface of the addressable resource (for example, via the AMBAAHB-Lite interface) from piece 108 to 102.Piece 150 can provide direct interface to configuration and the status register of all addressable Resource Supply interfaces and the submodule that is not positioned at piece 156a to 156n in the piece 102.Piece 150 also can be to the addressable Resource Supply interface among each piece 156a to 156n.In addition, piece 150 can comprise a context and consist of impact damper (CCB), and wherein, the processor firmware can be with real medium context write-in block 102 to store the system buffer device into via piece 168.In one example, piece 150 can comprise following characteristics: 32 AMBAAHB-Lite slave interfaces to 108; Can for the input clock value (for example, HCLK) some divide value (or identical) system clock (for example, SYS_CLK); Access to all configuration registers in the piece 102 and status register and processor addressable space; Be used for making up the contextual context that is stored in the system buffer device by the processor firmware and consist of impact damper (CCB); Be distributed to each the processor interface among the piece 156a to 156n, wherein, the access of each addressing resource processed by processor access port (PAP), and it comprises the register that can be used by a plurality of submodules in the piece 102.Piece 150 can be carried out all register decoding and all reading out datas multiplexing (multiplex) to the addressable resource that logically is not stored among the piece 156a to 156n.
In the request step of FLC, data transmission can along with a rising among the piece 156a to 156n separately the request line and begin.In retrieval context operation, can retrieve corresponding context from a buffer control unit via context searchig port (CRP) interface 166.Data transmission can occur between DDIP, DTP and the FLC piece, and in this process, context can be sent to DDIP and can be write back or do not write back.Finish the stage at FLC, finishing line and can raise to represent end of transmission (EOT) to selected piece 156a to 156n.DDM152 can carry out the retrieval context and provide input to the DTP piece, to make things convenient for data trade.
Each route data flow of piece 158a to 158n, and start the current control of each interface for the data stream between each among the piece 154a to 154n, optional inner ECC encoder/decoder and the corresponding data DMA interface port (DDIP).In one example, can in piece 158a to 158n, realize inner ECC encoder/decoder.Alternatively, each among the piece 158a to 158n can be configured to share single ECC encoder/decoder module.Can programme to piece 158a to 158n for each transmission with corresponding data DMA interface port (DDIP) piece 172a to 172n and piece 174a to 174n by corresponding data dma manager (DDM) module 152.Each piece 158a to 158n can comprise the independent flash reading and writing path that can work under full duplex operating mode.Current region counting in piece 158a to the 158n maintenance data transmission and current double word (dword) counting in the regional.The current control that piece 158a to 158n carries out between DDIP, ECC scrambler and demoder and the FLC piece usually transforms.Piece 158a to 158n keep each transmission operation recoverable (running correctable) ECC mistake and, and after end of transmission (EOT), provide this end value to piece 152.Piece 158a to 158n can comprise for the FMC register to ECC scrambler and demoder programming.Piece 150 can visit register by register interface.The ECC module can be carried out 64 bit corrections on the 4K byte data usually.Yet, can correspondingly realize other grades and else proofread and correct to satisfy the design standards of specific implementation.In one example, demoder door counting can be the 415K door, and scrambler door counting can be the 75K door.
The sub-block that piece 164 is implemented as piece 102 usually can detect completed contextual single-point to provide by firmware after finishing.Piece 164 is carried out arbitration usually between a plurality of FLC source.FLC provides the PASS/FAILE CC that is associated with context pointer state.In case the acquisition context, piece 164 upgrades the context state field, then context is offered firmware.Need the long period to read internal storage in completed context and the piece 164 at firmware and will become in the full situation, piece 164 can be stored in the completed context of ranking after the context of current report with impact damper.
In one example, piece 102 can be realized with three clocks.Most of logic in the piece 102 can (for example, be worked on SYS_CLK) the clock zone being called as system clock.System clock can be the AHB clock.System clock has half frequency of the frequency of operation of FMC processor (FARM) 112 usually.Second clock can for so-called flash memory clock (for example, FBC_CLK).Flash memory bus controller (FBC) 154A to 154n can be fully operational in the flash memory clock zone.In one example, can in data stream manager (DM) module of piece 154a to 154n, realize first-in first-out buffer (FIFO), with the frequency between management clock FBC_CLK and the SYS_CLK.The 3rd clock can for the buffer control unit clock (for example, BC_CLK).All interface ports with BC all are operated in the buffer control unit clock zone.Can between buffer control unit clock BC_CLK and system clock SYS_CLK, realize that buffer element (for example, QBFIFO).
With reference to figure 3, it shows diagram according to the diagram of the piece 200 of the example flash channel controller structure of embodiment of the present invention.In one example, piece 200 can be used for realizing piece 154a to 154n and the piece 156a to 156n of Fig. 2.In one example, piece (or circuit) 200 can comprise piece (or circuit) 202, piece (or circuit) 204, piece (or circuit) 206, piece (or circuit) 208, piece (or circuit) 210, piece (or circuit) 212 and piece (or circuit) 214.Circuit 202 to 210 can represent to be implemented as the combination of hardware, firmware, software and hardware and firmware and/or software or module and/or the piece of other embodiments.In one example, piece 202 can be realized context processing telegon (CPC).In one example, piece 204 can be realized context manager (CM).In one example, piece 206 can be realized nude film administration module (DMM).In one example, piece 208 can be realized flash disk operation manager (FOM).In one example, piece 210 can be realized processor access port (PAP).In one example, piece 212 can be realized flash memory bus controller (FBC).In one example, piece 214 can be realized data stream manager (DFM).
In case extract context, piece 202 submitted in context.202 pairs of contexts of piece are carried out some and are explained that also forwarding contexts is to piece 204.The nude film (LUN) that if block 206 does not have available initiation context to carry out, piece 206 notice pieces 202 lack available nude film, and then piece 202 notice (communicate) pieces 204 lack available nude film.Piece 202 also assists piece 200 to finish contextual configuration.In addition, what start this flow process is piece 204, and what send configuration messages is piece 202 to the piece (for example, piece 164 among Fig. 2) that realize to consume context manager (CCM).When being received configuration messages by CCM and starting work, piece 202 notice pieces 204, then piece 204 can continue to process contextual execution.
Some explanations of piece 202 common Execution contexts.Particularly, in order to determine whether context is processor control model (PCM) context, and piece 202 can interpretive context.When receiving the PCM context, contextual extraction (appending) should stop.Then, piece 202 is waited for that piece 204 begins to carry out the PCM context and continue (resume) " standard " operation when the processor control model is finished.In processor control model interim, piece 202 is determined whether 15 double word contexts of the context that extracts, rather than 4 double word flash memory contexts, and piece 202 sends it to piece 204 under " standard " operation.
In one example, piece 204 can comprise context state machine (CSM), context extract management device (CFM), context allocation engine (CDE), context interpretation device (CI).Piece 204 is in charge of the context of effectively being processed by piece 200 usually.Piece 204 is carried out effective contextual bookkeeping (bookkeeping) usually.Context is to provide flash media controller (FMC) to carry out the data structure of all required information of flash memory transaction and DMA to the system buffer device.The context of piece 204 management on flash memory channel controller rank relates generally to the relevant context management of flash memory transaction thus.Piece 204 keeps being carried out the flash memory nude film fill order on the flash memory passage and the used information of data transmission by piece 208.
Flash command is applied to the atom " cycle " by the actual flash memory nude film of piece 208 controls with can being broken down into serializable.Because flash command (for example is usually directed to the very long stand-by period, before data effectively read from chip, page or leaf reads and may need 25 μ s), " command cycle " can be often for " one by one " (back-to-back) operation of different nude films of flash memory passage, thereby reduced effectively, stand-by period of accumulation.Piece 208 is managed the flash memory nude film by the state that upgrades nude film along with each flash memory circulation of application usually.Then piece 208 context table that reads renewal determines that next what circulation should (or can) carry out.The nand flash memory storage operation generally includes one or more flash memory cycles.Usually the flash memory cycle that has Four types: order, address, data outputs (the w.r.t flush memory device for example, reads), data inputs (the w.r.t flush memory device for example, writes).Period type roughly is converted into the action type of definition between piece 208 and piece 212.
The characteristics of piece 210 can comprise: simple access interface meets the AHB-Lite slave protocol and is cushioned by the processor interface logic (PIL) among the FMC; Read and write access to register resources, context table, context cache and nude film admin table is provided; Read and write access to the flash memory channel data buffer device memory resource that is arranged in piece 214 is provided.Piece 210 supports to add the ability of every passage configuration register usually, although most of configuration register is provided as the input of piece 200 usually.Similarly, can the status of support register and the interrupt register access, although most of status register and interrupt register produce beyond piece 200 usually.The main logical groups of piece 210 can comprise: interface manager (IF_MGR), data stream management interface (DM_IF), block of registers demoder (REG_DEC), block of registers multiplexer (REG_MUX), interrupt handler (INT_HND) and FLC global register (GLOB_REGS).
With reference to Fig. 4, show the diagram of submodule of the context management module 204 of diagram Fig. 3.In one example, piece 204 can comprise context table (CT) 220, context state machine (CSM) 222, context cache (CC) 224 and context queue controller (CQC) 226.Piece 204 divides and carries out the stage of the operation on the flash memory channel controller usually; keep all the effective contextual priority orders on the flash memory passage; keep the contextual state of each flash memory passage; (for example provide; pass through context cache) minimum flow stored on the contextual interim sheet that needs of complete exchange; each contextual buffer pointer in the processing that keeps carrying out, and think that by the context that uses context state machine (CSM) 222 definite NextStates each context provides the agency (agency).Can in context table (CT) 220, keep minimum contextual information.Table 220 provides the contextual priority query that is carrying out at present usually.Context queue controller (CQC) 226 can be configured to remove completed context and compressed context table 220 from context table 220, to eliminate the gap.
With reference to Fig. 5, show the diagram of submodule of the nude film administration module 206 of diagram Fig. 3.In one example, piece 206 can comprise nude film state machine 230, nude film service moderator 232 and nude film admin table 234.
With reference to Fig. 6, show the diagram of submodule of the flash disk operation manager (FOM) 208 of diagram Fig. 3.In one example, piece 208 can be divided into four submodules: order moderator (CA) 240, data transmission moderator (DTA) 242, flash disk operation formatter (FOF) 244, nanometer serial device 246.Then the usually order of scanning context table to obtain using of order moderator 240 communicate by letter to send a signal to flash memory buffer control unit (FBC) with flash disk operation formatter (FOF) 244.In case all " order " part is moved, flash memory is that " data phase " is ready, the transmission that data transmission moderator 242 is initiated between FBC and the data stream management (DM) 214.At last, nanometer serial device 246 is explained the command sequence that special " soft context " may need to use any flash memory, even command sequence itself is not supported.
With reference to Fig. 7, show the diagram of the data stream management submodule 214 of diagram Fig. 3.Data stream management 214 provides flash memory channel data buffer device memory resource usually.In one example, flash memory channel data buffer device memory resource can comprise straight-through impact damper 250 and 252.In one example, to may be implemented as its size be programmable to straight-through impact damper 250 and 252.For example, impact damper 250 and 252 size can be adjusted, to satisfy band merit.In one example, impact damper 250 and 252 can comprise static RAM (SRAM).Yet, can realize correspondingly that the storer of other types is to satisfy the design standards of particular implementation.Normally, each flash memory passage is realized two straight-through impact dampers.
With reference to Fig. 8, show the diagram that the example of the context manager (CM) 204 of Fig. 3 is implemented.Context manager (CM) 204 is in charge of the context that corresponding flash memory channel controller (FLC) is being processed effectively usually.CM 204 carries out effective contextual bookkeeping usually.As previously mentioned, context is to provide flash media controller (FMC) 102 to carry out the data structure of flash memory transaction and employed all information of DMA to the system buffer device.The context of CM 204 management FLC levels relates generally to the context management relevant with the flash memory transaction thus.CM 204 keeps flash disk operation manager (FOM) to the flash memory nude film fill order on the flash memory passage and the used information of data transmission.
Context queue controller (CQC) the 226th is carried out the logical block of revising to context table (CT) 220.In one example, CT220 may be implemented as block of registers, and it is organized into an entity for each queuing context.CQC 226 is the pieces to the table executable operations of organizing according to priority query.CQC 226 starts usually and Execution context is processed, and is responsible for processing carrying out on the context table.Main processing generally includes appends, waits for, revises, disposes and compress.Processing is initiated and is carried out by CQC 226.
The stage of appending is that FMC extracts new context and these contextual clauses and subclauses is added into stage of context table 220.The contextual content of flash memory and the contextual information that is provided by CPC202 are provided CQC226, and content-based and contextual information appends and create clauses and subclauses.In one example, the clauses and subclauses of context table can comprise the clauses and subclauses whether effectively value, value, expression flash disk operation value, value, the context pointer of expression flash memory nude film, the position (or sign) that indicates whether the disable data transmission and the value that represents flat address of expression context cache index of position (or sign), the contextual state of expression that represents context table.New clauses and subclauses begin with " effectively " position setting (for example, for " 1 ") and the value that is set to " context state " of " QUEUED " usually.If flash disk operation is illegal, original state can the value of being set to " ILLEGAL ", and this context entries can the processing stage deleted.Usually, the context and the information that provide by CQC226 are determined other fields.New clauses and subclauses all append to the end of the context table 220 of compression usually.Therefore, CQC226 knows the degree of depth of 220 context table usually.
When CQC226 wait for no longer that uncompleted data transmission is finished and CQC226 when given flash disk operation has attempted in the cycle to append operation at least one times, CQC226 withdraws from " appending " stage usually.When no longer including any useful space in context table 220 or the context cache 224, CQC226 can also leave " appending " stage.
The next stage that CQC initiates is generally " modification " stage.At modification stage, context table 220 is modified based on the flash disk operation of being carried out by flash disk operation manager (FOM) and by the result from the data routing transmission.Renewal is usually directed to contextual state and therefore usually initiates by context state machine (CSM) 222.When state more during kainogenesis, CSM222 sends update mode and context table is indexed to CQC226.Then, CQC226 upgrades the clauses and subclauses in the context table 220.When FOM finished its flash interface treatment cycle, modification stage finished.FOM can (for example, FOM_CM_FLASH_PROC_CMPLT) processing of notification context manager 204 flash interfaces be finished by sending a signal.In case modification stage is finished, CQC226 can carry out configuration, compress and append the context on the context table 220.During this period, 220 couples of FOM of context table are inaccessibles.CQC226 can represent that to FOM context table (for example reads clauses and subclauses and the effective signal of context cache reading out data by remove (de-assert) within the specific clock period, CM_FOM_CT_VALID) mode, making 220 couples of FOM of context table is inaccessibles.
After modification stage was finished, CPC202 initiated " configuration " action.Action of configuration is inserted the pattern that CQC226 searches the context table 220 of retrieving the clauses and subclauses of having finished execution with CQC226.CQC226 with clauses and subclauses whether finished execution determine be based upon on the context state.When being in " finishing " state at context, context can be disposed by CQC226.In one example, context can be in such state, and wherein CQC226 is waiting for the notice from the relevant context completion status of data routing.For example, in the situation of read operation, context can be in the DATA_TRANSFER_DONE state, and waits for the result of ECC verification.In this case, CQC226 can suspend configuration process temporarily and wait for the state that returns from data routing.During this period, CQC226 allows " appending " to occur.Yet in case waiting status is returned, context can be disposed by CQC226, and the context record that consumes can be transmitted to the also Zhongdao consumption context manager of CPC202((CCM) 164).
When CQC226 has disposed context, CQC226 removes " effectively " of context table 220 corresponding clauses and subclauses.This process is continued until that CQC226 has checked each context in the context table 220.When the effective contextual end in the CQC226 arrival context table 220, configuration phase is finished.
By " effectively " position in the context removing table clause separately of CQC226 configuration.Move this in neither one mechanism and show to fill up in the situation of room (hole), the effectively clauses and subclauses dispersion (or segmentation) that can in context table 220, become.The context that disperses will be so that context table be difficult to scanning and " appending " stage is more complicated.Keep the feature of its priority query in order to ensure context table 220, context table 220 can be compressed.In compression process, when CQC 226 has disposed context, move a position on CQC 226 all clauses and subclauses after immediately will d/d clauses and subclauses.After this was finished dealing with, all effective clauses and subclauses all were removed in the front of priority orders tabulation and all rooms.The same with the situation of other actions, when compression process was finished, CQC 226 safeguarded " finishing " signal (or position).After in the end compression stage finished, CQC 226 can begin the stage of appending.
Usually, when the context that is set to PROCESSOR_CONTROL_MODE when " flash disk operation " field of processor control model (PCM) appears at the top of context formation, processor control model (PCM) beginning.Usually, in context table 220, should there be effective clauses and subclauses in PCM context back, in case because 226 pairs of PCM context queuings of CQC, CQC226 should suspend the retrieval of standard context.When PCM began, CQC 226 can be via signal (for example CM_CPC PROC_CNTL_MODE) notice CPC 202.In response to this notice, CPC 202 can obtain " the soft context " that the position in the PCM context occurs.From offering the angle of FOM, FOM does not know to have the PCM context usually in context table 220, and the PCM context is the back of other the effective clauses and subclauses in context table 220.PCM context entries in the context table 220 offers FOM with its " effectively " position as 0, until CM 204 begins to carry out soft contextual preparation for FOM carries out.
When FOM began to read soft context, because operation offers FOM 208 by the soft contextual context cache 224 of storage, CQC 226 monitored (snoop) operation.When operation relates to DMA context (prefetch data for example, read data buffer is set, or configuration context pointer) time, CQC226 specifies present untapped storage in (co-opt) context table in context table 220, and in context table put pointer to be used for tracking.When these DMA contexts were finished, FOM208 notification context manager 204 disposed context with standard mode after it.
CQC226 also seeks " obtaining next soft context " operation when monitoring.When CQC226 found one, CQC226 was retained to the signal (for example CM_CQCPCM_NEXT_CONTEXT) of obtaining next soft contextual CPC202.When the soft context execution of FOM208 notice CM204 had been finished, FOM208 notified CM204 at " FOM/CM " command interface.Then, CQC226 removes the signal (for example CM_CPC PROC_CNTL_MODE) of CPC, and then, standard operation continues.In one example, CM_CPC PROC_CNTL_MODE can be retained as the rank that expression CM204 has entered the processor control model and has been ready to now receive soft contextual signal.
Another critical function of CQC226 is the overtime situation of monitoring.In one example, CQC226 can comprise counter, and it is configured to the quantity in system clock (SYS_CLK) cycle is counted, so that the clauses and subclauses of same context table are positioned at the top (that is, in clauses and subclauses 0) of context table 220.If count value reaches the value of " overtime " able to programme counter, the clauses and subclauses on context table 220 tops can be considered to overtime.When clauses and subclauses were considered to overtime, clauses and subclauses can remove from context table 220, and the context pointer turns back to the context that consumes on the context interface and processes telegon (CPC) 202.
Contextual return state is one of two possible " overtime " states.In the first situation, overtime meeting may be due to such situation, and wherein, another nude film on the flash memory passage is had much to do and reduced the R/B line.In this case, state representation is overtime may be to result from the overtime of another nude film.In the second situation, contextual nude film is regarded as culprit (culprit).Can return the expression nude film here, is the different conditions of culprit.
Context table 220 is essentially the storage medium of clauses and subclauses.The degree of depth of context table is parameterized.For example, can support 16 nude films of every passage) the situation of chip under, can realize 16 clauses and subclauses.If each nude film (die) can be managed more than one operation, it can be favourable increasing the degree of depth.Context table 220 has minimum function (minimal function).CQC226 realizes the more deep processing of major part to context table 220.Yet, can implement context table 220 by the multiplexing logic of multiple fetch interface and each fetch interface.In one example, for the read access ability, can implement context table 220 by the interface of FOM208 and to the interface of context state machine (CSM) 222.Context table 220 also can have the fetch interface to CQC226.Context table 220 also can be accessed by processor.
Context table 220 also has " mobile (the shift) " ability for the compression stage of table.In addition, CQC226 can upgrade context table 220 with simply writing incoming interface.In one example, context table 220 can be implemented in trigger (flip-flop).When context table 220 is implemented, do not need the required arbitration of read access in trigger.Surpass about 1000 triggers if the scale of context table 220 is increased to, context table 220 can realize in register file or SRAM, but also should realize extra management and access arbitration.
Clauses and subclauses at context table 220 top ends are represented as in the processor control model of PROCESSOR_CONTROL_MODE operation, and context cache 224 should be fully idle.In the processor control model, context cache 224 should be expected and received soft context from CPC202.Context cache 224 can expect that also soft context comprises 15 double words.In fact, context cache 224 receives any data that provided by CPC202 as subordinate.CPC202 is responsible for an amount of data are write context cache 224.224 couples of FOM208 of context cache are addressable, and it uses whole flash memory contextual informations when flash cell is realized actual order.FOM208 provides the address to 32 double words, and context cache 224 is in the double word of subsequent clock periodic response request.During the processor control model, from context queue controller (CQC) 226 monitoring that response can be realized based on the content of operation action of reading of context cache 224.As context table 220, context cache 224 also can be accessed by processor interface.
Usually, context state machine (CSM) 222 is configured to, based on the current state of clauses and subclauses and or the operation carried out by FOM208 or data routing mode of operation and determine each contextual executing state in the context table 220.In modification stage, whenever FOM208 utility command or return results, CSM222 is called by CQC226.The content of FOM order notification interface and FOM context table fetch interface generally provides CSM222 to determine required all information of NextState.
In the disposal stage, when CQC226 scanning context table 220 and run into when being in the context table clauses and subclauses for the context table clauses and subclauses of the state of waiting for action (action), CQC226 for example calls CSM222(, TRANSFER_DATA state or PREFETCH_DATA state).When running into TRANSFER_DATA state or PREFETCH_DATA state, CQC226 is according to the information of transmission status wait from data routing (for example, DM, DDM or DTP).Which kind of mode no matter is usually called CSM222 and is determined NextState with the context table clauses and subclauses to (the in question) that paid close attention to.When the context table clauses and subclauses move to completion status (for example, COMPLETED or COMPLETED WITH ERROR(finishes or tape error is finished)), 222 of CSM also is responsible for notice nude film administration module 206.
With reference to Fig. 9, Fig. 9 shows the structural drawing that the example of flash disk operation manager (FOM) piece 208 of Fig. 6 is implemented.In one example, piece 208 can be implemented 5 submodules.For example, piece 208 can comprise piece (or circuit) 240, piece (or circuit) 242, piece (or circuit) 244, piece (or circuit) 246, piece (or circuit) 248.Circuit 240 can be expressed as to circuit 248 and be embodied as hardware, firmware, software, hardware, the combination of firmware and/or software, or the module of other enforcement and/or piece.In one example, piece 240 may be embodied as order moderator (CA).In one example, piece 242 may be embodied as data transmission moderator (DTA).In one example, piece 244 may be embodied as flash disk operation formatter (FOF).In one example, piece 246 may be embodied as nanometer serial device (nano-sequencer).In one example, piece 248 may be embodied as state of a control machine (FOMCSM).
The data transmission moderator 242 general flash disk operation managers 208 that connect are to data stream manager 214.Flash disk operation formatter 244 is coupled to flash memory bus controller 212 with flash disk operation manager 208 usually.State of a control machine 248 is coupled to context manager 204 with flash disk operation manager 208 usually.Order moderator 240 is connected between flash disk operation formatter (FOM) 244 and the state of a control machine 248 usually.Data transmission moderator 242 is coupled between flash disk operation formatter 244 and the state of a control machine 248 usually.Nanometer serial device 246 generally is coupled between flash disk operation formatter 244 and the state of a control machine 248.Then the order of context table to obtain using in the order moderator 240 general scanning context managers communicate by letter to send a signal to flash memory bus controller (FBC) 212 with flash disk operation formatter (FOF) 244.
With reference to Figure 10, show diagram according to the diagram of the example flash medium context layout 300 of embodiment of the present invention.Each flash memory transaction is represented by context usually.Context is to comprise that system hardware carries out with the transaction of flash memory bank (flash bank) and/or with position or the therefrom data structure of mobile this data employed all information of Mobile data in the system buffer device.Context is made up by firmware usually, and is used as the actual inner pointer of residing buffer control unit (BC) of context and offers flash memory channel controller (FLC).Firmware can be selected to make up these contextual lists of links (for example context list) thereby allow the hardware robotization of larger flash disk operation.Each flash cell that is managed (such as nude film, LUN etc.) has a context list usually.
Usually, during normal operations, all only some is used for carrying out the flash memory transaction by FLC to context.Therefore, only have by the employed part of FLC and be stored in the context cache of FLC.All contextual parts that all are stored in during normal running in the context cache of FLC are commonly called " flash memory context ".As what can see from flash media context layout 300, in one example, the flash memory context can only comprise contextual front four double words of whole 15 double words.
In one example, the context of realizing according to embodiment of the present invention can comprise following content and/or field: the flash disk operation field, the flash memory lines address field, piece is described pointer/return and to copy (copyback) row address field, consist of bit field, next context pointer field, DMA skips (skip) mask field, the data buffer pointer field, (alternate) for subsequent use data buffer pointer field, LBA (Logical Block Addressing) (LBA) field, mode field, flash cell number (FUN) field, can comprise metadata or composition data pointer, metadata, and/or the field of flash memory composition data, the field that can comprise metadata or flash memory composition data, if use 64 LBA pattern field then can comprise metadata or the field on the top of LBA (Logical Block Addressing) (LBA), the field that can comprise contextual error recovery coding techniques (ECC).The flash disk operation field can comprise operational code.In one example, operational code can comprise eight positions.Operational code can be produced by firmware, with the operation that will carry out to the hardware transmission.Usually, operation relates at least one times access to the flash memory ranks.Firmware can with the basic operation code can comprise the value that represents following operation, comprise for example RESET, SYNCHRONOUS_RESET, READ_ID, READ_PARAMETER_PAGE, GET_FEATURES, SET_FEATURES, READ_PAGE, PROGRAM_PAGE, ERASE_BLOCK, COPYBACK_READ/PROGRAM, READ_STATUS, READ_STATUS_ENHANCED, PROCESSOR_CONTROL_MODE, MUILTPLANE PROGRAM PAGE and MUILT PLANE PROGRAM PAGE END.
The flash memory lines address field can comprise the row address of the page or leaf of the access in the flash memories.In one example, the flash memory lines address field can comprise the block address that is connected in series with the page address.The flash memory lines address can offer flash array during three (3) individual row address operating cycles.For clear operation, only provide the block address of the access in the flash memories.For the READ_ID operation of only using a byte address, in one example, byte can be placed into the leftmost byte (MSB) of flash memory lines address.When flash disk operation was PROCESSOR_CONTROL_MODE, the flash memory lines address field also can be used as soft context pointer.When running into the operation of processor control model, FLC can use the value of flash memory lines address field as soft contextual system buffer device address.
In when position that data is moved to the system buffer device, DMA skips mask field and can allow to transmit or skip pages sector (subregion) based on the state of position (for example ' 1 ' or ' 0 ').In one example, DMA skips mask field and may be implemented as low effectively (active low) and skip mask or transmit mask (for example ' 1 ' expression send and corresponding page or leaf is skipped in ' 0 ' expression).DMA skips mask field and can be mainly used in reading/revising/write (RMW) operation, and this transaction for a small amount of sector is common.For example, on the page or leaf device of 8K, page or leaf is divided into ten six (16) individual sectors usually.The certain bits of skipping mask field at DMA is 1 o'clock, and in one example, corresponding sector can be written into the system buffer device or therefrom read.Be 0 o'clock in this position, corresponding sector can be from be written into the system buffer device or omission from the system buffer device is read.In one example, also can there be the pattern that allows data to write from the source of two separation: comprise the buffer block of unmodified page data, and the page data buffer block that comprises modification.For these situations, state (for example ' 0 ') can be used for the expression sector and write from the piece of the page data that comprises renewal, and other states (for example ' 1 ') are used for the expression sector and write from the piece that comprises unmodified page data.Bit position also can be meaningful (significant).For example, highest significant position (MSB) usually corresponding to the first page in the sector or minimum number the page or leaf the position.Least significant bit (LSB) (LSB) is normally corresponding to the position of the page or leaf of the maximum quantity of sector.If there is the subregion less than 16 in page or leaf, least significant bit (LSB) can be considered to be insignificant.Yet, can realize that the clauses and subclauses of other quantity are to reach the design standards of particular implementation.In one example, when realizing black nurse (bose_chaudhuri_hocquenghem) error-correcting code (ECC) of Bo Siqiaohelihuokewen, the mask granularity can be one (1) individual information word.
Next context pointer field can point to next the contextual pointer that comprises in the context list (for example contextual lists of links) that is made up by firmware.If " next context pointer " equals by " the tabulation end pointer " of firmware programs in the FLC, hardware can suppose that retrieval has arrived the end.Hardware is in the change that continues can wait for before the traversal lists of links " tabulation end pointer " value.Also can define " null pointer " value, it will stop the table search of hardware.
In one example, piece is described pointer (chunk descriptor pointer)/return and to copy row address field, usually copies the data cached row address that the flash memories page or leaf is provided that order will be written back into for returning.Row address is the serial connection of block address and page address.In other example, return and to copy the flash memory lines address field with to copy contextual untapped field for non-time shared.For example, block descriptor pointer/return and to copy the subsidiary field that row address field can be used to provide buffer allocation manager (BAM).The BAM subsidiary field can comprise the pointer by the descriptor of the data block in the data buffer of buffer allocation manager (BAM) management.
The block descriptor field can be used for cache management.Block descriptor can comprise that block address used in the buffer management (for example in the system buffer device), significance bit, dirty (dirty) position, transmission suspend counting, state, LBA and pointer.After DMA finished, the block descriptor pointer was sent to BAM by the dma manager in the flash media controller (FMC) usually.The block descriptor pointer also can be sent to BAM, if so that zone bit (for example BAM searches needed position) is set up then obtains the buffer data pointer with beginning DMA.Block descriptor pointer/BAM subsidiary field also can be set to general BAM subsidiary field by firmware, and content can be determined according to concrete programming of BAM serial device by firmware.Usually, block descriptor pointer/BAM subsidiary field is fully apparent to hardware.
The data buffer pointer field provides sensing to be sent to flash media or to be sent to the pointer of the real data of buffer control unit from flash media from buffer control unit usually.When originally context was obtained, the data buffer pointer field was present in the context, searched needed position if BAM perhaps is set, and the data buffer pointer field can be searched by BAM by BAM and insert (populate).The data buffer pointer field provides the address of first byte in the piece usually, is decided to be first effective LBA and differ.
Preliminary data buffer pointer field also is to be sent to flash media or to be sent to the pointer of the data of buffer control unit from flash media from buffer control unit.When the multi-source of impact damper or multiple destinations are used/go out in operation, use preliminary data buffer pointer field.Preliminary data buffer pointer mainly can be used for reading/revising/write (RMW) to operate.When main frame (host) was carried out operation less than whole page or leaf, main frame carried out the RMW operation with refresh page.Preliminary data buffer pointer can be used for read operation, in order to old page data is stored in the interim piece.Then, when implementing write operation, skip the source that writes that mask can be used for selecting from the medium block that comprises unmodified page data or the main frame piece that comprises the data that will be updated sector (or subregion).
Metadata fields generally includes the metadata relevant with Hash memory pages (for example, such as LBA, serial number, bad piece designator etc.).Usually can expect that all metadata can be contained in the context.Otherwise metadata buffer pointer can be included in the context to replace metadata, retrieves thereby metadata can be stored in the system buffer device or from the system buffer device.For writing, metadata fields is usually inserted by firmware and is inserted in the page or leaf by hardware.For reading, for firmware, the content of the metadata in the page or leaf is read in the expectation request usually.For these situations, context can be configured to read metadata in context from page or leaf.In one example, can determine size with the metadata of byte representation by the metadata size register.
The flash configuration data field usually with the shared byte location of metadata fields, and be generally used for transmitting the operation (such as READ_ID, GET_FEATURES, SET_FEATURES, READ_STATUS etc.) of limited quantity byte.(for example SET_FEATURES and GET_FEATURES can use 4 bytes because the byte number relevant with such transmission is usually less; READ_ID uses 5 bytes usually; READ_STATUS can only use 1 byte), data are only independently transmitted in the buffer positions in context rather than at one.If the data relevant with such transmission exceed the space of distributing in context, can use flash configuration data pointer field.4 bytes are used in " GET_FEATURES and SET_FEATURES " order often supposition.In one example, from the quantity that reads byte of READ_ID command register, can obtain the quantity of the required byte of READ_ID order.When the flash configuration data field was used for configuration data, 7 all double words were all by hardware update, and firmware only needs to read suitable byte.
The metadata buffer pointer field comprises the address of the position of page metadata (for example being included in the management data in the user data of Hash memory pages).Because all metadata can be stored in the context self and expect in many application, the metadata buffer pointer field can omit.In the time will from the system buffer device of outside, retrieving metadata, can use the metadata buffer pointer field.Usually only have metadata to be stored in the outside and not in context, just use the metadata buffer pointer field.In one example, can realize configuration bit, to specify metadata to be stored in the outside or to be stored within the context.In one example, the external system impact damper may be implemented as the storer (for example DDR RAM) of the outside of the chip that comprises flash media controller (FMC).In another example, outside system buffer device may be implemented as RAM on the sheet of outside of FMC IP.In another example, outside system buffer device can comprise the storer in the FMC IP.Usually, outside system buffer device can be any storage of contextual outside.
Flash configuration data pointer field provides maybe needing of obtaining to be written into the location address of the composition data of a flash cell usually.Because metadata is assigned to context field to be used for data trade, so the flash configuration data relevant with the SET_FEATURES order with READ_ID, GET_FEATURES can be stored in the context.Yet just as the situation of metadata, if size of data surpasses the space of distributing for the flash configuration data in the context, the pointer of the data of system buffer device can be used to access.
LBA (Logical Block Addressing) (LBA) field provides the LBA of first data partition in the page or leaf usually.For each sector of system buffer device and flash memory, LBA is encoded into data protection usually.Because page or leaf is continuous LBA group, only have first LBA in this group to be used as a contextual part.LBA can be used to the impact damper CRC of sector page to do kind of (seed).For the LBA part of metadata, LBA also can carry out verification selectively.For example, can realize that whether configuration bit select partly to come verification LBA with respect to the LBA of metadata.For example, when configuration bit was set up, LBA can partly carry out verification to the LBA of metadata.In one example, only have low 32 can be used for doing kind.
Flash cell number (FUN) field can determine with acting on which flash cell is with the identifier of application context by firmware.Should determine for hardware it is clearly.The flash cell field is used for administrative purposes individually by firmware, so that after context was by hardware consumption, in case identifier is provided back firmware, firmware can be coordinated context.
Consisting of bit field generally includes for consisting of context and determining all positions of the processing of context (and context represent transmission) with the various points of hardware flow.In one example, available context position and the field in the context configuration bit field can include but not limited to following: consume the context manager interrupt enable; Part command enable position, the part command functions on the use flash interface is enabled/is forbidden execution DMA and skips mask; Forbidding is to the DMA of system buffer device; Forbid any from or to the data transmission of FLC local buffer; The scrambler function is enabled, and enables/forbid the scrambler function; The interrupt enable of ECC error-detecting; The decoding of reading out data or additional parity are enabled/forbidden to the grand bypass of ECC to data writing; Impact damper CRC enables; Ignore metadata signal (position), make metadata when reading, not be forwarded to system data impact damper, system buffer device or context, and writing fashionable preventing from any source inserting metadata (for example, the leaf metadata fields is blank); Signal (position), the user data that is used in DMA keep metadata (for example, transmit metadata to data buffer when reading, and fashionablely receive metadata from data buffer writing); Signal (position), indicating whether will be with the beginning LBA field phase verification in " beginning LBA " field in the metadata and the context; Signal (position) indicates whether in impact damper to keep ECC parity fields (for example, when reading the ECC parity byte is transferred to the system buffer device, and fashionable ECC is transferred to flash memory from the system buffer device writing); Signal (position) indicates whether to use plane buffer (for example, non-managed memory zone is entered/gone out to data transmission) rather than hosted data impact damper (for example, can be used for determining how many data of transmission are to the system buffer device in the quantum burst); Signal (position) indicates whether that user's data sector length is configured to determine the data length (for example, if this is eliminated, the data length of sector can be determined according to the configuration of reserve area sector length) of sector; Signal (position) indicates whether to transmit flash configuration data (for example, flash data is read in the context, or write from contextual flash data); Signal (position) indicates whether whole (full) the original flash memory pages of transmission to the system buffer device or therefrom transmits all (full) original flash memory pages; Signal (position) indicates whether to use standby buffer (for example to skip mask, make the jump mask be used for sign (mark) will be transmitted into/go out by the sector of the pointer of preliminary data impact damper buffer block pointed (subregion), rather than omit the transmission of sector; When enabling disarrangement device for the field of each partition definition disarrangement device seed.Indicate whether to transmit whole original flash memory pages to or from the signal of system buffer device, it is mutual exclusions with other options of great majority in fact.Indicate whether to transmit a complete original flash memory pages to or usually surmount the setting in other in (overide) from the signal of system buffer device.Usually complete original Hash memory pages of transmission to or make firmware grasp (get at) from the feature of system buffer device not belong to the not use of page or leaf of any subregion regional.Transmission flash configuration data-signal can be used for the order such as ops, READID, GETFEATURES, and SETFEATURE.The size of data can be determined by the configuration data length register.Data will appear at the position that is usually occupied by context in the metadata.
Mode field generally includes the position that can be used for to the firmware return state.In one example, can comprise used the passing through of program/erase operations (pass)/failure (fail) state in mode field.In another example, mode field can also comprise the number of errors that the ECC logic detection arrives in the read operation.Yet, can realize other purposes of this field, to satisfy the design standards of specific implementation.In one example, mode field can be configured to expression in the flash memory pages number of errors and be used for contextual manager completion code (such as, remove that (clean), program/erase mistake, the read error of correction, the read error that can't proofread and correct, impact damper crc error, operation overtime, LBA/ metadata on look ahead (prefetch) of system buffer device are not mated, illegal operation etc.).
As mentioned above, context is the data structure of having determined command execution.Context is the communication unit between firmware and the hardware.Referring to figs. 2 and 3, general context stream can be summarized as follows.Firmware writes context in the context mechanism impact damper (CCB) of processor interface logic (PIL) of FMC102 with 150 internal memory pointers.A plurality of contexts can be linked by the firmware in the context by using next pointer field in the context mechanism.The contextual storer that hardware is carried out the position that the internal memory pointer is associated by updating context port (CUP) 168 writes.For example, the firmware execution that can enable specific nude film by the nude film supervisor register in the nude film administration module (DMM) 206 among flash memory channel controller (FLC) 156a to 156n separately.Can independently manage the nude film register for each nude film provides a cover.DMM206 sends (communicate) context manager (CM) 204 to flash memory channel controller (FLC) 156a to 156n separately with the information in the register.CM204 can extract from internal memory by context searchig port (CRP) 166 and enable context, and scheduling is to the execution of the order on the flash memory channel bus separately.The common traffic order of CM204 and indication are used for data dma manager (DDM) piece 152 of data-oriented operation.DDM piece 152 extracts context usually to extract from the context data parameters by CRP166 from storer.After the context that is undertaken by DDM152 and CM204 was successfully finished, state was updated to and consumes context manager (CCM) 164.After finishing, can produce be interrupted and firmware can read out completion status under the given context by hardware.
The data DMA interface port (DDIP) that comprises piece 172a to 172n and piece 174A to 174n is responsible for the real time data route between DTP 158a to 158n, system buffer controller and the related context usually.Each data transmission can comprise one or more subregions.Each subregion can comprise one or more zones.Actual format from FMC(for example uses register) and determine from the configuration setting of related context.Setting can be transmitted by each, each subregion and each region base are classified.Route can be determined according to area type and other configurations of data transmission format.Route generally includes and merges and burst (padding and stripping) function.All contextual double words that each data transmission relates to.Therefore, DDM 152 initiates contexts to the access of DDIP, and wherein DDIP read into its own context cache all context double words regional before real data moves.
In case retrieve related context, DDIP is with suitable configuration setting its inner control logic of programming, and provide some configuration informations to corresponding DTP 158a to DTP 158n.Then DDIP follows the tracks of the regional in each subregion, and sets up the logic that is used for suitable route.In actual data transfer, if data are redirected to context, then DDIP can switch contexts access to write mode.After being transmitted, DDIP can notify DDM 152 transmission and contextual access to finish.DDIP can the execution error verification.For example, DDIP can be configured to LBA that executive system impact damper CRC check and/or affirmation receive and meets LBA from contextual expection.The result of these verifications and system buffer device ECC byte error (when enabling) passes DDM piece 152 usually back.DDM piece 152 can transfer information is reached selected FLC 156a to 156n.DDIP also can be configured to generate and insert CRC.Can make up whole user data by collecting all customer data byte from each subregion.Equally, can be by making up whole metadata from each subregion collected metadata byte.In one example, can collected metadata until reach the predetermined upper limit.In one example, DDIP can have default configuration, wherein DDIP only route advance/go out the system buffer device with the part of user data area, and only context unit is entered/gone out to route with the data area part.The ECC zone can burst/merging.Can revise default configuration so that multiple variation to be provided.For example, DDIP can be configured to: (1) keeps whole user data area intact, comprise untapped byte, (2) make into/the metadata area that goes out system buffer device territory and keep user data, (3) burst/merging metadata area, (4) keep ECC intact, and/or (5) keep whole subregion intact (for example, not having burst/merging).
Context layout structure 300(is described in conjunction with Figure 10 in the above) can be used in any target the page or leaf programming.Example programming data stream between the module of top can be summarized as follows.Firmware programs with the associative storage pointer among the CCB, in processor logic interface (PIL) 150, with the order context is programmed.CCB carries out the write operation of storer by CUP_168.Firmware can be enabled DMM206 among the FLC156a to 156n separately to allow contextual execution.CM204 among the FLC156a to 156n separately extracts context by CRP166 from internal memory, and processes the context part that is used for the order on scheduling flash memory bus controller (FBC) 154a to 154n separately.DDM and FLC152 communicate for context, and DDM152 extracts context by CRP166, and data block pointer DTP piece 158a to 158n extremely separately is provided.DTP piece 158a to 158n separately passes through the pointer of from the context decoding from the memory request data.This request is to be undertaken by the DMA interface FPDP (DDIP) that piece 172a to 172n and piece 174a to 174n form.Data DMA interface port (DDIP) in quantum burst from memory read data.
The data communication device that reads from internal memory often is delivered to DTP by the DDIP that is formed by piece 172a to 172n and piece 174a to 174n.In DTP, if enable, data can be carried out CRC check, and if enable, ECC can add user data to and be delivered to FLC156a to 156n separately.If the failure of the integrality of data, state is updated to CCM piece 164.Order and data flash memory bus controller (FBC) 154a to 154n extremely separately that flash disk operation manager (FOM) 208 scheduling programming cycle among the FLC156a to 156n separately are relevant.FBC154a to 154n separately carries out programming operation with the flash interface standard to the flash memory bus interface.FBC154a to 154n separately reads the state that flash disk operation is finished.When operation was finished, FBC154a to 154n communicated by letter with FLC156A to 156N separately separately, and FLC156a to 156n separately communicates by letter with CCM164.CCM164 keeps interrupting finishing with the context that notice is located in the relevant context register of CCM164 to firmware, and is ready to the inspection of firmware.Then, firmware reads context from CCM164.Finish contextually when reading and processing when firmware, firmware can keep allowing to load the contextual signal (for example, position) of another consumption.
Basic flash memory reading data flow can be described below.A context mechanism is used for reading any page object.Firmware program is programmed to context with order in processor logic interface (PIL) 150 with the associative storage pointer among the CCB.CCB carries out the write operation of storer by CUP_168.CCB carries out writing memory access by CUP168. and firmware is enabled DMM206 among the FLC156a to 156n separately to allow Execution context.CM204 among the FLC156a to 156n separately from the memory fetch context, and processes the required context part of order that scheduling is used to FBC154a to 154n separately by CRP166.FLC156a to FLC156n separately and FLC154a to 154n separately communicate to carry out the reading order to target.FLC156a to 156n separately and DDM152 communicate for context, and DDM152 extracts context by CRP166, and the pointer DTP piece 158a to 158n extremely separately of data block is provided.
When the data that receive from the FBC154a to 154n of flash memory by separately to DTP158a to 158n separately, DTP158a to 158n separately is by wanting the data of write store from the pointer request of contextual decoding.DTP158a to 158n separately is also by by piece 172a to 172n and piece 174a to 174n(DDIP) the DMA interface FPDP that forms does like this.DDIP writes data into storer in the quantum burst.In DTP, if enable, data are carried out the ECC verification, and if enable, CRC adds user data to and this data pass to DDIP.If the failure of the integrality of data, state is updated to CCM piece 164.After operation was finished, the state of read operation was provided to CCM piece 164.CCM piece 164 keep interrupting to firmware with the notice firmware, the context that is positioned in the context register of CCM piece 164 is complete, and it is ready to think that firmware checks.Firmware reads the context from CCM piece 164.Finish when firmware and contextually to read and to process, firmware can keep allowing to load another and consume contextual signal (for example, position).
With reference to Figure 11, there is shown according to the example partition sections in the Hash memory pages of embodiment of the present invention.The nand flash memory storer is organized into the page or leaf that comprises user data usually.At present, modal page or leaf size is 8KB.Except the 8KB of user data, the nand flash memory storer has the spare area, wherein can comprise for multi-purpose extra byte.At first, the spare area can comprise flash memory management information (for example, LBA, sequence number, bad piece index etc.), and this is commonly called page metadata.Next, the spare area can comprise the information of verification and/or end-to-end (end to end) data integrity inspection (EDC) of error-correcting code (ECC).The ECC verification can be used for the data protection of user data and metadata (for example, detection and error recovery).In one example, except the user data of 8KB, the spare area of the 512 extra bytes that can share between metadata, ECC, the EDC can also be arranged.
Physical Page can comprise a plurality of subregions.Flash media controller according to embodiment of the present invention can use conventional page subregion (regioning), is configurable (for example, by register etc.) but allow subregion.In one example, can use zoning's 400 each subregion of configuration.Can use zoning's 410 each subregion of configuration.
When using zoning 400, each subregion can comprise follows user data fields 402 after meta-data region 404 after the ECC 406 and meta-data region 404.ECC 406 is protection user data 402 and metadata 404 usually.Generally, the size of the size of subregion 400 and user data 402 and metadata 404 is configurable.In addition, the size in ECC district 406 exists with ... the size of user data 402 and metadata 404.The flash media controller of the enforcement of mode is supported the contiguous page subregion (abutted page regioning) as conventional page or leaf format structure usually according to the present invention.The contiguous page subregion refers to a plurality of subregion adjacency.Yet this subregion is not limited to 2 power; Subregion can be arbitrary size.By following the subregion of any size, can support larger sector, DIF, CRC and/or other metadata according to the flash media controller that embodiment of the present invention is implemented.Usually, all sizes are programmable.
When using zoning 410, each subregion can comprise the first field 412 and the second field 414.It can be original, scrambling (if enabling) and/or the host sector data of encrypting (if enabling) that the first field 412 comprises usually.In one example, the size of user data can the 512/1K/2K/4K byte add n double word, and wherein the scope of n for example from 0 to 32.An example, current LBA can be used for doing kind of (seed) for scrambling and crypto engine.The second field 414 can comprise the flash memory management information (for example, LBA, sequence number, bad piece index etc.) that is commonly called page metadata.Use zoning 410, have two kinds of metadata can be placed on mode in the Physical Page: (1) metadata is striden subregion and is distributed, and (2) whole metadata only is placed on last subregion.When metadata was striden the subregion distribution, metadata generally was regarded as the part of this subregion.The size of the size of subregion and user data and metadata generally is configurable.In one example, the size of user data and metadata can be programmable (for example, passing through register).Usually, firmware is responsible for guaranteeing that size programmes in the restriction of the size of Physical Page.
With reference to figure 12A and Figure 12 B, Figure 12 A and Figure 12 B show the diagram of example flash page structure.According to the traditional page or leaf subregion of the general employing of flash media controller that embodiment of the present invention is implemented, be configurable (for example, passing through register) but allow the page or leaf subregion.In one example, can use zoning 400 to implement Hash memory pages structure 500.In another example, can use zoning 410 to implement a plurality of flash memory structure pages or leaves 510,515,520,525,530,535.
In one example, in the meta-data region of the subregion in page structure 500, metadata can be by represent left-to-rightly.For example, the page or leaf by having the 8K byte-sized and the flush memory device of the spare area of 512 bytes, the host sector of 512 byte-sized can adapt to 16 subregions, and wherein each subregion maximum has 544 bytes.In one example, each subregion can comprise the user data of 512 bytes, the metadata of four (4) bytes and the ECC that reaches 28 bytes.If metadata adds up to 28 bytes, 4 meta-data region that byte will enter each subregion of front 7 subregions of metadata, all the other 9 meta-data region (for example, in subregion 7 to 15 subregions) will fill 0 or or give over to other purposes.When the DMA interface port data is processed page or leaf, data DMA interface port keeps the tracking of the processing in the page or leaf processing, thereby data DMA interface port is known and is begun wherein to insert and collected metadata, and know residing position, code word (codeword) border, it also is the residing position of partition boundaries.Although the size of this subregion is programmable, the code word of the maximum that the size of subregion should can not be worked greater than the ECC encoding and decoding.For example, BCHECC reaches 48 bit corrections to the support of 1K+80 information word.For each correction bit, add 16 bit checks.
Use zoning 410, can implement various flash memory structure pages or leaves 510,515,520,525,530,535.In one example, Hash memory pages can be divided into 8 subregions, and wherein each subregion uses zoning 410 to consist of.Untapped spare area in the Hash memory pages can utilize in two ways.In the first example, metadata can be striden subregion and be distributed, as the part (shown in the structure 510,520,530) of subregion.In the second example, whole metadata can only be placed on last subregion (shown in the structure 515,525,535) of page or leaf.In the first example (shown in the structure 510 and 515), the information word of LDPC equals the host sector size.In this example, each subregion all adds separative EDC and ECC check field.EDC does kind with the BA of the host sector in the subregion.In the second example (shown in the structure 520 and 525), the information word of LDPC is greater than the host sector size.In this example, the additional separative EDC of per two subregions and ECC verification.EDC does kind with the LBA of the last host sector in the subregion.In the 3rd example (shown in the structure 530 and 535), the information word of LDPC is less than the size of host sector.In this example, be attached with two ECC verifications and an EDC in the subregion.EDC plants with the LBA of the host sector in the subregion.Because the page or leaf subregion disposes, and can correspondingly implement other page structures to satisfy the design standards of particular implementation.
With reference to Figure 13, Figure 13 shows the process flow diagram according to the processing 600 of embodiment of the present invention.(or the method) 600 of processing provides the step that is used for according to the embodiment of the present invention process metadata generally.In one example, process 600 and can comprise step (or state) 602, step (or state) 604, step (or state) 606, step (or state) 608 and step (or state) 610.In step 602, process 600 can define be stored in context in the corresponding threshold value of predefined metadata size.In step 604, processing 600 can be waited for from flush memory device and read metadata or write metadata to the request of flush memory device.When carrying out read or write operation, process 600 and can move to step 606.In step 606, process 600 and can determine that whether the size of metadata is greater than predetermined threshold.When the size of metadata greater than predetermined threshold, process 600 and be movable to step 608.When the size of metadata is less than or equal to predetermined threshold, process 600 and be movable to step 610.
In step 608, process 600 can store the metadata that from flush memory device, reads to the context mechanism relevant with reading transaction (for example, by updating context port (CUP) 168), perhaps from (for example write transaction, by context searchig port (CRP) 166 and BC_RD_I/F) in the relevant context mechanism retrieval will be programmed into the metadata (for example, by context searchig port (CRP) 166 and BC_RD_I/F) of flush memory device.In step 610, process 600 and (for example can store the indicated position of the metadata that from flush memory device, reads defined metadata pointer to the context mechanism relevant with reading transaction, externally in the system buffer device), perhaps from write the context mechanism that is associated of transaction the indicated position of the metadata pointer that defines (for example, externally system buffer device in) retrieval will be programmed to the metadata in the flush memory device.For example, in program command, to retrieve metadata to 172n and BC_RD_I/F by data DMA fetch interface port (DDRIP) 172a separately, in reading order, will write by data DMA separately interface port (DDWIP) 174a to 174n and BC_WR_I/F update metadata.After the transaction in completing steps 608 or step 610, process 600 steps 604 that can return.
Flash media controller (FMC) according to embodiment of the present invention provides processing to be stored in the whole bag of tricks of the metadata in system buffer and/or the flash media controller generally.Flash media controller according to embodiment of the present invention can comprise following feature for the metadata processing.Can define metadata information on each context basis, wherein, defining context on each page base plinth.When the size of metadata is less than or equal to predetermined threshold, can in context mechanism, store complete metadata.At flash memory programming in the cycle, metadata from context (for example, by CRP166 and BC_RD_I/F) can be stored in the flash target, and in read cycle, the metadata that reads from flash target can be deposited back in the context mechanism (for example, passes through CUP168).When the size of metadata during greater than predetermined threshold, can in context, define the metadata pointer, rather than in context mechanism storing metadata.The metadata pointer can provide address pointer, (for example to retrieve metadata in the flash memory programming cycle from external system memory, by DDRIP and BC_RD_I/F separately) and will be stored to from the reading out data in the flash memory reading order position in the indicated external system memory of the metadata pointer of context appointment (for example, by separately DDWIP and BC_WR_I/F).In another example, FMC can be configured to the part of metadata and be processed by context, and another part of metadata is to be processed by external system memory.
The size of metadata is defined by flash memory transaction layer (FTL) usually.In one example, FTL can use the metadata of about 12 bytes.Maximum available backup district in the context 300 shown in Figure 10 is 28 bytes.Consider FTL metadata size parameter and the spare area parameter of context 300, can select the predetermined threshold of 28 bytes.For example, when the size of metadata less than or equal to 28 bytes, the complete metadata of storage in the context mechanism in can the flash memory channel controller in the flash media controller., can be stored in the flash target from contextual metadata in the cycle at flash memory programming, and at read cycle, the metadata that reads from flash target can be stored in the context mechanism.When the size of metadata during greater than 28 bytes, the flash memory channel controller defines the metadata pointer that points to the position of storing metadata in the external memory storage in context, rather than with metadata store in context mechanism.Be that (for example, as shown in figure 12), metadata is generally distributed each host subscriber's data in the situation of multiple of main frame size in the page or leaf size.For example, big or small for the main frames of the page or leaf size of 1K byte and 1024 bytes, in the flash memory programming order, can be distributed between two host subscriber's data the metadata of 14 bytes of each user data (for example, to) from contextual 28 bytes:
1(512 byte of host subscriber's data)+a metadata 1(14 byte)+ECC+
2(512 byte of host subscriber's data)+a metadata 2(14 byte)+ECC.
General by using ECC protection metadata.The use of ECC partly provides completeness check and correction to metadata usually.
Various signal of the present invention generally is " opening " (on) (for example, numeral is high, or 1) or " passs " (off) (for example, digital low, or 0).Yet opening (for example, keeping) and closing (for example, removing) of the particular polarity of signal condition can correspondingly be adjusted (for example, putting upside down), to satisfy the design standards of particular implementation.
Institute is apparent as various equivalent modifications, the function that Fig. 1 implements to the diagram of Fig. 9 and Figure 13 can be used one or more traditional general processors, digital computer, microprocessor, microcontroller, the RISC(Reduced Instruction Set Computer) processor, the CISC(complex instruction set computer (CISC)) processor, the SIMD(single instruction multiple data) processor, digital signal processor, CPU (central processing unit) (CPU), ALU (ALU), video digital signal processor (VDSP) and/or similar computing machine are realized, and can be programmed according to the instruction of this instructions.Also apparent as various equivalent modifications institute, skilled programmer can work out suitable software, firmware, coding, programming, instruction, operational code, microcode and/or programming module based on explanation of the present invention.One or more processors that software is implemented by machine from medium or a plurality of media are usually carried out.
The present invention also can pass through the ASIC(special IC), platform ASIC, the FPGA(field programmable gate array), the PLD(programmable logic device (PLD)), the CPLD(CPLD), magnanimity door (sea-of-gates), the RFIC(radio frequency integrated circuit), ASSP(application-specific standardized product), one or more monolithic integrated optical circuits, be arranged as one or more chips or the nude film of flip-chip (flip-chip) module and/or multi-chip module, or realize with the stand-by mode of the suitably interconnected chip of conventional components circuit network, as described herein, its modification is apparent for those skilled in the art.
Therefore, the present invention can also comprise computer product, and it can be storage medium and/or the transmission medium that comprises instruction, and wherein, this instruction can be used for machine programming to carry out one or more treatment in accordance with the present invention or method.The execution of contained instruction in the computer product that is undertaken by machine, operation along with peripheral circuits, the input data-switching can be become the one or more files on the storage medium, and/or convert the one or more output signals such as audio frequency and/or vision description (depiction) of expression physical object or material to.Storage medium can include but are not limited to the disk of any type of floppy disk, hard disk, disk, CD, CD-ROM DVD and magneto-optic disk, such as ROM(read memory), the RAM(random access memory), EPROM(erasable programmable ROM), EEPROM(electrically erasable ROM), UVPROM(ultraviolet light erasable programming ROM), the circuit of flash memory, magnetic card, light-card, and/or any suitable media type that is used for the store electrons instruction.
Element of the present invention can form part or all of one or more devices, unit, parts, system, machine and/or device.These devices can include but not limited to server, workstation, storage array controllers, storage system, single computer, notebook computer, notebook computer, palm PC, the individual digit assistant, mobile electronic device, the powered battery device, the set-top box scrambler, demoder, transcoder, compressor, decompress, pretreater, preprocessor, transmitter, receiver, transceiver, cryptochannel, cell phone, digital camera, location and/or navigational system, medical device, head mounted display, wireless devices, recording, audio storage and/or audio player spare, video recording, video storage and/or video playback device, gaming platform, peripheral components and/or multi-chip module.Various equivalent modifications should be understood, and element of the present invention can be realized in the device of other types, to satisfy the standard of application-specific.
Although the present invention specifies with reference to its preferred implementation and describes that various equivalent modifications should be appreciated that under the prerequisite that does not deviate from scope of the present invention can carry out various variations in form and details.
Claims (17)
1. method that is used for processing at the flash media controller metadata in the page or leaf that is stored in flash memories, described method comprises:
In the described metadata of each contextual basis definition, wherein, described context is based on each page definition;
When the size of described metadata during less than or equal to predetermined threshold, with complete metadata store in context mechanism; And
When the size of described metadata during greater than described predetermined threshold, definition metadata pointer in described context.
2. method according to claim 1 also comprises:
The mistake in using correcting code is protected described metadata.
3. method according to claim 1, wherein, described metadata comprises management data.
4. method according to claim 1, wherein, described predetermined threshold is specified every page byte number.
5. method according to claim 1, wherein, during the flash memory programming cycle, will be from the described metadata store of described context mechanism in flash target, and during read cycle, will deposit back the described context mechanism from the described metadata that described flash target reads.
6. method according to claim 1, wherein, described metadata pointer provides address pointer, during the flash memory programming cycle, retrieving described metadata from external system memory, and will be from the described metadata store of the flash memory reading order indicated position of described metadata pointer by described context appointment to the described external system memory.
7. method according to claim 1, wherein:
During the flash memory programming cycle, with the first that is stored in the metadata in the flash target from described context mechanism, and the second portion that will be stored in the described metadata in the described flash target from the external system memory by the indicated position of described metadata pointer of described context appointment; And
During read cycle, the described first of the described metadata that will read from described flash target deposits back in the described context mechanism, and described second portion is stored in the described external system memory the indicated position of described metadata pointer by described context appointment.
8. method according to claim 1 wherein, when the page or leaf size is the multiple of main frame size, is distributed described metadata between each of a plurality of host subscriber's data sector.
9. device comprises:
The flash memories that comprises a plurality of flash media devices, described flash memories are organized into a plurality of pages or leaves;
The flash media controller, be configured to metadata store in one or more pages or leaves of described flash memories, wherein, (i) described flash media controller is at the described context of the basis of each page definition, and based on the described metadata of each contextual definition, (ii) when the size of described metadata during less than or equal to predetermined threshold, described flash media controller with complete metadata store in context mechanism, (iii) when the size of described metadata during greater than described predetermined threshold, described flash media controller defines the metadata pointer in described context.
10. device according to claim 9, wherein, described flash media controller mistake in using correcting code is protected described metadata.
11. device according to claim 9, wherein, described metadata comprises management data.
12. device according to claim 9, wherein, for the metadata size less than or equal to described predetermined threshold:
During the flash memory programming cycle, described flash media controller will be from the described metadata store of described context mechanism in flash target; And
During read cycle, the described metadata that described flash media controller will read from described flash target is deposited back in the described context mechanism.
13. device according to claim 9, wherein, the byte number that described predetermined threshold definition is every page.
14. device according to claim 9, wherein, described metadata pointer provides the address pointer that is used by described flash media controller, during the flash memory programming cycle, retrieving described metadata from external system memory, and will from the described metadata store of flash memory reading order to the described external system memory by in the indicated position of the described metadata pointer of described context appointment.
15. device according to claim 9, wherein,
During the flash memory programming cycle, with the first that is stored in the metadata in the flash target from described context mechanism, and the second portion that will be stored in the described metadata in the flash target from the external system memory by the indicated position of described metadata pointer of described context appointment; And
During read cycle, the described first of the described metadata that will read from described flash target deposits back the described context mechanism, and described second portion is stored in the described external system memory the indicated position of described metadata pointer by described context appointment.
16. device according to claim 9, wherein, when the size of the page or leaf of described flash memories when being the multiple of main frame size, described flash media controller also is configured to distribute described metadata between each of a plurality of host subscriber's data sector.
17. a flash memory system comprises:
Be used for the device in each contextual basis definition metadata, wherein, described context is based on each page definition;
When being used for size when described metadata less than or equal to predetermined threshold, with the device of complete metadata store at context mechanism; And
Define the device of metadata pointer when being used for size when described metadata greater than described predetermined threshold, at described context.
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Cited By (8)
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|---|---|---|---|---|
| CN106486167A (en) * | 2015-08-24 | 2017-03-08 | Hgst荷兰公司 | Improve the method and system that flash memory is removed |
| WO2017097042A1 (en) * | 2015-12-07 | 2017-06-15 | 国民技术股份有限公司 | Secure chip, and nonvolatile storage control device and method for same |
| CN108255464A (en) * | 2016-12-28 | 2018-07-06 | 北京忆恒创源科技有限公司 | Data scrambling method, de-scrambling method and its device |
| CN108780424A (en) * | 2016-03-30 | 2018-11-09 | 高通股份有限公司 | Space-efficient storage for dynamic random access memory DRAM cache label is provided |
| CN109697176A (en) * | 2017-10-20 | 2019-04-30 | 慧荣科技股份有限公司 | Storage device and its interface chip |
| CN111435331A (en) * | 2019-01-14 | 2020-07-21 | 杭州宏杉科技股份有限公司 | Data writing method and device for storage volume, electronic equipment and machine-readable storage medium |
| US11288182B2 (en) | 2019-06-21 | 2022-03-29 | Silicon Motion, Inc. | Method and computer program product and apparatus for multi-namespace data access |
| CN118035019A (en) * | 2024-04-10 | 2024-05-14 | 沐曦科技(北京)有限公司 | Data driving system based on improved arbitration mechanism |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101678919B1 (en) * | 2011-05-02 | 2016-11-24 | 삼성전자주식회사 | Memory system and error correction method |
| US20130124778A1 (en) * | 2011-11-10 | 2013-05-16 | Greenliant Llc | Method of storing host data and meta data in a nand memory, a memory controller and a memory system |
| KR101888009B1 (en) * | 2012-02-28 | 2018-09-07 | 삼성전자주식회사 | Storage device |
| US9921954B1 (en) * | 2012-08-27 | 2018-03-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for split flash memory management between host and storage controller |
| US8972826B2 (en) * | 2012-10-24 | 2015-03-03 | Western Digital Technologies, Inc. | Adaptive error correction codes for data storage systems |
| US9348746B2 (en) | 2012-12-31 | 2016-05-24 | Sandisk Technologies | Method and system for managing block reclaim operations in a multi-layer memory |
| US9734911B2 (en) * | 2012-12-31 | 2017-08-15 | Sandisk Technologies Llc | Method and system for asynchronous die operations in a non-volatile memory |
| US9734050B2 (en) | 2012-12-31 | 2017-08-15 | Sandisk Technologies Llc | Method and system for managing background operations in a multi-layer memory |
| US9336133B2 (en) | 2012-12-31 | 2016-05-10 | Sandisk Technologies Inc. | Method and system for managing program cycles including maintenance programming operations in a multi-layer memory |
| US9465731B2 (en) | 2012-12-31 | 2016-10-11 | Sandisk Technologies Llc | Multi-layer non-volatile memory system having multiple partitions in a layer |
| US9223693B2 (en) | 2012-12-31 | 2015-12-29 | Sandisk Technologies Inc. | Memory system having an unequal number of memory die on different control channels |
| KR102050729B1 (en) * | 2013-02-12 | 2019-12-02 | 삼성전자 주식회사 | Memory System |
| WO2014167670A1 (en) | 2013-04-10 | 2014-10-16 | 三菱電機株式会社 | Data transfer device and data transfer method |
| US9575884B2 (en) | 2013-05-13 | 2017-02-21 | Qualcomm Incorporated | System and method for high performance and low cost flash translation layer |
| WO2015029230A1 (en) * | 2013-08-30 | 2015-03-05 | 株式会社日立製作所 | Storage device and data control method |
| JP6028709B2 (en) * | 2013-10-18 | 2016-11-16 | ソニー株式会社 | Storage control device, storage device, information processing system, and storage control method thereof |
| US9798493B2 (en) | 2013-12-16 | 2017-10-24 | International Business Machines Corporation | Firmware bypass for medium-access commands |
| US9633749B2 (en) | 2013-12-19 | 2017-04-25 | Sandisk Technologies Llc | System and method of managing tags associated with read voltages |
| TWI523025B (en) * | 2013-12-27 | 2016-02-21 | 慧榮科技股份有限公司 | Data storage device and error correction method thereof |
| US20150199282A1 (en) * | 2014-01-16 | 2015-07-16 | Storart Technology Co., Ltd. | Scramble random seed prediction method with storage device built-in data copy back procedure |
| US9535785B2 (en) | 2014-01-17 | 2017-01-03 | Macronix International Co., Ltd. | ECC method for flash memory |
| US9921909B2 (en) | 2015-07-03 | 2018-03-20 | Qualcomm Incorporated | Systems and methods for providing error code detection using non-power-of-two flash cell mapping |
| US20170017414A1 (en) | 2015-07-15 | 2017-01-19 | Innovium, Inc. | System And Method For Implementing Hierarchical Distributed-Linked Lists For Network Devices |
| US20170017420A1 (en) | 2015-07-15 | 2017-01-19 | Innovium, Inc. | System And Method For Enabling High Read Rates To Data Element Lists |
| US20170017419A1 (en) | 2015-07-15 | 2017-01-19 | Innovium, Inc. | System And Method For Enabling High Read Rates To Data Element Lists |
| US20170017567A1 (en) * | 2015-07-15 | 2017-01-19 | Innovium, Inc. | System And Method For Implementing Distributed-Linked Lists For Network Devices |
| US10133490B2 (en) | 2015-10-30 | 2018-11-20 | Sandisk Technologies Llc | System and method for managing extended maintenance scheduling in a non-volatile memory |
| US9778855B2 (en) | 2015-10-30 | 2017-10-03 | Sandisk Technologies Llc | System and method for precision interleaving of data writes in a non-volatile memory |
| US10042553B2 (en) | 2015-10-30 | 2018-08-07 | Sandisk Technologies Llc | Method and system for programming a multi-layer non-volatile memory having a single fold data path |
| US10120613B2 (en) | 2015-10-30 | 2018-11-06 | Sandisk Technologies Llc | System and method for rescheduling host and maintenance operations in a non-volatile memory |
| US10509742B2 (en) | 2016-05-16 | 2019-12-17 | Hewlett Packard Enterprise Development Lp | Logical memory buffers for a media controller |
| US9983930B2 (en) * | 2016-07-28 | 2018-05-29 | Qualcomm Incorporated | Systems and methods for implementing error correcting code regions in a memory |
| KR102717098B1 (en) * | 2016-11-01 | 2024-10-15 | 삼성전자주식회사 | Memory device with stepwise low power states |
| TWI680374B (en) * | 2017-10-20 | 2019-12-21 | 慧榮科技股份有限公司 | Storage device and interface chip thereof |
| TWI721565B (en) * | 2017-10-20 | 2021-03-11 | 慧榮科技股份有限公司 | Storage device and interface chip thereof |
| TWI639157B (en) | 2017-10-30 | 2018-10-21 | 新唐科技股份有限公司 | Semiconductor device and automatic adjustment method of access cycles of flash memory thereof |
| KR20220023649A (en) | 2020-08-21 | 2022-03-02 | 에스케이하이닉스 주식회사 | Memory controller and operating method thereof |
| US12210456B2 (en) * | 2021-03-26 | 2025-01-28 | Intel Corporation | Dynamic random access memory (DRAM) with scalable meta data |
| US11379752B1 (en) * | 2021-05-27 | 2022-07-05 | Red Hat, Inc. | Qubit reservation service |
| US11714692B2 (en) | 2021-05-27 | 2023-08-01 | Red Hat, Inc. | Classical management of qubit requests |
| US12159033B2 (en) | 2022-10-18 | 2024-12-03 | Qualcomm Incorporated | Metadata registers for a memory device |
| TW202524321A (en) * | 2023-08-18 | 2025-06-16 | 南韓商三星電子股份有限公司 | Memory device and memory system |
| TW202522469A (en) * | 2023-08-29 | 2025-06-01 | 南韓商三星電子股份有限公司 | Memory device and memory module including the same |
| KR20250121682A (en) * | 2024-02-05 | 2025-08-12 | 삼성전자주식회사 | Memory controller and storage device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100023682A1 (en) * | 2007-10-11 | 2010-01-28 | Super Talent Electronics Inc. | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read |
| CN101676882A (en) * | 2008-09-16 | 2010-03-24 | 美光科技公司 | Built-in mapping message of memory device |
| US20100083247A1 (en) * | 2008-09-26 | 2010-04-01 | Netapp, Inc. | System And Method Of Providing Multiple Virtual Machines With Shared Access To Non-Volatile Solid-State Memory Using RDMA |
| US20100198888A1 (en) * | 2009-01-30 | 2010-08-05 | Blomstedt Linda C | System for managing distributed assets and medadata |
| CN101911612A (en) * | 2008-01-08 | 2010-12-08 | 阿克塞斯股份公司 | Network offload with reduced packet loss |
| US20110131346A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Context Processing for Multiple Active Write Commands in a Media Controller Architecture |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4030072A (en) | 1974-12-18 | 1977-06-14 | Xerox Corporation | Computer system operation and control |
| US4766533A (en) | 1984-03-09 | 1988-08-23 | The United States Of America As Represented By The United States National Aeronautics And Space Administration | Nanosequencer digital logic controller |
| US5438668A (en) | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
| US6735685B1 (en) | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
| US5430841A (en) | 1992-10-29 | 1995-07-04 | International Business Machines Corporation | Context management in a graphics system |
| FR2708763B1 (en) | 1993-06-30 | 2002-04-05 | Intel Corp | Flash memory device, method and circuit for processing a user command in a flash memory device and computer system comprising a flash memory device. |
| US5802553A (en) | 1995-12-19 | 1998-09-01 | Intel Corporation | File system configured to support variable density storage and data compression within a nonvolatile memory |
| US6157963A (en) | 1998-03-24 | 2000-12-05 | Lsi Logic Corp. | System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients |
| US7149846B2 (en) | 2002-04-17 | 2006-12-12 | Lsi Logic Corporation | RAID protected external secondary memory |
| US7277978B2 (en) | 2003-09-16 | 2007-10-02 | Micron Technology, Inc. | Runtime flash device detection and configuration for flash data management software |
| US7596639B2 (en) * | 2004-09-01 | 2009-09-29 | Lsi Corporation | Skip mask table automated context generation |
| US7817767B2 (en) | 2004-12-23 | 2010-10-19 | Rambus Inc. | Processor-controlled clock-data recovery |
| KR100772376B1 (en) * | 2005-06-23 | 2007-11-01 | 삼성전자주식회사 | Image forming apparatus and method |
| US20070083697A1 (en) * | 2005-10-07 | 2007-04-12 | Microsoft Corporation | Flash memory management |
| US20070094445A1 (en) | 2005-10-20 | 2007-04-26 | Trika Sanjeev N | Method to enable fast disk caching and efficient operations on solid state disks |
| GB0606012D0 (en) | 2006-03-25 | 2006-05-03 | Zenopia Ltd | Data storage |
| US8751467B2 (en) * | 2007-01-18 | 2014-06-10 | Dot Hill Systems Corporation | Method and apparatus for quickly accessing backing store metadata |
| KR100823171B1 (en) | 2007-02-01 | 2008-04-18 | 삼성전자주식회사 | Computer system with partitioned flash translation layer and partitioning method of flash translation layer |
| CN100458751C (en) | 2007-05-10 | 2009-02-04 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
| US8572310B2 (en) * | 2007-11-06 | 2013-10-29 | Samsung Electronics Co., Ltd. | Invalidating storage area of non-volatile storage medium based on metadata |
| US7870351B2 (en) | 2007-11-15 | 2011-01-11 | Micron Technology, Inc. | System, apparatus, and method for modifying the order of memory accesses |
| US9152496B2 (en) | 2007-12-21 | 2015-10-06 | Cypress Semiconductor Corporation | High performance flash channel interface |
| US8621137B2 (en) | 2007-12-27 | 2013-12-31 | Sandisk Enterprise Ip Llc | Metadata rebuild in a flash memory controller following a loss of power |
| US7873619B1 (en) | 2008-03-31 | 2011-01-18 | Emc Corporation | Managing metadata |
| KR101486987B1 (en) | 2008-05-21 | 2015-01-30 | 삼성전자주식회사 | Semiconductor memory device including nonvolatile memory and commnand scheduling method for nonvolatile memory |
| US8732388B2 (en) * | 2008-09-16 | 2014-05-20 | Micron Technology, Inc. | Embedded mapping information for memory devices |
| JP5272013B2 (en) * | 2008-10-01 | 2013-08-28 | 株式会社日立製作所 | Semiconductor device |
| KR101543431B1 (en) * | 2008-11-20 | 2015-08-11 | 삼성전자주식회사 | Non-volatile memroy system and access method thereof |
| US20110289112A1 (en) * | 2009-01-26 | 2011-11-24 | Junpei Kamimura | Database system, database management method, database structure, and storage medium |
| US8205037B2 (en) | 2009-04-08 | 2012-06-19 | Google Inc. | Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages |
| US8706727B2 (en) * | 2009-06-19 | 2014-04-22 | Sybase, Inc. | Data compression for reducing storage requirements in a database system |
| US20110041039A1 (en) | 2009-08-11 | 2011-02-17 | Eliyahou Harari | Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device |
| DE112010003762B4 (en) | 2009-12-11 | 2012-12-06 | International Business Machines Corporation | Flash memory controller |
| US8611678B2 (en) * | 2010-03-25 | 2013-12-17 | Apple Inc. | Grouping digital media items based on shared features |
| US8468318B2 (en) | 2010-09-15 | 2013-06-18 | Pure Storage Inc. | Scheduling of I/O writes in a storage environment |
-
2011
- 2011-12-22 US US13/334,599 patent/US8806112B2/en active Active
-
2012
- 2012-06-19 JP JP2012138094A patent/JP5960517B2/en not_active Expired - Fee Related
- 2012-07-13 CN CN2012102442055A patent/CN103034562A/en active Pending
- 2012-07-13 EP EP12176435A patent/EP2546751A1/en not_active Withdrawn
- 2012-07-13 KR KR1020120076961A patent/KR20130009927A/en not_active Withdrawn
- 2012-07-16 TW TW101125546A patent/TW201303587A/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100023682A1 (en) * | 2007-10-11 | 2010-01-28 | Super Talent Electronics Inc. | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read |
| CN101911612A (en) * | 2008-01-08 | 2010-12-08 | 阿克塞斯股份公司 | Network offload with reduced packet loss |
| CN101676882A (en) * | 2008-09-16 | 2010-03-24 | 美光科技公司 | Built-in mapping message of memory device |
| US20100083247A1 (en) * | 2008-09-26 | 2010-04-01 | Netapp, Inc. | System And Method Of Providing Multiple Virtual Machines With Shared Access To Non-Volatile Solid-State Memory Using RDMA |
| US20100198888A1 (en) * | 2009-01-30 | 2010-08-05 | Blomstedt Linda C | System for managing distributed assets and medadata |
| US20110131346A1 (en) * | 2009-11-30 | 2011-06-02 | Noeldner David R | Context Processing for Multiple Active Write Commands in a Media Controller Architecture |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486167B (en) * | 2015-08-24 | 2019-11-15 | Hgst荷兰公司 | Method and system for improving flash memory clearing |
| CN106486167A (en) * | 2015-08-24 | 2017-03-08 | Hgst荷兰公司 | Improve the method and system that flash memory is removed |
| WO2017097042A1 (en) * | 2015-12-07 | 2017-06-15 | 国民技术股份有限公司 | Secure chip, and nonvolatile storage control device and method for same |
| TWI619019B (en) * | 2015-12-07 | 2018-03-21 | Nationz Technologies Inc. | Security chip, non-volatile memory control device and non-volatile memory control method |
| CN108780424A (en) * | 2016-03-30 | 2018-11-09 | 高通股份有限公司 | Space-efficient storage for dynamic random access memory DRAM cache label is provided |
| CN108780424B (en) * | 2016-03-30 | 2022-10-28 | 高通股份有限公司 | Providing space efficient storage for dynamic random access memory DRAM cache tags |
| CN108255464A (en) * | 2016-12-28 | 2018-07-06 | 北京忆恒创源科技有限公司 | Data scrambling method, de-scrambling method and its device |
| CN109697176B (en) * | 2017-10-20 | 2022-06-07 | 慧荣科技股份有限公司 | Storage device and its interface chip |
| CN109697176A (en) * | 2017-10-20 | 2019-04-30 | 慧荣科技股份有限公司 | Storage device and its interface chip |
| CN111435331A (en) * | 2019-01-14 | 2020-07-21 | 杭州宏杉科技股份有限公司 | Data writing method and device for storage volume, electronic equipment and machine-readable storage medium |
| CN111435331B (en) * | 2019-01-14 | 2022-08-26 | 杭州宏杉科技股份有限公司 | Data writing method and device for storage volume, electronic equipment and machine-readable storage medium |
| US11288182B2 (en) | 2019-06-21 | 2022-03-29 | Silicon Motion, Inc. | Method and computer program product and apparatus for multi-namespace data access |
| TWI766207B (en) * | 2019-06-21 | 2022-06-01 | 慧榮科技股份有限公司 | Method and computer program product for multi-namespace data access |
| CN118035019A (en) * | 2024-04-10 | 2024-05-14 | 沐曦科技(北京)有限公司 | Data driving system based on improved arbitration mechanism |
| CN118035019B (en) * | 2024-04-10 | 2024-06-21 | 沐曦科技(北京)有限公司 | Data driving system based on improved arbitration mechanism |
Also Published As
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|---|---|
| KR20130009927A (en) | 2013-01-24 |
| JP5960517B2 (en) | 2016-08-02 |
| US8806112B2 (en) | 2014-08-12 |
| JP2013025793A (en) | 2013-02-04 |
| EP2546751A1 (en) | 2013-01-16 |
| US20130019051A1 (en) | 2013-01-17 |
| TW201303587A (en) | 2013-01-16 |
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