CN103021865B - Metal silicide film and the manufacture method of ultra-shallow junctions - Google Patents

Abstract

The invention relates to the technical field of semiconductors, and discloses a method for manufacturing a metal silicide thin film and an ultra-shallow junction. In the present invention, by using a mixture of metal and semiconductor doped with impurities as the target material, the physical vapor deposition PVD method deposits the mixture film on the semiconductor substrate, removes the mixture film by wet method, and performs annealing to form a metal silicide film and super Shallow knot. Since the mixture of metal and semiconductor doped with impurities is used as the target to deposit the mixture film, and the mixture film is removed by wet method before heating and annealing, the self-limiting ultra-thin uniform metal can be formed synchronously in the process of semiconductor field effect transistor fabrication. Silicide thin films and ultra-shallow junctions can be used in field effect transistors of 14nm, 11nm and below technology nodes.

Description

Fabrication method of metal silicide film and ultra-shallow junction

technical field

The invention relates to the technical field of semiconductors, in particular to a method for making a metal silicide thin film and an ultra-shallow junction.

Background technique

With the advancement of the semiconductor industry, the feature size of semiconductor devices has become smaller and smaller with the innovation of process technology. While the lateral size of the device is continuously shrinking, the vertical size of the device is also shrinking accordingly. Especially when entering the node of 65 nanometers and below, the source/drain region and the source/drain extension region are required to be correspondingly shallower, and the doped junction with a junction depth of less than 100 nanometers is usually called an ultra-shallow junction (UltraShallowJunction, referred to as "USJ") ”), the ultra-shallow junction can better improve the short-channel effect of the device. As ultra-shallow junctions become shallower, one of the main challenges facing ultra-shallow junction technology is how to solve the contradiction between reducing the series parasitic resistance and reducing the junction depth of ultra-shallow junctions.

In the prior art, ion implantation technology is usually used to form ultra-shallow junctions, such as forming highly doped source regions and drain regions of metal-oxide-semiconductor MOS transistors. That is to say, use the gate structure as a mask, implant N-type or P-type dopant impurities into the semiconductor substrate, then perform annealing to activate to form a shallow PN junction, then deposit a metal film, perform heating and annealing, and form metal silicide, and perform wet etching to remove the remaining metal to form metal silicide. As transistors shrink in size, the length of their gates also shrinks. As the gate length continues to shrink, the source/drain and source/drain extensions are required to be correspondingly shallower. Ultra-shallow junctions are usually formed by ultra-low energy ion implantation and millisecond laser annealing activation technology. The ultra-shallow junction depth of semiconductor field-effect transistors of future technology nodes will be less than 10 nanometers. Due to the huge challenges of ultra-low energy ion implantation technology itself and the diffusion of impurities during annealing and activation, it is a huge challenge to use conventional ultra-low energy ion implantation and annealing activation technology to form field effect transistors suitable for future technology nodes.

Contents of the invention

The purpose of the present invention is to provide a metal silicide thin film and ultra-shallow junction manufacturing method, so that the self-limiting limit ultra-thin uniform metal silicide thin film and ultra-shallow junction can be formed synchronously during the semiconductor field effect transistor manufacturing process, which can be applied in 14nm, 11nm and below technology node field effect transistors.

In order to solve the above technical problems, an embodiment of the present invention provides a method for fabricating a metal silicide film and an ultra-shallow junction, comprising the following steps:

A. Provide semiconductor substrates;

B. using a mixture of metal and semiconductor doped impurities as a target material, and depositing a thin film of the mixture on the semiconductor substrate by physical vapor deposition PVD;

C. wet removal of the mixture film;

D. Annealing the semiconductor substrate on which the mixture film has been deposited and removed to form a metal silicide film and an ultra-shallow junction; the ultra-shallow junction is a PN junction or a metal-semiconductor junction.

Compared with the prior art, the embodiment of the present invention uses a mixture of metal and semiconductor doped with impurities as a target material, deposits the mixture film on the semiconductor substrate by physical vapor deposition PVD method, removes the mixture film by wet method, and performs Annealing forms metal silicide films and ultra-shallow junctions. Since the mixture of metal and semiconductor doped with impurities is used as the target to deposit the mixture film, and the mixture film is removed by wet method before heating and annealing, the self-limiting ultra-thin uniform metal can be formed synchronously in the process of semiconductor field effect transistor fabrication. Silicide thin films and ultra-shallow junctions can be used in field effect transistors of 14nm, 11nm and below technology nodes.

In addition, before the step D, the step B and the step C are performed at least twice; that is, before the annealing, the deposition and wet removal of the mixture film are performed multiple times, which can be achieved through repeated execution Limiting the thickness of the metal silicide thin film and the ultra-shallow junction by the number of times can also make the finally formed metal silicide thin film and ultra-shallow junction more uniform.

In addition, in the step of performing the step B and the step C at least twice, each time the step B is performed, a different mixture of metal and semiconductor doped impurities is used as the target material. That is to say, metals can be selected according to actual needs to prepare metal silicides, and the selection range of metals that can be used to form metal silicides can be expanded, so that the resistance of metal silicides can be as small as possible, and the application is more flexible.

In addition, in the step B, the target is ionized into an ionic state to generate metal ions and semiconductor dopant impurity ions, and a substrate bias is applied to the semiconductor substrate. The ionization of the target material into an ion state is realized by applying a first bias voltage to the target material.

By ionizing the target and depositing the mixture film by applying substrate bias on the semiconductor substrate, on the one hand, metal ions and semiconductor dopant impurity ions can be deposited on the surface of the semiconductor substrate at a certain acceleration. The diffusion depth of ions can be controlled; on the other hand, the uniformity and stability of film deposition on the three-dimensional structure can be improved.

In addition, in the step D, microwave heating may be used for annealing. In the step of annealing by microwave heating, the cavity of the microwave heating equipment used for the microwave annealing contains multi-mode and multi-frequency electromagnetic waves during heating.

By adopting microwave heating annealing technology, metal silicide and ultra-shallow junction can be formed at a relatively low temperature, so that metal silicide can exist stably.

Description of drawings

Fig. 1 is the flow chart of the fabrication method of metal silicide thin film and ultra-shallow junction according to the first embodiment of the present invention;

2A to 2E are structural cross-sectional schematic diagrams corresponding to each step of the fabrication method of the metal silicide film and the ultra-shallow junction according to the first embodiment of the present invention;

Fig. 3 is a schematic structural diagram of depositing a mixture of metal and semiconductor doping impurities on a semiconductor substrate in the method for manufacturing an ultra-shallow junction semiconductor field effect transistor according to the first embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that, in each implementation manner of the present invention, many technical details are provided for readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following implementation modes, the technical solution claimed in each claim of the present application can be realized.

The first embodiment of the present invention relates to a method for fabricating a metal silicide thin film and an ultra-shallow junction. The specific process is shown in FIG. 1 and includes the following steps:

Step 101, provide a semiconductor substrate 201, as shown in FIG. 2A; the semiconductor substrate can be silicon (Si), germanium (Ge), silicon germanium (SiGe), or III-V semiconductor. A gate structure 202 is formed on the semiconductor substrate, including a gate dielectric layer, a gate electrode and a protection layer for sidewalls thereof. The method for forming the gate structure is consistent with the prior art, and will not be repeated here.

In step 102, a mixture of metal and semiconductor doped with impurities is used as a target material, and a mixture film is deposited on a semiconductor substrate by physical vapor deposition PVD method, as shown in FIG. 2B , 203 is a mixture film.

Physical vapor deposition (PVD) is a well-known technique used in the manufacture of integrated circuits. During PVD, the desired coating material is deposited onto the substrate as a spray target. As shown in Figure 3, it is a schematic diagram of a PVD cavity. The target 301 and the semiconductor substrate 201 formed with the gate structure 202 are placed in a vacuum chamber 300, which is evacuated and maintained at a very low pressure (eg, less than 10 mTorr).

The vacuum cavity 300 is filled with an inert gas 303, such as argon, and the required gas pressure in the cavity is maintained by a pumping system (not shown in the figure). Using conventional methods, a glow discharge plasma is generated in a low pressure gas, at least partially ionizing the gas. If the target is properly biased, positive ions in the plasma can be accelerated towards the target, causing the target 305 to be ejected from the target electrode. Part of the sputtered target material is deposited onto the semiconductor substrate 201 to form a mixture film 203 .

In this embodiment, the target material is a metal-rich mixture in the form of a polycrystalline solid material. The mixture can be obtained by mixing metal powder and semiconductor powder doped with impurities, and through heat treatment or other treatments. The semiconductor doping impurities in the target are evenly distributed in the metal. Wherein, the content of semiconductor doping impurities in the mixture of metal and semiconductor doping impurities is between 0.1% and 5%. The metal may be any one of nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), molybdenum (Mo) or an alloy formed in any combination thereof. Nickel is preferred for most applications. Nickel is usually Pt, W or other combinations of the above mentioned metals for stability and adjustment of Schottky barrier height. Semiconductor doping impurities can be P-type doped boron (B), boron fluoride (BF ₂ ), indium (Indium) any one or a mixture of any combination; or N-type doped phosphorus (P), arsenic Any one of (As) or a mixture of any combination.

Although the target material is a mixture of metals and semiconductors doped with impurities, the process flow of the PVD method is consistent with the prior art and will not be repeated here. After depositing the mixture film, metal ions and semiconductor dopant impurity ions will permeate into the semiconductor substrate, forming an ultra-shallow ion diffusion region in the semiconductor substrate, as shown by 204 in FIG. 2C . Specifically, the metal in the mixture film 203 will react with the semiconductor substrate to form a metal silicide, and the semiconductor doping impurities in the mixture film 203 will diffuse to the metal silicide, the interface between the metal silicide and the semiconductor substrate, and ions The interface between the region and the semiconductor substrate and the diffusion in the semiconductor substrate form the ion diffusion region 204 .

Step 103, wet removal of the mixture film, as shown in FIG. 2D. In this step, conventional wet etching techniques may be used to remove the remaining mixture film on the surface of the semiconductor substrate, which will not be repeated here.

Step 104, annealing the semiconductor substrate on which the mixture film has been deposited and removed to form a metal silicide film and an ultra-shallow junction, as shown in Figure 2E, 205 and 207 are the metal silicide contact regions of the source or drain , 206 and 208 are the impurity diffusion regions of the source or drain. Normally, a PN junction is formed between the impurity diffusion regions 206 and 208 and the semiconductor substrate, and an ohmic contact is formed between the metal silicide 205/207 and the impurity diffusion regions 206/208. However, when the formed impurity diffusion regions 206 and 208 are sufficiently small (for example, less than 1.5 nanometers), a metal-semiconductor contact is formed between the metal silicide and the semiconductor substrate.

In this step, conventional rapid thermal annealing (RTP) can be used for annealing, and microwave heating can also be used for annealing. The process flow is similar to the conventional annealing process, and metal silicide and ultra-shallow Junction, so that the metal silicide can exist stably. In addition, the substrate temperature when depositing the mixture thin film on the semiconductor substrate may be between 0 and 300°C. According to the formation temperature and the highest stable temperature of different metal silicides, the annealing temperature can be between 300 and 800°C. In step 102, metal and semiconductor dopant impurities diffuse to the semiconductor substrate to form a metal silicide; and the semiconductor dopant impurities contained in the metal silicide will continue to diffuse to the semiconductor substrate during annealing to form an ultra-shallow junction . Since the formation temperature and stable existence temperature of metal silicides are relatively low, for example, the stable existence temperatures of nickel silicide (NiSi), cobalt silicide (CoSi ₂ ), and titanium silicide (TiSi ₂ ) are respectively less than 600, 700, and 1000°C, so , when metal silicides and ultra-shallow junctions are formed at relatively low temperatures, it may cause semiconductor doping impurities to not be fully activated in the semiconductor substrate, but if they can be fully activated, a PN junction will be formed; and if they cannot be fully activated If activated, a metal-semiconductor junction can also be formed; that is, in the process of forming an ultra-shallow junction and an ultra-thin metal silicide, the formed ultra-shallow junction can be a PN junction or a metal-semiconductor junction.

The ultra-shallow junction and metal silicide films formed by the above steps can be applied in ultra-shallow junction semiconductor field effect transistors. The thickness of the metal silicide is about 3 to 12 nanometers, and the junction depth is about 1 to 15 nanometers. The peak doping concentration in the source/drain region of the ultrashallow junction is about 2×10 ¹⁹ to 2×10 ²⁰ ions per cubic centimeter, and the length of the gate structure is about 7 to 25 nanometers.

In addition, it is worth mentioning that metal silicide and ultra-shallow junction can be formed at a relatively low temperature by using microwave heating annealing technology, so that metal silicide can exist stably. In addition, different materials on the substrate have different abilities to absorb microwave energy. Moreover, microwave heating is closely related to defects in the substrate. The damage to the semiconductor lattice caused by impurities or other factors can be regarded as defects. Defects The more, the greater the microwave heating effect, that is, the defect can enhance the ability of microwave absorption. In view of this feature, using microwave heating for annealing can improve the heating efficiency.

In addition, it is worth noting that since the mixture film contains metal and semiconductor doped impurities, when microwave annealing is performed, the cavity of the microwave heating equipment needs to contain multi-mode and multi-frequency electromagnetic waves during heating, and the microwave The center frequency is between 1.5GHz and 15GHz, so that the material to be heated can be fully heated. In addition, it is worth noting that when microwave heating is performed, the microwave electromagnetic waves used by microwave heating equipment have a Gaussian distribution around 5.8GHz, and multi-frequency heating can be performed at intervals of 30Hz-50Hz. At the same time, microwaves of different frequencies in the cavity At the same time, it has the feature of multi-mode, which can ensure the uniformity and consistency of microwave energy distribution inside the cavity, and further lead to the uniformity and consistency of heating the substrate.

Compared with the prior art, this embodiment uses a mixture of metal and semiconductor doped with impurities as the target material, deposits the mixture film on the semiconductor substrate by physical vapor deposition PVD method, removes the mixture film by wet method, and performs annealing to form Extreme ultrathin homogeneous metal silicide films and ultrashallow junctions. Since the mixture of metal and semiconductor doped with impurities is used as the target to deposit the mixture film, and the mixture film is removed by wet method before heating and annealing, the self-limiting ultra-thin uniform metal can be formed synchronously in the process of semiconductor field effect transistor fabrication. Silicide thin films and ultra-shallow junctions can be used in field effect transistors of 14nm, 11nm and below technology nodes.

The second embodiment of the present invention relates to a method for fabricating a metal silicide film and an ultra-shallow junction. The second embodiment is further improved on the basis of the first embodiment, and the main improvement is that: in the second embodiment of the present invention, before performing annealing, the deposition and wet removal of the mixture film are performed at least twice; That is to say, before performing annealing, the deposition and wet removal of the mixture film are performed multiple times, the thickness of the metal silicide film and the ultra-shallow junction can be limited by the number of repeated executions, and the final formed metal silicide film and Ultra-shallow knots are more uniform.

In addition, in the process of repeatedly depositing the mixture film and removing it by wet method, different metal and semiconductor impurity-doped mixtures can be used as targets each time the mixture film is deposited. For example, when depositing a mixture film, a mixture of platinum and boron is used for the first time, a mixture of nickel and boron is used for the second time, or a mixture of nickel and indium is used; that is to say, it can be selected according to actual needs. Using metals to prepare metal silicides can expand the selection range of metals that can be used when forming metal silicides, so that the resistance of metal silicides can be as small as possible, and the application is more flexible.

The third embodiment of the present invention relates to a method for fabricating a metal silicide film and an ultra-shallow junction. The third embodiment has been further improved on the basis of the first embodiment or the second embodiment. The main improvement is that: in the third embodiment of the present invention, the improved high-power pulsed magnetron sputtering technology (HiPIMS) is adopted For PVD deposition, by ionizing the target and depositing the mixture film by applying substrate bias on the semiconductor substrate, on the one hand, metal ions and semiconductor doped impurity ions can be deposited at a certain acceleration. The surface of the semiconductor substrate controls the diffusion depth of ions; on the other hand, it can improve the uniformity and stability of film deposition on the three-dimensional structure.

Specifically, in the process of depositing a mixture film on a semiconductor substrate by using a mixture of metal and semiconductor doped with impurities as a target material, the target material is ionized into an ion state to generate metal ions. Doping impurity ions with the semiconductor, and applying substrate bias on the semiconductor substrate. Wherein, ionizing the target material into an ion state is realized by applying a first bias voltage to the target material.

In addition, the first bias voltage may be any one of DC bias voltage, AC bias voltage or pulse bias voltage. The magnitude of the first bias voltage depends on the PVD system used, that is, the magnitude of the first bias voltage varies correspondingly depending on the PVD system; generally speaking, the magnitude of the first bias voltage is 200V-1000V, where For bias voltage and pulse bias voltage, the above values refer to their effective values. In addition, the substrate bias voltage is any one of DC bias voltage, AC bias voltage or pulse bias voltage. The magnitude of the substrate bias voltage is adjustable. By adjusting the magnitude of the substrate bias voltage, the amount of metal ions diffused to the surface of the semiconductor substrate can be adjusted, so that the thickness of the finally formed metal-semiconductor compound film can be adjusted. Generally, the magnitude of the substrate bias voltage is 200V-1000V, wherein for the AC bias voltage and the pulse bias voltage, the above magnitude refers to its effective value.

The fourth embodiment of the present invention relates to a semiconductor device, as shown in FIG. 2E , comprising: a metal silicide film and an ultra-shallow junction, and the metal silicide film and the ultra-shallow junction use a mixture of metal and semiconductor doped impurities as a target , using the physical vapor deposition PVD method to deposit the mixture film on the semiconductor substrate, remove the mixture film by wet method, and perform annealing to form; wherein, the ultra-shallow junction is a PN junction or a metal-semiconductor junction.

Since the mixture of metal and semiconductor doped with impurities is used as the target to deposit the mixture film, and the mixture film is removed by wet method before heating and annealing, the self-limiting ultra-thin uniform metal can be formed synchronously in the process of semiconductor field effect transistor fabrication. Silicide thin films and ultra-shallow junctions can be used in field effect transistors of 14nm, 11nm and below technology nodes. For example, the thickness of the metal silicide is about 3 to 12 nanometers, the junction depth is about 1 to 15 nanometers, and the peak doping concentration in the source/drain region of the ultra-shallow junction is about 2× per cubic centimeter 10 ¹⁹ to 2×10 ²⁰ ions, the length of the gate structure is about 7 to 25 nanometers.

It should be noted that the content of semiconductor doping impurities in the mixture of metal and semiconductor doping impurities is between 0.1% and 5%. The metal may be any one of nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), molybdenum (Mo), or an alloy formed in any combination thereof. Nickel is preferred for most applications. Nickel is usually Pt, W or other combinations of the above mentioned metals for stability and adjustment of Schottky barrier height. Semiconductor doping impurities can be P-type doped boron (B), boron fluoride (BF ₂ ), indium (Indium) any one or a mixture of any combination; or N-type doped phosphorus (P), arsenic Any one of (As) or a mixture of any combination.

It is not difficult to find that this embodiment is a system embodiment corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and will not be repeated here in order to reduce repetition. Correspondingly, the relevant technical details mentioned in this implementation manner can also be applied in the first implementation manner.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, various changes can be made to it in form and details without departing from the spirit and spirit of the present invention. scope.

Claims (16)

1. A method for making a metal silicide film and an ultra-shallow junction, characterized in that it comprises the following steps: A. Provide semiconductor substrates; B. Using a mixture of metal and semiconductor doped impurities as a target material, a thin film of the mixture is deposited on the semiconductor substrate by physical vapor deposition; C. wet removal of the mixture film; D. Annealing the semiconductor substrate on which the mixture film has been deposited and removed to form a metal silicide film and an ultra-shallow junction; the ultra-shallow junction is a PN junction or a metal-semiconductor junction. 2. The method for fabricating metal silicide films and ultra-shallow junctions according to claim 1, characterized in that, before the step D, the step B and the step C are performed at least twice. 3. The method for manufacturing metal silicide films and ultra-shallow junctions according to claim 2, characterized in that, in the step of performing step B and step C at least twice, step B is performed each time When using a mixture of different metals and semiconductors doped with impurities as the target. 4. The fabrication method of the metal silicide thin film and the ultra-shallow junction according to claim 1, characterized in that, in the step B, the target is ionized into an ion state, so that metal ions and semiconductor doping impurities are produced ions, and apply a substrate bias on the semiconductor substrate. 5 . The method for fabricating metal silicide thin films and ultra-shallow junctions according to claim 4 , wherein the ionization of the target material into an ion state is realized by applying a first bias voltage to the target material. 6 . 6 . The method for fabricating metal silicide films and ultra-shallow junctions according to claim 5 , wherein the first bias voltage is any one of DC bias voltage, AC bias voltage or pulse bias voltage. 7 . The method for fabricating metal silicide films and ultra-shallow junctions according to claim 4 , wherein the substrate bias voltage is any one of DC bias voltage, AC bias voltage or pulse bias voltage. 8. The fabrication method of metal silicide film and ultra-shallow junction according to claim 1, characterized in that, in said step D, annealing is carried out by rapid thermal annealing; Or use microwave heating for annealing. 9. The method for making metal silicide thin films and ultra-shallow junctions according to claim 8, characterized in that, in the step of annealing by microwave heating, the cavity of the microwave heating equipment used for microwave heating annealing Multi-modal and multi-frequency electromagnetic waves are used for heating. 10. The method for making metal silicide films and ultra-shallow junctions according to claim 9, characterized in that, in the step of annealing by microwave heating, the frequency of the microwaves is between 1.5GHZ and 15GHZ; 1 to 30 minutes. 11. The method for making a metal silicide film and an ultra-shallow junction according to any one of claims 1 to 10, wherein the metal is any one of nickel, platinum, titanium, cobalt, molybdenum or their Alloys formed in any combination. 12. The method for fabricating metal silicide thin films and ultra-shallow junctions according to any one of claims 1 to 10, wherein the semiconductor doping impurities are boron B, boron fluoride BF ₂ , and indium Indium Any one or any combination of mixtures; Or any one of phosphorus and arsenic or a mixture of any combination. 13. The method for making a metal silicide film and an ultra-shallow junction according to any one of claims 1 to 10, characterized in that the content of semiconductor doping impurities in the mixture of metal and semiconductor doping impurities is 0.1% to 5%. 14. The method for fabricating metal silicide films and ultra-shallow junctions according to any one of claims 1 to 10, wherein the semiconductor substrate is silicon, germanium, silicon germanium, or III-V semiconductor. 15. The method for making a metal silicide film and an ultra-shallow junction according to any one of claims 1 to 10, characterized in that, in the step B, when the compound film is deposited on the semiconductor substrate The substrate temperature is 0 to 300°C. 16. The method for fabricating metal silicide films and ultra-shallow junctions according to any one of claims 1 to 10, characterized in that, in the step D, the annealing temperature is 300 to 800°C.