CN103018646A - High-temperature wafer level burn-in test scheduling method for SoC (system on a chip) chip - Google Patents

Abstract

The invention discloses a wafer-level high-temperature aging test scheduling method for SoC chips, using the high heat generated by the chips in the test mode to heat the chips, and taking the power consumption of circuit nodes as the guide, by selecting different temperature control capabilities Test vectors, control the application time of each test vector, thereby controlling the test temperature of the circuit module or SoC chip, and control the WLTBI test duration; by optimizing the circuit test path, arrange the transmission timing of test data on different test paths, thereby enhancing Test parallelism and reduce test time. According to the test requirements, the present invention can flexibly configure test schemes under the same test framework, so as to improve the accuracy of the aging test and reduce the test cost.

Description

A Wafer-Level High Temperature Aging Test Scheduling Method Oriented to SoC Chips

technical field

The invention relates to the technical field of integrated circuits, in particular to a wafer-level aging test method for integrated circuits.

Background technique

In order to make chip products go through the early failure stage of the "bathtub curve" of its failure rate before delivery to users, it is necessary to perform aging tests on chips. WLTBI (Wafer Level Test during Burn In) technology simultaneously performs chip fault coverage test (usually for fixed faults, Stuck-AtFaults) and burn-in test on the wafer surface, which has a significant effect on improving chip production yield and reducing chip cost. The International Technology Roadmap for Semiconductors (ITRS: International Technology Roadmap for Semiconductors) has listed it as one of the important development parties in today's chip testing technology. The chip packaging test after adopting WLTBI technology is significantly different from the traditional chip packaging test in terms of process. Moving the test link forward can greatly reduce unnecessary subsequent packaging costs, timely feedback on systematic problems in the previous process, and simplify the acquisition of multi-chip packaging. MCP: Multi Chip Package) or the KGD (Known Good Die) process required by the system chip package (SiP: System in Package) chip, so this technology has gained rapid development and application in recent years.

The implementation of WLTBI needs to use a specific test vector to stimulate the chip to complete a series of state transitions, which can be done in a variety of ways: (1) Use a specific metal layer as a test path, and remove this layer of metal in the subsequent process after the test task is completed. This method is called the sacrificial metal method (sacrificial metal method), which requires additional process support, and can only be adopted by IDM (Integrated Design and Manufacturing) companies such as Intel. (2) Directly use the probe to touch the pad of the chip under test, and apply test excitation. Its implementation requires doubling the number of probes in a common probe station (Prober) device and installing a temperature control system. (3) Based on the BIST (Built-In-Self Test) method, the BIST circuit and DfT (Design for Test) structure are embedded in the chip design to support fault coverage and burn-in test functions. The chip implementation of the pure BIST method has high cost, poor flexibility and low degree of standardization.

There is an underlying assumption in the general temperature aging test, that is, during the test, the temperature of all areas of the circuit under test (CUT: Circuit Under Test) is the same everywhere. Therefore, the main means of implementing the aging test is to control the ambient temperature of the CUT, which is usually achieved by means of an aging furnace. However, when the chip is actually working, the functional modules on the chip do not perform the same actions at the same time, the temperature distribution between different modules in the chip is not uniform, and even the temperature of each circuit node in the same circuit module is not the same, so The actual situation deviates from the above assumptions. The high-temperature aging failure of the chip is usually due to the local heat accumulation in the circuit too fast, and the temperature rises rapidly, resulting in the generation of "hot spots". That is to say, the local temperature inside the chip when the chip is working is the direct factor for the high temperature failure of the chip. Therefore, for high-temperature aging tests, it is more effective to create "hot spots" in the circuit than to simulate the ambient temperature.

Based on the multiplexed system chip (SoC: System on Chip) of silicon intellectual property (Silicon IP: Silicon Intellectual Property), the IP used may come from different IP suppliers, and the actual working temperature stress that each IP hard core can withstand Ranges may vary. When the ambient temperature is applied to the SoC chip, some IP reliability tests may be insufficient, and some IP may be subjected to excessive stress. Therefore, making different circuit modules in the SoC chip work at different test temperatures not only makes the burn-in test more in line with the actual working conditions of the chip, but also facilitates chip product quality classification (Binning) from the perspective of temperature stress test.

Contents of the invention

Aiming at wafer or wafer-level packaging, the present invention proposes a method for dispatching wafer-level high-temperature aging tests for SoC chips, which can achieve the purpose of improving the accuracy of aging tests and reducing test costs.

In order to solve the above-mentioned technical problems, the present invention utilizes the high heat generated by the chip in the test mode to heat the chip, and designs a test scheduling method targeting aging capability based on the power consumption of circuit nodes.

In this method, under the constraints of resource conflict, priority setting in the test program, and test power consumption limitation, the optimization goal is to maximize the controllability of the test temperature and minimize the test time during the test, and use a three-dimensional box-packing model to model (The model is shown in Figure 1), and a reasonable test scheduling is performed on the test vector set. By controlling the application time of each test vector, the test temperature of the circuit module or SoC chip is controlled, and the WLTBI test duration is controlled; by arranging the transmission timing of test data on different test paths, the test parallelism is enhanced and the test time is reduced. Its working principle is shown in Figure 2.

Based on the above test method, the present invention also provides a Wrapper/TAM (Test Access Mechanism) joint optimization design method of a SoC test structure, the test structure is shown in Figure 3. First, optimize the test shell of the IP core. By balancing the length of the scan chain in the Wrapper and uniforming the power consumption of the scan test, the test temperature of a single IP is controlled, the length of the longest scan chain is shortened, and the test time of a single IP core is reduced. On this basis, the TAM structure is optimized, and the optimal division of the test bus is approached through algorithm iteration, so as to control the test temperature of the entire SoC and shorten the test time of the SOC.

The whole design scheme can simulate the "hot spots" in the chip, apply different test temperatures to each circuit module in the SoC chip, improve the accuracy of the aging test, and minimize the impact of changing test power consumption on the expected calculation of the aging test temperature and time adverse effects, thereby obtaining a more accurate aging expected time, reducing test time, and reducing the cost of wafer-level testing.

The beneficial effect of the present invention is that: the traditional aging test technology based on the aging furnace adopts the electrothermal conversion method, the rated power of the aging test equipment is usually in the range of tens of KW, the energy consumption is high, and the energy conversion efficiency is low. The idea of the present invention is different from the general test method relying on the aging furnace. Through test scheduling, the appropriate test vector is selected and applied to the appropriate circuit module at the appropriate time to meet the requirements of SoC aging test in terms of temperature and time. The disadvantage of high test power consumption can improve the accuracy of aging test, save test cost, and reduce WLTBI's requirements for test equipment, which is in line with the spirit of green industry.

Description of drawings

Figure 1 is a three-dimensional packing model for test scheduling;

Figure 2 Schematic diagram of the working principle of aging test scheduling;

Figure 3 is a schematic diagram of the SoC test structure;

FIG. 4 is a schematic diagram of a TAM bus division scheme;

Fig. 5 is a schematic diagram of a test scheduling scheme.

Detailed ways

The needs of the present invention are implemented according to the following 4 steps:

first step:

Obtain information such as process documents, wafer material parameters, wafer layout and dimensions, burn-in test requirements, etc.

Step two:

Calculate the effect of different test input vectors on the power consumption and temperature control of the chip, and obtain the test vector sets corresponding to different temperature rise conditions.

Circuit power consumption P is mainly composed of dynamic power consumption and static power consumption.

The dynamic power consumption of the circuit is determined by formula (1):

P _dyn = 1/2·C·V ² ·N·f(1)

Among them, V is the operating voltage of the circuit, C is the load capacitance of the circuit, f is the operating frequency, and N is the number of circuit level jumps. After the circuit is completed, the circuit load capacitance C is basically unchanged, and parameters such as the circuit operating voltage V and the circuit operating frequency f can be adjusted within a certain range. The number of circuit level jumps within a period of time can be controlled by the test vector input by the circuit. control.

For circuits manufactured with a process above 90nm, the dynamic power consumption accounts for a large proportion of the total power consumption, and the static power consumption is negligible. Under the process conditions of 90nm and below, it is necessary to check the process file to obtain the static power consumption according to the gate circuit type used to form the test scan chain.

According to the dynamic power consumption and the static power consumption, the total power consumption of the circuit under the test vector input is obtained by summing.

The operating temperature of the circuit in test mode is determined by Equation (2):

Tj=Ta+P×Rja(2)

Where Ta is the ambient temperature, P is the power dissipation of the circuit, and Rja is the thermal resistance.

third step:

For specific aging temperature test requirements, optimize the design of the SoC test structure, and formulate the aging test scheduling plan (test vector sequence, working mode, duration, etc.).

For the SoC circuit, the test scheduling scheme design description in the present invention is as follows:

Assuming that the SoC chip has N circuit modules, it is required that the nth (1<=n<=N) module be continuously tested at a temperature Tn for a time tn. Suppose there are M modules adjacent to the nth module. Thermal diffusion will occur between adjacent modules, and the temperature rise caused by the thermal diffusion of module n to module m to module m is Tmn. The test vector set of IP core n is recorded as Vectorn, which contains K vectors, and the i-th one is recorded as Vectorni (1<=i<=K). Since the power consumption calculation method is known, the power consumption corresponding to Vectori can be calculated. Equation (1) is expanded in a cycle-accurate power consumption method and converted into a cycle temperature value. The temperature of module n in cycle j is:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; nj</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&theta;P</span>}}_{\mathrm{<span\; class="notranslate">\; nj</span>}}<span\; class="notranslate">\; +</span>\underset{\underset{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; \&NotEqual;</span>\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; nl</span>}}<span\; class="notranslate">\; -</span>\underset{\underset{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; \&NotEqual;</span>\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ln</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, the first item is the temperature of module n in the last cycle. The second item is the temperature rise after applying the test vector in this cycle, θ is the thermal resistance, and P _nj is the power consumption of module n in the circuit cycle j. The third term is the temperature contribution of adjacent modules to the thermal diffusion of module n. The fourth term is the temperature loss caused by the thermal diffusion of module n to adjacent modules. Since the power dissipation generated by each vector is known, the temperature rise per cycle can be calculated.

The definition of the problem according to the situation is as follows:

SoC single module aging test: The tested module n is continuously tested at the specified temperature Tn for the specified time tn. The scheduling problem can be formally defined as follows: Suppose module n is the module under test. In order to find that Vectorni belongs to Vectorn in each cycle, the temperature generated by it satisfies: min|Tnj-Tn|. Initially, the temperature of all modules is room temperature. When |Tnj-Tn|<δ, start counting and make it last for tn. δ is a very small value.

Multi-module parallel aging test: All modules under test are tested continuously for a specified time at a specified temperature. The scheduling problem can be formally defined as: In each cycle, find the test vector belonging to ∪Vectorn, 1<n<N, so that each The current temperature of IP satisfies: min|Tnj-Tn|, 1<n<N. For each IP core, start timing when |Tnj-Tn|<δ, so that it lasts for tn.

the fourth step:

Dynamic test vectors are imposed according to the burn-in test schedule.

The implementation example of aging test scheduling is as follows:

P_i和P_i+1分别表示在第i和第i+1个时钟周期的测试功耗开销。Definition: T _SoC represents the test time of the SoC in the entire clock cycle, P _mean represents the average power consumption overhead of the test clock cycle, P _max represents the maximum test power consumption peak value of the SoC, TS _i represents the i-th group of cores tested at the same time set. In order to be able to control the test temperature, it is necessary to obtain a smooth test power consumption curve, we define the smoothness of the test power consumption curve:

P _i and P _i+1 represent the test power consumption overhead of the ith clock cycle and the i+1th clock cycle respectively.

最小化。In order to be able to control the test temperature of the entire SoC, we control the test temperature by controlling the test power variation difference, so the objective function is defined: SoC test power variation difference

minimize.

Burn-in test scheduling problem description: It is known that there are N IP cores on the SoC, and the sum of the TAM widths of Group B is W. Find the core set selection scheme that can be tested at the same time, the division of the TAM test bus, and the distribution of each IP core on each bus. The allocation scheme and test sequence make the test power consumption variation difference of the entire SoC the smallest under the constraint condition of not exceeding the maximum power consumption peak value P _max .

Considering the D695ITC'02SoC benchmark circuit with a TAM line width of 32, the TAM bus is divided into 3 groups (as shown in Figure 4), and the test scheduling optimization scheme (as shown in Figure 5), as can be seen from Figure 5, while testing the core set selection The scheme is: TS ₁ ={3,1,4}, TS ₂ ={7,2,6}, Ts ₃ ={5,8}, TS ₄ ={9}, TS ₅ ={10}.

To sum up, the aging test scheduling method provided by the present invention does not add any new hardware overhead, only by optimizing the internal test structure of the circuit, and then solving an optimized and reasonable aging test scheduling scheme through intelligent algorithm scheduling, using the original structure of the circuit The aging test efficiency can be effectively improved, the test time is greatly shortened, and the accuracy of the aging test is improved.

The foregoing embodiments are only examples of the present invention. Although the best embodiment of the present invention and accompanying drawings are disclosed for illustrative purposes, those skilled in the art can understand that: without departing from the spirit and scope of the present invention and the appended claims Inside, various substitutions, changes and modifications are possible. Therefore, the present invention should not be limited to what is disclosed in the preferred embodiments and drawings.

Claims (4)

1. A wafer-level high-temperature aging test scheduling method for SoC chips, characterized in that, comprising: (1) By selecting test vectors with different temperature control capabilities, the application time of each test vector is controlled, thereby controlling the test temperature of the circuit module or SoC chip, and controlling the WLTBI test duration. (2) By optimizing the circuit test structure, arrange the sending timing of test data on different test paths, thereby enhancing test parallelism and reducing test time. (3) Based on the test scheduling scheme of the three-dimensional packing model, the intelligent algorithm is used for scheduling optimization. 2. The burn-in test scheduling method according to claim 1, wherein the test vectors of different temperature control capabilities include: when the temperature rise generated by the scan chain is equal to the temperature lost by the chip heat sink, the burn-in temperature is constant constant. When the temperature rise generated by the scan chain is greater than the temperature lost by the chip heat sink, the aging temperature rises, otherwise, the aging temperature decreases. According to the temperature control requirements in the aging test scheme (such as constant high temperature test, temperature cycle test, etc.), design the test vector and test input waveform. Different temperature control requirements form different test vectors. 3. The burn-in test scheduling method according to claim 1, wherein said circuit test structure optimization comprises: (1) First, optimize the test shell of the IP core. By balancing the length of the scan chain in the Wrapper and uniforming the power consumption of the scan test, the test temperature of a single IP is controlled, the length of the longest scan chain is shortened, and the test of a single IP core is reduced. time. (2) On this basis, the TAM structure is optimized, and the optimal division of the test bus is approached iteratively through an intelligent algorithm, thereby controlling the test temperature of the entire SoC and shortening the SOC test time. 4. the burn-in test scheduling method as claimed in claim 1, is characterized in that, the test scheduling scheme based on three-dimensional packing model comprises: setting TAM bus width and test temperature are the inherent constraints of SoC chip, and TAM width , test temperature and test time are regarded as three dimensions respectively. The goal of test scheduling process optimization is to put all the small boxes into the big box, the test temperature change is even and controllable, and the total length of the small boxes in the test time dimension is the smallest , without exceeding the size constraints of the large box.

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