CN103018558B

CN103018558B - Master-slave multiprocessor real-time signal analyzing method

Info

Publication number: CN103018558B
Application number: CN201210504908.7A
Authority: CN
Inventors: 储昭碧; 冯小英; 丁明
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2012-11-30
Filing date: 2012-11-30
Publication date: 2015-03-11
Anticipated expiration: 2032-11-30
Also published as: CN103018558A

Abstract

The invention discloses a master-slave multi-processor real-time signal analysis method, which adopts a master processor and N slave processors to execute; wherein, the master processor uses T seconds as the sampling period to regularly sample the measured signal and Obtain the sampling data, and use the iterative method to obtain the DC component x ₀ ; in the N slave processors, set the value of a positive integer K, and set the values of N×K frequencies to increase sequentially and not greater than 2π/T Positive numbers ω ₁₁ , ω ₁₂ , ..., ω _1K , ω ₂₁ , ..., ω _NK , using an iterative method to obtain N×K AC components x ₁₁ , x ₁₂ , ..., x _1K , x ₂₁ , ..., x _NK , N×K orthogonal components z ₁₁ , z ₁₂ ,…, z _1K , z ₂₁ ,…, z _NK , and calculate N×K estimated amplitudes a ₁₁ , a ₁₂ ,…, a _1K , a ₂₁ ,… , a _NK . The algorithm structure of the master-slave multiprocessor real-time signal analysis method of the present invention is relatively simple, the calculation amount is relatively small, and the running time is relatively short.

Description

Master-slave multiprocessor real-time signal analysis method

技术领域technical field

本发明属于信号分析技术领域，具体涉及一种采用一个主处理器与多个从处理器，把信号实时分解为直流分量与指定频率的多个交流分量，并获得每个交流分量的正交分量和幅值的信号分析方法。The invention belongs to the technical field of signal analysis, and specifically relates to a method of using a main processor and multiple slave processors to decompose a signal into a DC component and multiple AC components of a specified frequency in real time, and obtain an orthogonal component of each AC component. and amplitude signal analysis methods.

背景技术Background technique

在工程中，经常需要把电压、电流、声音、振动等信号实时分解为直流分量与指定频率的多个交流分量，并计算直流分量的数值与各个交流分量的幅值，例如电力系统的谐波与间谐波分析以及机械振动的振动分量分析等。In engineering, it is often necessary to decompose signals such as voltage, current, sound, and vibration into DC components and multiple AC components of specified frequencies in real time, and calculate the value of the DC component and the amplitude of each AC component, such as the harmonics of the power system Interharmonic analysis and vibration component analysis of mechanical vibration, etc.

为此，现有技术中已经提出了几种信号分析方法，虽获得较好效果，但还存在一些不足，例如：For this reason, several signal analysis methods have been proposed in the prior art. Although good results are obtained, there are still some deficiencies, such as:

采用单处理器的信号分析方法，受处理器运算速度限制，数据处理时间和采样周期长，交流分量个数受限，实时分析性能难以提高；The single-processor signal analysis method is limited by the operation speed of the processor, the data processing time and sampling cycle are long, the number of AC components is limited, and the real-time analysis performance is difficult to improve;

基于递推傅里叶变换的信号分析方法，需要保存一个完整周期内的全部采样数据，并且需要计算正弦函数和余弦函数；The signal analysis method based on recursive Fourier transform needs to save all the sampling data in a complete cycle, and needs to calculate the sine function and cosine function;

基于微分方程形式的针对连续时间信号的信号分析方法，不能直接应用于计算机系统中。The signal analysis method for continuous time signals based on differential equations cannot be directly applied to computer systems.

采用一阶无限冲激响应（IIR）算法的方法，每次迭代的运行时间可能不相等，难以确定定时采样周期的数值。With the method of the first-order infinite impulse response (IIR) algorithm, the running time of each iteration may not be equal, and it is difficult to determine the value of the timing sampling period.

发明内容Contents of the invention

本发明的目的是提供一种算法结构相对简单、运算量相对小、运行时间相对短的信号分析方法。The purpose of the present invention is to provide a signal analysis method with relatively simple algorithm structure, relatively small calculation amount and relatively short running time.

为了实现上述目的，本发明提供了一种主从式多处理器实时信号分析方法，采用一个主处理器与N个从处理器执行；其中，主处理器以T秒为采样周期，定时对被测信号进行采样并获得采样数据，并利用迭代方法获得直流分量x₀；在N个从处理器中，设定正整数K的值，设定N×K个频率的数值为依次递增且均不大于2π/T的正数ω₁₁、ω₁₂、…、ω_1K、ω₂₁、…、ω_NK，利用迭代方法获得N×K个交流分量x₁₁、x₁₂、…、x_1K、x₂₁、…、x_NK，N×K个正交分量z₁₁、z₁₂、…、z_1K、z₂₁、…、z_NK，并计算N×K个估计幅值a₁₁、a₁₂、…、a_1K、a₂₁、…、a_NK。In order to achieve the above object, the present invention provides a master-slave multiprocessor real-time signal analysis method, which adopts a master processor and N slave processors to execute; The measured signal is sampled and the sampled data is obtained, and the DC component x ₀ is obtained by an iterative method; in the N slave processors, the value of a positive integer K is set, and the values of N×K frequencies are set to increase sequentially and not Positive numbers greater than 2π/T ω ₁₁ , ω ₁₂ , ..., ω _1K , ω ₂₁ , ..., ω _NK , using an iterative method to obtain N×K AC components x ₁₁ , x ₁₂ , ..., x _1K , x ₂₁ , ..., x _NK , N×K orthogonal components z ₁₁ , z ₁₂ , ..., z _1K , z ₂₁ , ..., z _NK , and calculate N×K estimated amplitudes a ₁₁ , a ₁₂ , ..., a _1K , a ₂₁ , ..., a _NK .

作为优选，针对所述被测信号的每个采样数据u[s]，按照下述第一处理方案和第二处理方案中的一种执行，连续的两个采样数据分别执行不同的处理方案；其中μ为不大于2π/T的正数，从处理器序号n分别取值为1,2，…,N；Preferably, each sampling data u[s] of the signal under test is executed according to one of the following first processing scheme and second processing scheme, and two consecutive sampling data are respectively executed with different processing schemes; Among them, μ is a positive number not greater than 2π/T, and the values from the processor serial number n are 1, 2, ..., N respectively;

第一处理方案依次包括以下步骤：The first treatment plan includes the following steps in turn:

S101：主处理器按式(1)计算直流分量增量h₀[2]的值，并发送该值到全部从处理器；S101: The master processor calculates the value of the DC component increment h ₀ [2] according to formula (1), and sends the value to all slave processors;

${h h}_{00} [[22]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + T T \cdot &Center Dot; {h h}_{00} [[11]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[11]])) - - - - - - ((11))$

第n个从处理器获得直流分量增量h₀[2]的值，把中间变量d_n[2]清零后，令k分别取值为1,2，…,K，循环执行式(2)，依次得到交流分量增量h_nk[2]、正交分量增量g_nk[2]和d_n[2]的值；The nth slave processor obtains the value of the DC component increment h ₀ [2], and after clearing the intermediate variable d _n [2], let k take the value of 1, 2, ..., K respectively, and execute the formula (2 ), and obtain the values of AC component increment h _nk [2], quadrature component increment g _nk [2] and d _n [2] in turn;

$\{\begin{matrix} {h h}_{nk nk} [[22]] = = {h h}_{00} [[22]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + T T \cdot &Center Dot; {g g}_{nk nk} [[11]])) \\ {g g}_{nk nk} [[22]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[11]])) \\ {d d}_{n no} [[22]] &LeftArrow; &LeftArrow; {d d}_{n no} [[22]] + + (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[22]])) \end{matrix} - - - - - - ((22))$

S102：主处理器读取中间变量d₁[2]、d₂[2]、…、d_N[2]的值；S102: the main processor reads the values of the intermediate variables d ₁ [2], d ₂ [2], ..., d _N [2];

S103：主处理器按式(3)计算直流分量增量h₀[3]的值，并发送该值到全部从处理器；S103: the master processor calculates the value of the DC component increment h ₀ [3] according to formula (3), and sends the value to all slave processors;

${h h}_{00} [[33]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + T T \cdot \cdot {h h}_{00} [[22]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[22]])) - - - - - - ((33))$

第n个从处理器获得直流分量增量h₀[3]的值，把中间变量d_n[3]清零后，令k分别取值为1,2，…,K，循环执行式(4)，依次得到交流分量增量h_nk[3]、正交分量增量g_nk[3]和d_n[3]的值；The nth slave processor obtains the value of the DC component increment h ₀ [3], and after clearing the intermediate variable d _n [3], let k take the value of 1, 2, ..., K respectively, and execute the formula (4 ) to obtain the values of AC component increment h _nk [3], quadrature component increment g _nk [3] and d _n [3] in turn;

$\{\begin{matrix} {h h}_{nk nk} [[33]] = = {h h}_{00} [[33]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + T T \cdot &Center Dot; {g g}_{nk nk} [[22]])) \\ {g g}_{nk nk} [[33]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[22]])) \\ {d d}_{n no} [[33]] &LeftArrow; &LeftArrow; {d d}_{n no} [[33]] + + (({x x}_{nk nk} + + 22 T T \cdot &Center Dot; {h h}_{nk nk} [[33]])) \end{matrix} - - - - - - ((44))$

S104：主处理器读取中间变量d₁[3]、d₂[3]、…、d_N[3]的值；S104: the main processor reads the values of the intermediate variables d ₁ [3], d ₂ [3], ..., d _N [3];

第二处理方案依次包括以下步骤：The second treatment plan includes the following steps in turn:

S201：主处理器按式(5)先计算直流分量增量h₀[4]的值，再进行迭代获得直流分量x₀的值，并发送该值到全部从处理器；S201: The main processor first calculates the value of the DC component increment h ₀ [4] according to the formula (5), and then iterates to obtain the value of the DC component x ₀ , and sends this value to all the slave processors;

$\{\begin{matrix} {h h}_{00} [[44]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + 22 T T \cdot &Center Dot; {h h}_{00} [[33]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[33]])) \\ {x x}_{00} &LeftArrow; &LeftArrow; {x x}_{00} + + \frac{T T}{33} (({h h}_{00} [[44]] + + 22 {h h}_{00} [[33]] + + 22 {h h}_{00} [[22]] + + {h h}_{00} [[11]])) \end{matrix} - - - - - - ((55))$

第n个从处理器获得直流分量增量h₀[4]的值，把中间变量d_n[4]清零，令k分别取值为1,2，…,K，循环执行式(6)，先计算交流分量增量h_nk[4]和正交分量增量g_nk[4]的值，再进行迭代获得交流分量x_nk、正交分量z_nk和d_n[4]的值，依据迭代后的交流分量x_nk和正交分量z_nk计算得到估计幅值a_nk的值；The nth slave processor obtains the value of the DC component increment h ₀ [4], clears the intermediate variable d _n [4], sets k to be 1, 2, ..., K, and executes formula (6) in a loop , first calculate the values of AC component increment h _nk [4] and quadrature component increment g _nk [4], and then iteratively obtain the values of AC component x _nk , quadrature component z _nk and d _n [4], according to The value of the estimated amplitude a _nk is obtained by calculating the AC component x _nk and the quadrature component z _nk after iteration;

$\{\begin{matrix} {h h}_{nk nk} [[44]] = = {h h}_{00} [[44]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + 22 T T \cdot &Center Dot; {g g}_{nk nk} [[33]])) \\ {g g}_{nk nk} [[44]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + 22 T T \cdot &Center Dot; {h h}_{nk nk} [[33]])) \\ {x x}_{nk nk} &LeftArrow; &LeftArrow; {x x}_{nk nk} + + \frac{T T}{33} (({h h}_{nk nk} [[44]] + + 22 {h h}_{nk nk} [[33]] + + 22 {h h}_{nk nk} [[22]] + + {h h}_{nk nk} [[11]])) \\ {z z}_{nk nk} &LeftArrow; &LeftArrow; {z z}_{nk nk} + + \frac{T T}{33} (({g g}_{nk nk} [[44]] + + 22 {g g}_{nk nk} [[33]] + + 22 {g g}_{nk nk} [[22]] + + {g g}_{nk nk} [[11]])) \\ {d d}_{n no} [[44]] &LeftArrow; &LeftArrow; {d d}_{n no} [[44]] + + {x x}_{nk nk} \\ {a a}_{nk nk} = = \sqrt{{x x}_{nk nk}^{22} + + {z z}_{nk nk}^{22}} \end{matrix} - - - - - - ((66))$

S202：主处理器读取中间变量d₁[4]、d₂[4]、…、d_N[4]的值；S202: the main processor reads the values of the intermediate variables d ₁ [4], d ₂ [4], ..., d _N [4];

S203：主处理器按式(7)计算直流分量增量h₀[1]的值，并发送该值到全部从处理器；S203: The master processor calculates the value of the DC component increment h ₀ [1] according to formula (7), and sends the value to all slave processors;

${h h}_{00} [[11]] = = μ μ ((u u [[s the s]] - - {x x}_{00} - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[44]])) - - - - - - ((77))$

第n个从处理器获得直流分量增量h₀[1]的值，把中间变量d_n[1]清零后，令k分别取值为1,2，…,K，循环执行式(8)，依次获得交流分量增量h_nk[1]、正交分量增量g_nk[1]和d_n[1]的值；The nth slave processor obtains the value of the DC component increment h ₀ [1], and after clearing the intermediate variable d _n [1], let k take the value of 1, 2, ..., K respectively, and execute the formula (8 ), sequentially obtain the values of AC component increment h _nk [1], quadrature component increment g _nk [1] and d _n [1];

$\{\begin{matrix} {h h}_{nk nk} [[11]] = = {h h}_{00} [[11]] + + {ω ω}_{nk nk} \cdot &Center Dot; {z z}_{nk nk} \\ {g g}_{nk nk} [[11]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; {x x}_{nk nk} \\ {d d}_{n no} [[11]] &LeftArrow; &LeftArrow; {d d}_{n no} [[11]] + + (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[11]])) \end{matrix} - - - - - - ((88))$

S204：主处理器读取中间变量d₁[1]、d₂[1]、…、d_N[1]的值。S204: The main processor reads the values of the intermediate variables d ₁ [1], d ₂ [1], . . . , d _N [1].

作为进一步地优选，具体包括以下步骤：As further preferably, specifically comprising the following steps:

S1：参数设定：S1: Parameter setting:

主处理器设定采样周期T、正数μ、从处理器个数N的值，The master processor sets the value of the sampling period T, the positive number μ, and the number of slave processors N,

第n个从处理器设定采样周期T、频率个数K、递增的频率数值ω_n1、ω_n2、…、ω_nK；The nth slave processor sets the sampling period T, the number of frequencies K, and the incremented frequency values ω _n1 , ω _n2 ,..., ω _nK ;

S2：变量初始化：S2: Variable initialization:

主处理器设定直流分量x₀、直流分量增量h₀[1]以及中间变量d₁[1]、d₂[1]、…、d_N[1]的初值，设定标志字初值为执行第一处理方案，依据采样周期T设置定时间隔并开始定时，The main processor sets the initial value of the DC component x ₀ , the DC component increment h ₀ [1], and the intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1], and sets the initial value of the flag word The value is to execute the first processing scheme, set the timing interval according to the sampling period T and start timing,

第n个从处理器设定交流分量x_n1、x_n2、…、x_nK，正交分量z_n1、z_n2、…、z_nK，交流分量增量h_n1[1]、h_n2[1]、…、h_nK[1]和正交分量增量g_n1[1]、g_n2[1]、…、g_nK[1]的初值；The nth slave processor sets AC components x _n1 , x _n2 , ..., x _nK , quadrature components z _n1 , z _n2 , ..., z _nK , and AC component increments h _n1 [1], h _n2 [1] , ..., h _nK [1] and the initial value of the quadrature component increment g _n1 [1], g _n2 [1], ..., g _nK [1];

S3：实时分析：S3: Real-time analysis:

在定时采样时刻，主处理器获得采样数据u[s]后，依据标志字的值，执行第一处理方案或者执行第二处理方案，获得直流分量x₀的值，然后修改标志字的值为对应另一种处理方案，At the time of timing sampling, after the main processor obtains the sampling data u[s], it executes the first processing plan or the second processing plan according to the value of the flag word to obtain the value of the DC component x ₀ , and then modifies the value of the flag word to be Corresponding to another treatment scheme,

第n个从处理器在主处理器的控制下，对应地执行第一处理方案或者第二处理方案规定的操作，获得各个交流分量x_n1、x_n2、…、x_nK、正交分量z_n1、z_n2、…、z_nK、估计幅值a_n1、a_n2、…、a_nK的值；Under the control of the master processor, the nth slave processor correspondingly executes the operations prescribed by the first processing scheme or the second processing scheme, and obtains each AC component x _n1 , x _n2 , ..., x _nK , and orthogonal component z _n1 , z _n2 , ..., z _nK , estimated amplitudes a _n1 , a _n2 , ..., a _nK values;

S4：循环执行：S4: Loop execution:

当采样周期T定时时间到，返回步骤S3循环执行。When the timing of the sampling period T expires, return to step S3 for cyclic execution.

与现有技术相比，本发明具有以下有益效果：Compared with the prior art, the present invention has the following beneficial effects:

1、本发明采用多个处理器并行工作，由于主处理器与从处理器之间交换数据所需要的时间，远小于从处理器执行第一方案或第二处理方案的时间，整个系统的数据处理时间大为减少，有效减小采样周期，提高实时信号分析性能；1, the present invention adopts a plurality of processors to work in parallel, because the time required for exchanging data between the main processor and the slave processor is far less than the time for the slave processor to execute the first scheme or the second processing scheme, the data of the whole system The processing time is greatly reduced, the sampling period is effectively reduced, and the real-time signal analysis performance is improved;

2、本发明以迭代方法直接得到直流分量、交流分量和正交分量，不需要计算正弦函数和余弦函数，结构简单、运算量小，可消除信号的直流分量对计算交流分量及其幅值的不良影响，拓宽了应用范围，便于利用计算机实现；2. The present invention directly obtains the DC component, the AC component and the quadrature component by an iterative method, does not need to calculate the sine function and the cosine function, has a simple structure and a small amount of calculation, and can eliminate the influence of the DC component of the signal on the calculation of the AC component and its amplitude. Adverse effects, broaden the scope of application, easy to use computer to realize;

3、本发明采用四阶有限脉冲响应算法，具有四阶精度和四阶收敛速度，较无限冲击响应算法更加易于实现，比一阶有限脉冲响应算法具有更高的精度和更快的收敛速度；3. The present invention adopts the fourth-order finite impulse response algorithm, which has fourth-order precision and fourth-order convergence speed, is easier to implement than the infinite impulse response algorithm, and has higher precision and faster convergence speed than the first-order finite impulse response algorithm;

4、本发明不要求所指定的交流分量的频率在数值上保持特定关系，便于分析被测信号的谐波或间谐波成分。4. The present invention does not require the frequency of the specified AC component to maintain a specific relationship in value, which is convenient for analyzing the harmonic or inter-harmonic components of the measured signal.

附图说明Description of drawings

图1为本发明的信号分析方法中采用的主处理器和从处理器的一种连接关系图；Fig. 1 is a kind of connection diagram of master processor and slave processor adopted in the signal analysis method of the present invention;

图2为本发明的信号分析方法中采用的主处理器和从处理器的又一种连接关系图；Fig. 2 is another connection diagram of the main processor and the slave processor adopted in the signal analysis method of the present invention;

图3为本发明的信号分析方法中主处理器的工作流程示意图；Fig. 3 is the workflow schematic diagram of main processor in the signal analysis method of the present invention;

图4为本发明的信号分析方法中从处理器的工作流程示意图。FIG. 4 is a schematic diagram of the workflow of the slave processor in the signal analysis method of the present invention.

具体实施方式Detailed ways

下面结合附图对本发明的具体实施例进行详细说明，本发明的信号分析方法可应用于分析电力系统的谐波与间谐波以及分析机械振动的不同频率的振动分量。Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The signal analysis method of the present invention can be applied to analyze harmonics and inter-harmonics of a power system and vibration components of different frequencies of mechanical vibration.

图1为本发明的信号分析方法中采用的主处理器和从处理器的一种连接关系图，如图1所示，主处理器和N个从处理器通过同步串行接口（SPI）进行通信。时钟信号SCK、数据输出SDO和数据输入SDI组成SPI接口。主处理器的信号S0~Sm经过译码后，控制各个从处理器的片选信号CS。N个从处理器的状态信号STS都采用集电极开路输出，按照“线与”的方式，连接到主处理器的STS输入端，主处理器据此判断是否读取从处理器的数据。Fig. 1 is a kind of connection diagram of master processor and slave processor adopted in the signal analysis method of the present invention, as shown in Fig. 1, master processor and N slave processors are carried out through synchronous serial interface (SPI) communication. Clock signal SCK, data output SDO and data input SDI form the SPI interface. After the signals S0~Sm of the main processor are decoded, they control the chip select signal CS of each slave processor. The status signals STS of the N slave processors are all output with open collectors, and are connected to the STS input of the main processor in a "wired-AND" manner, and the main processor judges whether to read the data of the slave processor based on this.

图2为本发明的信号分析方法中采用的主处理器和从处理器的又一种连接关系图，如图2所示，主处理器和N个从处理器通过并行接口进行通信。并行数据信号D0~D7、读信号RD、写信号WR组成并行接口。各个从处理器的状态信号STS经由缓冲器，并行接入主处理器的数据信号D0~D7，供主处理器查询。主处理器的地址信号A0~Am经过译码后，控制各个从处理器以及缓冲器的片选信号CS。FIG. 2 is another connection diagram of the main processor and the slave processors adopted in the signal analysis method of the present invention. As shown in FIG. 2 , the main processor communicates with N slave processors through parallel interfaces. Parallel data signals D0~D7, read signal RD, and write signal WR form a parallel interface. The status signal STS of each slave processor is connected to the data signals D0~D7 of the master processor in parallel via the buffer for query by the master processor. After decoding, the address signals A0~Am of the main processor control the chip select signal CS of each slave processor and buffer.

采用上述两种连接关系的主处理器和从处理器进行信号分析时，被测信号经过检测和调理电路处理，再经模数转换器的采样和量化后送至主处理器。从处理器的状态信号STS=1表示从处理器的数据处理过程没有开始或正在进行，STS=0表示数据处理过程结束，主处理器可以读取该从处理器当前计算的中间变量。SPI接口中断或者并行接口的读写操作中断构成数据处理中断，从处理器在数据处理中断步骤中进行数据计算与交换。When the main processor and the slave processor of the above two connection relations are used for signal analysis, the measured signal is processed by the detection and conditioning circuit, and then sent to the main processor after being sampled and quantized by the analog-to-digital converter. The status signal STS=1 of the slave processor indicates that the data processing process of the slave processor has not started or is in progress, and STS=0 indicates the end of the data processing process, and the master processor can read the intermediate variable currently calculated by the slave processor. The SPI interface interrupt or the read and write operation interrupt of the parallel interface constitutes a data processing interrupt, and the slave processor performs data calculation and exchange in the data processing interrupt step.

图3为本发明的信号分析方法中主处理器的工作流程示意图，如图3所示，主处理器的工作流程包括主步骤（a）和定时中断步骤（b）。FIG. 3 is a schematic diagram of the workflow of the main processor in the signal analysis method of the present invention. As shown in FIG. 3 , the workflow of the main processor includes a main step (a) and a timing interrupt step (b).

图4为本发明的信号分析方法中从处理器的工作流程示意图，如图4所示，各个从处理器的工作流程分别包括主步骤（a）和数据处理中断步骤（b）。Fig. 4 is a schematic diagram of the workflow of the slave processor in the signal analysis method of the present invention. As shown in Fig. 4, the workflow of each slave processor includes a main step (a) and a data processing interruption step (b).

如图3和图4所示，本发明的主从式多处理器实时信号分析方法依次包括以下步骤：As shown in Fig. 3 and Fig. 4, master-slave multiprocessor real-time signal analysis method of the present invention comprises the following steps successively:

S1：参数设定：S1: Parameter setting:

第n个从处理器设定采样周期T、频率个数K、递增的频率数值ω_n1、ω_n2、…、ω_nK（以弧度/秒为单位）；The nth slave processor sets the sampling period T, the number of frequencies K, and the incremented frequency values ω _n1 , ω _n2 , ..., ω _nK (in radians/second);

S2：变量初始化：S2: Variable initialization:

主处理器设定直流分量x₀、直流分量增量h₀[1]以及中间变量d₁[1]、d₂[1]、…、d_N[1]的初值，设定标志字初值为执行第一处理方案（将在下文中进行详细说明），依据采样周期T设置定时间隔并开始定时，The main processor sets the initial value of the DC component x ₀ , the DC component increment h ₀ [1], and the intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1], and sets the initial value of the flag word The value is to execute the first processing scheme (will be described in detail below), set the timing interval according to the sampling period T and start timing,

S3：实时分析：S3: Real-time analysis:

在定时采样时刻，主处理器获得采样数据u[s]后，依据标志字的值，执行第一处理方案或者执行第二处理方案（将在下文中进行详细说明），获得直流分量x₀的值，然后修改标志字的值为对应另一种处理方案，At the regular sampling time, after the main processor obtains the sampled data u[s], it executes the first processing scheme or the second processing scheme (will be described in detail below) according to the value of the flag word to obtain the value of the DC component x ₀ , and then modify the value of the flag word to correspond to another processing scheme,

S4：循环执行：S4: Loop execution:

如图3所示，在主处理器的主步骤中，依次对参数进行了设定（即步骤S1），包括：设定采样周期T、参数μ和从处理器个数N的值；设定包括直流分量x₀、直流分量增量h₀[1]以及中间变量d₁[1]、d₂[1]、…、d_N[1]的初值；设定标志字FLAG初值为执行第一处理方案的数值1；依据采样周期T设置定时器的定时间隔（等于采样周期T）并开始定时，并开放定时中断。As shown in Figure 3, in the main step of the main processor, the parameters are set in turn (that is, step S1), including: setting the value of the sampling period T, parameter μ and the number of slave processors N; setting Including the initial value of DC component x ₀ , DC component increment h ₀ [1] and intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1]; set the initial value of the flag word FLAG to execute The value of the first processing scheme is 1; according to the sampling period T, set the timing interval of the timer (equal to the sampling period T) and start timing, and open the timing interrupt.

如图4所示，在第n个从处理器的主步骤中，依次对各个变量进行了初始化（即步骤S2），包括：设定采样周期T、频率个数K以及递增的频率数值ω_n1、ω_n2、…、ω_nK的值；设定包括交流分量x_n1、x_n2、…、x_nK，正交分量z_n1、z_n2、…、z_nK，交流分量增量h_n1[1]、h_n2[1]、…、h_nK[1]和正交分量增量g_n1[1]、g_n2[1]、…、g_nK[1]的初值；设定状态信号STS的初值为1，开放进行数据交换的SPI接口中断或者并行接口读写中断。As shown in Figure 4, in the main step of the nth slave processor, each variable is initialized in turn (that is, step S2), including: setting the sampling period T, the number of frequencies K, and the incremented frequency value ω _n1 , ω _n2 ,..., ω _nK values; setting includes AC components x _n1 , x _n2 , ..., x _nK , quadrature components z _n1 , z _n2 , ..., z _nK , AC component increment h _n1 [1] , h _n2 [1], ..., h _nK [1] and the initial value of the quadrature component increment g _n1 [1], g _n2 [1], ..., g _nK [1]; set the initial value of the state signal STS When the value is 1, the SPI interface interrupt for data exchange or the parallel interface read and write interrupt are opened.

步骤S3的实时分析功能由主处理器的定时中断步骤与从处理器的数据处理中断步骤共同实现。The real-time analysis function of step S3 is realized jointly by the timing interruption step of the master processor and the data processing interruption step of the slave processor.

如图3所示，在主处理器的定时中断步骤中，在保存中断现场数据之后，先对被测信号进行采样获得采样数据u[s]；再依据标志字FLAG的值等于1还是0，分别执行第一处理方案和第二处理方案，获得直流分量x₀的值；然后对标志字FLAG进行逻辑取反运算，使下次中断执行另外一种处理方案；最后恢复中断现场数据，中断返回到主步骤执行。As shown in Figure 3, in the timing interrupt step of the main processor, after saving the interrupt field data, the measured signal is first sampled to obtain the sampling data u[s]; then according to whether the value of the flag word FLAG is equal to 1 or 0, Execute the first processing plan and the second processing plan respectively to obtain the value of the DC component x ₀ ; then perform logical inversion operation on the flag word FLAG, so that the next interrupt executes another processing plan; finally restore the interrupted field data, and return from the interrupt to the main step for execution.

主处理器对从处理器的读写操作都引起从处理器的数据处理中断，如图4所示，在数据处理中断步骤中，第n个从处理器在保存中断现场数据之后，依据自身的状态信号STS的值，判断是向主处理器发送数据还是从主处理器接收数据；如果STS=0则是发送数据，依次把中间变量d_n[1]或d_n[2]或d_n[3]或d_n[4]的各个字节传送到数据交换接口，供主处理器读取，然后把状态信号STS置1；如果STS=1，则读取并判断主处理器发送来的数据，如果主处理器发送来的数据是h₀[1]、h₀[2]、h₀[3]，就相应地分别计算h_nk[1]、g_nk[1]和d_n[1]、h_nk[2]、d_nk[2]和d_n[2]、h_nk[3]、g_nk[3]和d_n[3]的值，如果主处理器发送来的数据是h₀[4]，就在计算h_nk[4]、g_nk[4]之后，迭代处理交流分量x_nk、正交分量z_nk和d_n[4]，并计算估计幅值a_nk；然后，清零状态信号STS，通知主处理器读取数据；不论是读取还是发送数据，最后均恢复中断现场数据，中断返回到主步骤执行。The read and write operations of the master processor to the slave processor all cause the data processing interruption of the slave processor. The value of the state signal STS determines whether to send data to the main processor or receive data from the main processor; if STS=0, it is sending data, and the intermediate variable d _n [1] or d _n [2] or d _n [ 3] or each byte of d _n [4] is transmitted to the data exchange interface for the main processor to read, and then set the status signal STS to 1; if STS=1, read and judge the data sent by the main processor , if the data sent by the main processor is h ₀ [1], h ₀ [2], h ₀ [3], calculate h _nk [1], g _nk [1] and d _n [1] accordingly , h _nk [2], d _nk [2] and d _n [2], h _nk [3], g _nk [3] and d _n [3] values, if the data sent by the host processor is h ₀ [4], just after calculating h _nk [4], g _nk [4], iteratively process the AC component x _nk , the quadrature component z _nk and d _n [4], and calculate the estimated amplitude a _nk ; then, clear The zero state signal STS informs the main processor to read data; whether it is reading or sending data, the interrupted field data is finally restored, and the interrupt returns to the main step for execution.

下面对前述的第一处理方案和第二处理方案进行详细说明。The aforementioned first treatment scheme and second treatment scheme will be described in detail below.

第一处理方案依次包括：The first treatment plan includes in order:

S101：主处理器按式(1)计算直流分量增量h₀[2]的值，并按序号n从小到大的顺序发送h₀[2]值到全部从处理器；S101: The master processor calculates the value of the DC component increment h ₀ [2] according to formula (1), and sends the value of h ₀ [2] to all slave processors in order of sequence number n from small to large;

${h h}_{00} [[22]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + T T \cdot \cdot {h h}_{00} [[11]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[11]])) - - - - - - ((11))$

第n个从处理器在数据处理中断步骤中，读取主处理器发送来的数据，并判断为直流分量增量h₀[2]的值，把中间变量d_n[2]清零后，令k分别取值为1,2，…,K，循环执行式(2)，依次得到交流分量增量h_nk[2]、正交分量增量g_nk[2]和d_n[2]的值，然后清零状态信号STS，通知主处理器读取d_n[2]值；In the data processing interrupt step, the nth slave processor reads the data sent by the master processor, and judges it as the value of the DC component increment h ₀ [2], and after clearing the intermediate variable d _n [2], Let k take the value of 1, 2, ..., K respectively, execute formula (2) cyclically, and obtain the AC component increment h _nk [2], orthogonal component increment g _nk [2] and d _n [2] in sequence value, and then clear the status signal STS to notify the main processor to read the value of d _n [2];

$\{\begin{matrix} {h h}_{nk nk} [[22]] = = {h h}_{00} [[22]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + T T \cdot &Center Dot; {g g}_{nk nk} [[11]])) \\ {g g}_{nk nk} [[22]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot \cdot {h h}_{nk nk} [[11]])) \\ {d d}_{n no} [[22]] &LeftArrow; &LeftArrow; {d d}_{n no} [[22]] + + (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[22]])) \end{matrix} - - - - - - ((22))$

S102：主处理器查询状态信号STS的值，按序号n从小到大的顺序从N个处理器分别读取中间变量d₁[2]、d₂[2]、…、d_N[2]的值，从处理器发送对应数据后置状态信号STS为1；S102: The main processor queries the value of the state signal STS, and reads the values of the intermediate variables d ₁ [2], d ₂ [2], ..., d _N [2] from the N processors in ascending order of the sequence number n Value, the slave processor sends the corresponding data post-status signal STS to 1;

S103：主处理器按式(3)计算直流分量增量h₀[3]的值，并按序号n从小到大的顺序发送h₀[3]值到全部从处理器；S103: The master processor calculates the value of the DC component increment h ₀ [3] according to formula (3), and sends the value of h ₀ [3] to all slave processors in the order of sequence number n from small to large;

第n个从处理器在数据处理中断步骤中，读取主处理器发送来的数据，并判断为直流分量增量h₀[3]的值，把中间变量d_n[3]清零后，令k分别取值为1,2，…,K，循环执行式(4)，依次得到交流分量增量h_nk[3]、正交分量增量g_nk[3]和d_n[3]的值，然后清零状态信号STS，通知主处理器读取d_n[3]值；In the data processing interrupt step, the nth slave processor reads the data sent by the master processor, and judges it as the value of the DC component increment h ₀ [3], and after clearing the intermediate variable d _n [3], Let k take the value of 1, 2, ..., K respectively, execute formula (4) cyclically, and obtain the AC component increment h _nk [3], orthogonal component increment g _nk [3] and d _n [3] in sequence value, and then clear the status signal STS to notify the main processor to read the value of d _n [3];

$\{\begin{matrix} {h h}_{nk nk} [[33]] = = {h h}_{00} [[33]] + + {ω ω}_{nk nk} \cdot \cdot (({z z}_{nk nk} + + T T \cdot \cdot {g g}_{nk nk} [[22]])) \\ {g g}_{nk nk} [[33]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[22]])) \\ {d d}_{n no} [[33]] &LeftArrow; &LeftArrow; {d d}_{n no} [[33]] + + (({x x}_{nk nk} + + 22 T T \cdot \cdot {h h}_{nk nk} [[33]])) \end{matrix} - - - - - - ((44))$

S104：主处理器查询状态信号STS的值，按序号n从小到大的顺序从N个处理器分别读取中间变量d₁[3]、d₂[3]、…、d_N[3]的值，从处理器发送对应数据后置状态信号STS为1。S104: The main processor queries the value of the state signal STS, and reads the values of the intermediate variables d ₁ [3], d ₂ [3], ..., d _N [3] from the N processors in the order of sequence number n from small to large value, the slave processor sends the corresponding data and sets the status signal STS to 1.

第二处理方案依次包括：The second treatment plan in turn includes:

S201：主处理器按式(5)先计算直流分量增量h₀[4]的值，再进行迭代获得直流分量x₀的值，并按序号n从小到大的顺序发送h₀[4]值到全部从处理器；S201: The main processor first calculates the value of the DC component increment h ₀ [4] according to formula (5), and then iterates to obtain the value of the DC component x ₀ , and sends h ₀ [4] according to the sequence number n from small to large value to all slave processors;

第n个从处理器在数据处理中断步骤中，读取主处理器发送来的数据，并判断为直流分量增量h₀[4]的值，把中间变量d_n[4]清零后，令k分别取值为1,2，…,K，循环执行式(6)，先计算交流分量增量h_nk[4]和正交分量增量g_nk[4]的值，再进行迭代获得交流分量x_nk、正交分量z_nk和d_n[4]的值，依据迭代后的交流分量x_nk和正交分量z_nk计算得到估计幅值a_nk的值，然后清零状态信号STS，通知主处理器读取d_n[4]值；In the data processing interrupt step, the nth slave processor reads the data sent by the master processor, and judges it as the value of the DC component increment h ₀ [4], and after clearing the intermediate variable d _n [4], Let k take the value of 1, 2, ..., K respectively, execute the formula (6) in a loop, first calculate the values of the AC component increment h _nk [4] and the orthogonal component increment g _nk [4], and then iterate to obtain The value of AC component x _nk , quadrature component z _nk and d _n [4] is calculated according to the iterated AC component x _nk and quadrature component z _nk to obtain the value of the estimated amplitude a _nk , and then the state signal STS is cleared, Notify the main processor to read the _dn [4] value;

由于计算机系统中数据是有限字长的，为避免饱和，迭代过程中也可对直流分量、交流分量、正交分量分别进行限幅处理。Since the data in the computer system has a finite word length, in order to avoid saturation, the DC component, the AC component, and the quadrature component can also be limited separately during the iterative process.

S202：主处理器查询状态信号STS的值，按序号n从小到大的顺序从N个处理器分别读取中间变量d₁[4]、d₂[4]、…、d_N[4]的值，从处理器发送对应数据后置状态信号STS为1；S202: The main processor queries the value of the state signal STS, and reads the values of the intermediate variables d ₁ [4], d ₂ [4], ..., d _N [4] from the N processors in ascending order of the sequence number n Value, the slave processor sends the corresponding data post-status signal STS to 1;

S203：主处理器按式(7)计算直流分量增量h₀[1]的值，并按序号n从小到大的顺序发送h₀[1]值到全部从处理器；S203: The master processor calculates the value of the DC component increment h ₀ [1] according to formula (7), and sends the value of h ₀ [1] to all slave processors in the order of sequence number n from small to large;

第n个从处理器在数据处理中断步骤中，读取主处理器发送来的数据，并判断为直流分量增量h₀[1]的值，把中间变量d_n[1]清零后，令k分别取值为1,2，…,K，循环执行式(8)，依次获得交流分量增量h_nk[1]、正交分量增量g_nk[1]和d_n[1]的值，然后清零状态信号STS，通知主处理器读取d_n[1]值；In the data processing interrupt step, the nth slave processor reads the data sent by the master processor, and judges it as the value of the DC component increment h ₀ [1], after clearing the intermediate variable d _n [1], Let k take the value of 1, 2, ..., K respectively, execute formula (8) cyclically, and obtain the AC component increment h _nk [1], quadrature component increment g _nk [1] and d _n [1] in sequence value, and then clear the status signal STS to notify the main processor to read the value of d _n [1];

$\{\begin{matrix} {h h}_{nk nk} [[11]] = = {h h}_{00} [[11]] + + {ω ω}_{nk nk} \cdot \cdot {z z}_{nk nk} \\ {g g}_{nk nk} [[11]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; {x x}_{nk nk} \\ {d d}_{n no} [[11]] &LeftArrow; &LeftArrow; {d d}_{n no} [[11]] + + (({x x}_{nk nk} + + T T \cdot \cdot {h h}_{nk nk} [[11]])) \end{matrix} - - - - - - ((88))$

S204：主处理器查询状态信号STS的值，按序号n从小到大的顺序从N个处理器分别读取中间变量d₁[1]、d₂[1]、…、d_N[1]的值，从处理器发送对应数据后置状态信号STS为1。S204: The main processor queries the value of the state signal STS, and reads the values of the intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1] from the N processors in ascending order of the sequence number n value, the slave processor sends the corresponding data and sets the status signal STS to 1.

在主处理器发送到从处理器的数据中，除了h₀[1]、h₀[2]、h₀[3]与h₀[4]的数值部分以外，还包含ID1和ID0两位二进制数据标识，方便从处理器区分所接收数据是h₀[1]、h₀[2]、h₀[3]与h₀[4]中的哪一个。In the data sent from the master processor to the slave processor, in addition to the numerical parts of h ₀ [1], h ₀ [2], h ₀ [3] and h ₀ [4], it also contains two bits of ID1 and ID0 The data identification is convenient for the slave processor to distinguish which one of h ₀ [1], h ₀ [2], h ₀ [3] and h ₀ [4] the received data is.

步骤S4的循环执行功能通过主处理器的循环定时中断事件，触发定时中断步骤的循环执行来实现。The cyclic execution function of step S4 is realized by triggering the cyclic execution of the timing interruption step by a cyclic timing interrupt event of the main processor.

在上述实施方式中，参数μ、采样周期T、从处理器个数N、每个从处理器的交流频率个数K以及全部N×K个频率的数值，均可依据被测信号的先验知识与信号分析要求设定。In the above embodiment, the parameter μ, the sampling period T, the number of slave processors N, the number K of AC frequencies of each slave processor, and the values of all N×K frequencies can all be based on the prior knowledge of the signal under test. Knowledge and signal analysis requirements set.

参数μ的物理意义相当于指定频点处的通频带的带宽，依据香农采样定理，限定其数值不大于2π/T。μ数值大小对估计幅值的收敛速度具有主要影响，μ值越大，估计幅值越快地收敛到实际值，但同时加大了干扰对幅值估计精度的不良影响。The physical meaning of the parameter μ is equivalent to the bandwidth of the passband at the specified frequency point. According to the Shannon sampling theorem, its value is limited to no more than 2π/T. The value of μ has a major impact on the convergence speed of the estimated amplitude. The larger the value of μ, the faster the estimated amplitude converges to the actual value, but at the same time, the adverse effect of interference on the amplitude estimation accuracy is increased.

本发明的信号分析方法属于四阶迭代方法，在满足香农采样定理要求的条件下，各个迭代变量的稳态值与其实际值之间的误差，与采样周期T的四次方相关，采样周期越小，分析精度越高。The signal analysis method of the present invention belongs to the fourth-order iterative method. Under the condition of meeting the requirements of Shannon's sampling theorem, the error between the steady-state value of each iterative variable and its actual value is related to the fourth power of the sampling period T. The smaller the value, the higher the analysis accuracy.

与第一处理方案相比，第二处理方案还要进行交流分量x_nk和正交分量z_nk的迭代以及估计幅值a_nk的计算，执行时间更长。如果主处理器采样数据时间为Δt₁，主处理器执行式(5)和式(7)的总时间为Δt₂，从处理器循环执行式(6)和式(8)一次的总时间为Δt₃，主处理器与从处理器交换一个数据的时间为Δt₄，则本发明的信号分析方法的第二处理方案运行时间为Δt₁+Δt₂+K×Δt₃+(2N+2)Δt₄。而单处理器方法的第二处理方案运行时间为Δt₁+Δt₂+N×K×Δt₃。可见，K与Δt₃的数值越大，Δt₃与Δt₄的差值越大，本发明的信号分析方法节省的执行时间越显著。Compared with the first processing scheme, the second processing scheme also needs to iterate the AC component x _nk and the quadrature component z _nk and calculate the estimated amplitude a _nk , and the execution time is longer. If the data sampling time of the master processor is Δt ₁ , the total time for the master processor to execute formula (5) and formula (7) is Δt ₂ , and the total time for the slave processor to execute formula (6) and formula (8) once is Δt ₃ , the time for the master processor and the slave processor to exchange a piece of data is Δt ₄ , then the running time of the second processing scheme of the signal analysis method of the present invention is Δt ₁ +Δt ₂ +K×Δt ₃ +(2N+2) Δt ₄ . However, the running time of the second processing scheme of the single processor method is Δt ₁ +Δt ₂ +N×K×Δt ₃ . It can be seen that the larger the value of K and Δt ₃ is, the larger the difference between Δt ₃ and Δt ₄ is, and the execution time saved by the signal analysis method of the present invention is more significant.

若被测信号交流分量的实际频率分别等于设定的N×K个频率ω₁₁、ω₁₂、…、ω_1K、ω₂₁、…、ω_NK，则迭代变量直流分量x₀、交流分量x₁₁、x₁₂、…、x_1K、x₂₁、…、x_NK、正交分量z₁₁、z₁₂、…、z_1K、z₂₁、…、z_NK总能分别收敛到各自的实际值。因此对于这些迭代变量的初值没有特别限制，优选地，均设定为0。If the actual frequencies of the AC components of the measured signal are equal to the set N×K frequencies ω ₁₁ , ω ₁₂ , ..., ω _1K , ω ₂₁ , ..., ω _NK , then the iterative variables DC component x ₀ , AC component x ₁₁ , x ₁₂ , ..., x _1K , x ₂₁ , ..., x _NK , orthogonal components z ₁₁ , z ₁₂ , ..., z _1K , z ₂₁ , ..., z _NK can always converge to their respective actual values. Therefore, there is no special restriction on the initial values of these iteration variables, preferably, they are all set to 0.

设定标志字FLAG是为了区分两种不同的处理方案，只要能体现两种数值即可。优选地，标志字FLAG的值取为0和1。The flag word FLAG is set to distinguish two different processing schemes, as long as the two values can be reflected. Preferably, the value of the flag word FLAG is 0 and 1.

对于直流分量增量h₀[1]，中间变量d₁[1]、d₂[1]、…、d_N[1]，交流分量增量h₁₁[1]、h₁₂[1]、…、h_1K[1]、h₂₁[1]、…、h_NK[1]和正交分量增量g₁₁[1]、g₁₂[1]、…、g_1K[1]、g₂₁[1]、…、g_NK[1]的初值，没有特别限制。优选地，均设定为0。For DC component increments h ₀ [1], intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1], AC component increments h ₁₁ [1], h ₁₂ [1], ... , h _1K [1], h ₂₁ [1], ..., h _NK [1] and quadrature component increments g ₁₁ [1], g ₁₂ [1], ..., g _1K [1], g ₂₁ [1 ], ..., g The initial value of _NK [1] is not particularly limited. Preferably, both are set to 0.

若被测信号表示为u=U₀+U₁₁sin(Ω₁₁t+δ₁₁)+U₁₂sin(Ω₁₂t+δ₁₂)+…+U_1Ksin(Ω_1Kt+δ_1K)+U₂₁sin(Ω₂₁t+δ₂₁)+…+U_NKsin(Ω_NKt+δ_NK)，且指定频率ω₁₁、ω₁₂、…、ω_1K、ω₂₁、…、ω_NK依次分别等于实际频率Ω₁₁、Ω₁₂、…、Ω_1K、Ω₂₁、…Ω_NK，则经过上述方法分析之后，按照指数收敛规律，直流分量x₀收敛到U₀，交流分量x₁₁、x₁₂、…、x_1K、x₂₁、…、x_NK分别收敛到U₁₁sin(Ω₁₁t+δ₁₁)、U₁₂sin(Ω₁₂t+δ₁₂)、…、U_1Ksin(Ω_1Kt+δ_1K)、U₂₁sin(Ω₂₁t+δ₂₁)、…、U_NKsin(Ω_NKt+δ_NK)，正交分量z₁₁、z₁₂、…、z_1K、z₂₁、…、z_NK分别收敛到U₁₁cos(Ω₁₁t+δ₁₁)、U₁₂cos(Ω₁₂t+δ₁₂)、…、U_1Kcos(Ω_1Kt+δ_1K)、U₂₁cos(Ω₂₁t+δ₂₁)、…、U_NKcos(Ω_NKt+δ_NK)，估计幅值a₁₁、a₁₂、…、a_1K、a₂₁、…、a_NK分别收敛到U₁₁、U₁₂、…、U_1K、U₂₁、…、U_NK，获得高精度的分析结果。If the measured signal is expressed as u=U ₀ +U ₁₁ sin(Ω ₁₁ t+δ ₁₁ )+U ₁₂ sin(Ω ₁₂ t+δ ₁₂ )+…+U _1K sin(Ω _1K t+δ _1K )+U ₂₁ sin(Ω ₂₁ t+δ ₂₁ )+…+U _NK sin(Ω _NK t+δ _NK ), and the specified frequencies ω ₁₁ , ω ₁₂ ,…, ω _1K , ω ₂₁ ,…, ω _NK are respectively equal to the actual Frequency Ω ₁₁ , Ω ₁₂ , ..., Ω _1K , Ω ₂₁ , ... Ω _NK , after the analysis by the above method, according to the law of exponential convergence, the DC component x ₀ converges to U ₀ , and the AC components x ₁₁ , x ₁₂ , ..., x _1K , x ₂₁ ,…, x _NK respectively converge to U ₁₁ sin(Ω ₁₁ t+δ ₁₁ ), U ₁₂ sin(Ω ₁₂ t+δ ₁₂ ),…, U _1K sin(Ω _1K t+δ _1K ) , U ₂₁ sin(Ω ₂₁ t+δ ₂₁ ),…, U _NK sin(Ω _NK t+δ _NK ), the quadrature components z ₁₁ , z ₁₂ ,…, z _1K , z ₂₁ ,…, z _NK respectively converge to U ₁₁ cos(Ω ₁₁ t+δ ₁₁ ), U ₁₂ cos(Ω ₁₂ t+δ ₁₂ ),…, U _1K cos(Ω _1K t+δ _1K ), U ₂₁ cos(Ω ₂₁ t+δ ₂₁ ) , ..., U _NK cos(Ω _NK t+δ _NK ), the estimated amplitudes a ₁₁ , a ₁₂ , ..., a _1K , a ₂₁ , ..., a _NK converge to U ₁₁ , U ₁₂ , ..., U _1K , U ₂₁ , . . . , U _NK , to obtain high-precision analysis results.

以上实施例仅为本发明的示例性实施例，不用于限制本发明，本发明的保护范围由权利要求书限定。本领域技术人员可以在本发明的实质和保护范围内，对本发明做出各种修改或等同替换，这种修改或等同替换也应视为落在本发明的保护范围内。The above embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and the protection scope of the present invention is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements to the present invention within the spirit and protection scope of the present invention, and such modifications or equivalent replacements should also be deemed to fall within the protection scope of the present invention.

Claims

1. a master-slave multiprocessor real-time signal analysis method, is characterized in that, adopts a master processor and N slave processors to carry out; Wherein, the master processor takes T seconds as the sampling cycle, and the measured signal is regularly processed Sampling and obtaining sampling data, and using an iterative method to obtain the DC component x ₀ ; in the N slave processors, set the value of a positive integer K, and set the values of N×K frequencies to increase sequentially and not greater than 2π/ The positive numbers ω ₁₁ , ω ₁₂ , ..., ω _1K , ω ₂₁ , ..., ω _NK of T, use the iterative method to obtain N×K AC components x ₁₁ , x ₁₂ , ..., x _1K , x ₂₁ , ..., x _NK , N×K orthogonal components z ₁₁ , z ₁₂ , …, z _1K , z ₂₁ , …, z _NK , and calculate N×K estimated amplitudes a ₁₁ , a ₁₂ , …, a _1K , a ₂₁ ,…, a _NK , where,

For each sampling data u[s] of the signal under test, execute according to one of the following first processing scheme and second processing scheme, and execute different processing schemes for two consecutive sampling data, two processing schemes The scheme is executed successively once to complete an iterative calculation; where μ is a positive number not greater than 2π/T, and the serial number n of the processor is respectively 1, 2, ..., N;

The first treatment plan includes the following steps in sequence:

S101: The master processor calculates the value of the DC component increment h ₀ [2] according to formula (1), and sends the value to all slave processors;

{h h}_{00} [[22]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + T T \cdot \cdot {h h}_{00} [[11]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[11]])) - - - - - - ((11))

The nth slave processor obtains the value of the DC component increment h ₀ [2], and after clearing the intermediate variable d _n [2], let k take the value of 1, 2, ..., K respectively, and execute the formula (2 ), and obtain the values of AC component increment h _nk [2], quadrature component increment g _nk [2] and d _n [2] in turn;

\{\begin{matrix} {h h}_{nk nk} [[22]] = = {h h}_{00} [[22]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + T T \cdot &Center Dot; {g g}_{nk nk} [[11]])) \\ {g g}_{nk nk} [[22]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[11]])) \\ {d d}_{n no} [[22]] &LeftArrow; &LeftArrow; {d d}_{n no} [[22]] + + (({x x}_{nk nk} + + T T \cdot \cdot {h h}_{nk nk} [[22]])) \end{matrix} - - - - - - ((22))

S102: the main processor reads the values of the intermediate variables d ₁ [2], d ₂ [2], ..., d _N [2];

S103: the master processor calculates the value of the DC component increment h ₀ [3] according to formula (3), and sends the value to all slave processors;

{h h}_{00} [[33]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + T T \cdot &Center Dot; {h h}_{00} [[22]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[22]])) - - - - - - ((33))

The nth slave processor obtains the value of the DC component increment h ₀ [3], and after clearing the intermediate variable d _n [3], let k take the value of 1, 2, ..., K respectively, and execute the formula (4 ) to obtain the values of AC component increment h _nk [3], quadrature component increment g _nk [3] and d _n [3] in turn;

\{\begin{matrix} {h h}_{nk nk} [[33]] = = {h h}_{00} [[33]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + T T \cdot &Center Dot; {g g}_{nk nk} [[22]])) \\ {g g}_{nk nk} [[33]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + T T \cdot &Center Dot; {h h}_{nk nk} [[22]])) \\ {d d}_{n no} [[33]] &LeftArrow; &LeftArrow; {d d}_{n no} [[33]] + + (({x x}_{nk nk} + + 22 T T \cdot &Center Dot; {h h}_{nk nk} [[33]])) \end{matrix} - - - - - - ((44))

S104: the main processor reads the values of the intermediate variables d ₁ [3], d ₂ [3], ..., d _N [3];

The second treatment plan includes the following steps in turn:

S201: The main processor first calculates the value of the DC component increment h ₀ [4] according to the formula (5), and then iterates to obtain the value of the DC component x ₀ , and sends this value to all the slave processors;

\{\begin{matrix} {h h}_{00} [[44]] = = μ μ ((u u [[s the s]] - - (({x x}_{00} + + 22 T T \cdot &Center Dot; {h h}_{00} [[33]])) - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[33]])) \\ {x x}_{00} &LeftArrow; &LeftArrow; {x x}_{00} + + \frac{T T}{33} (({h h}_{00} [[44]] + + 22 {h h}_{00} [[33]] + + 22 {h h}_{00} [[22]] + + {h h}_{00} [[11]])) \end{matrix} - - - - - - ((55))

The nth one obtains the value of the DC component increment h ₀ [4] from the processor, clears the intermediate variable d _n [4], sets k to be 1, 2,..., K respectively, and executes formula (6) in a loop , first calculate the values of AC component increment h _nk [4] and quadrature component increment g _nk [4], and then iteratively obtain the values of AC component x _nk , quadrature component z _nk and d _n [4], according to The value of the estimated amplitude a _nk is obtained by calculating the AC component x _nk and the quadrature component z _nk after iteration;

\{\begin{matrix} {h h}_{nk nk} [[44]] = = {h h}_{00} [[44]] + + {ω ω}_{nk nk} \cdot &Center Dot; (({z z}_{nk nk} + + 22 T T \cdot &Center Dot; {g g}_{nk nk} [[33]])) \\ {g g}_{nk nk} [[44]] = = - - {ω ω}_{nk nk} \cdot &Center Dot; (({x x}_{nk nk} + + 22 T T \cdot \cdot {h h}_{nk nk} [[33]])) \\ {x x}_{nk nk} &LeftArrow; &LeftArrow; {x x}_{nk nk} + + \frac{T T}{33} (({h h}_{nk nk} [[44]] + + 22 {h h}_{nk nk} [[33]] + + 22 {h h}_{nk nk} [[22]] + + {h h}_{nk nk} [[11]])) \\ {z z}_{nk nk} &LeftArrow; &LeftArrow; {z z}_{nk nk} + + \frac{T T}{33} (({g g}_{nk nk} [[44]] + + 22 {g g}_{nk nk} [[33]] + + 22 {g g}_{nk nk} [[22]] + + {g g}_{nk nk} [[11]])) \\ {d d}_{n no} [[44]] &LeftArrow; &LeftArrow; {d d}_{n no} [[44]] + + {x x}_{nk nk} \\ {a a}_{nk nk} = = \sqrt{{x x}_{nk nk}^{22} + + {z z}_{nk nk}^{22}} \end{matrix} - - - - - - ((66))

S202: the main processor reads the values of the intermediate variables d ₁ [4], d ₂ [4], ..., d _N [4];

S203: The master processor calculates the value of the DC component increment h ₀ [1] according to formula (7), and sends the value to all slave processors;

{h h}_{00} [[11]] = = μ μ ((u u [[s the s]] - - {x x}_{00} - - {Σ Σ}_{n no = = 11}^{N N} {d d}_{n no} [[44]])) - - - - - - ((77))

The nth slave processor obtains the value of the DC component increment h ₀ [1], and after clearing the intermediate variable d _n [1], let k take the value of 1, 2, ..., K respectively, and execute the formula (8 ), sequentially obtain the values of AC component increment h _nk [1], quadrature component increment g _nk [1] and d _n [1];

\{\begin{matrix} {h h}_{nk nk} [[11]] = = {h h}_{00} [[11]] + + {ω ω}_{nk nk} \cdot \cdot {z z}_{nk nk} \\ {g g}_{nk nk} [[11]] = = - - {ω ω}_{nk nk} \cdot \cdot {x x}_{nk nk} \\ {d d}_{n no} [[11]] &LeftArrow; &LeftArrow; {d d}_{n no} [[11]] + + (({x x}_{nk nk} + + T T \cdot \cdot {h h}_{nk nk} [[11]])) \end{matrix} - - - - - - ((88))

S204: The main processor reads the values of the intermediate variables d ₁ [1], d ₂ [1], . . . , d _N [1].

2. master-slave multiprocessor real-time signal analysis method according to claim 1, is characterized in that, specifically comprises the following steps:

S1: Parameter setting:

The master processor sets the value of the sampling period T, the positive number μ, and the number of slave processors N,

The nth slave processor sets the sampling period T, the number of frequencies K, and the incremented frequency values ω _n1 , ω _n2 ,..., ω _nK ;

S2: Variable initialization:

The main processor sets the initial value of the DC component x ₀ , the DC component increment h ₀ [1], and the intermediate variables d ₁ [1], d ₂ [1], ..., d _N [1], and sets the initial value of the flag word The value is to execute the first processing scheme, set the timing interval according to the sampling period T and start timing,

The nth slave processor sets AC components x _n1 , x _n2 , ..., x _nK , quadrature components z _n1 , z _n2 , ..., z _nK , and AC component increments h _n1 [1], h _n2 [1] , ..., h _nK [1] and the initial value of the quadrature component increment g _n1 [1], g _n2 [1], ..., g _nK [1];

S3: Real-time analysis:

At the time of timing sampling, after the main processor obtains the sampling data u[s], it executes the first processing plan or the second processing plan according to the value of the flag word to obtain the value of the DC component x ₀ , and then modifies the value of the flag word to be Corresponding to another treatment scheme,

Under the control of the master processor, the nth slave processor correspondingly executes the operations prescribed by the first processing scheme or the second processing scheme, and obtains each AC component x _n1 , x _n2 , ..., x _nK , and orthogonal component z _n1 , z _n2 , ..., z _nK , estimated amplitudes a _n1 , a _n2 , ..., a _nK values;

S4: Loop execution:

When the timing of the sampling period T expires, return to step S3 for cyclic execution.