CN103000674B - Transistor and manufacturing method thereof - Google Patents

Abstract

The transistor has an inverted heterojunction structure in which the emitter layer is formed before the base and collector layers are formed. Higher cut-off frequency (f _T ) can be achieved by providing better thermal budget for critical base topography and doping profile control; parasitic capacitance can be significantly reduced by minimizing collector and base contact area , Increase the highest oscillation frequency (f _max ). This can significantly improve the frequency characteristics of the transistor. This inverted heterojunction structure can be prepared by forming an emitter layer on a pre-formed epitaxial monocrystalline metal silicide, a base layer on the emitter layer, and a collector layer on the base layer using the ALE process. get.

Description

A kind of transistor and its manufacturing method

technical field

The invention relates to electronic device technology, in particular to a transistor and a manufacturing method thereof.

Background technique

In the 0.5 to 6 terahertz (THz, ie 10 ¹² Hz) frequency system, imaging and spectroscopy systems have important applications in the fields of security, health, remote sensing, and basic science. Terahertz waves have strong attenuation strength in water, but have a greater penetration depth to biological tissues without causing damage to biological tissues. They are therefore particularly suitable for security applications involving low-risk imaging through opaque objects, such as through clothing, teeth, paper, plastic and ceramic materials. Terahertz waves are also ideal for health applications, such as early diagnosis of skin cancer. Consequently, many socially based applications involving security, medicine, bioanalysis, remote sensing for environmental monitoring, and natural disaster mitigation have recently been extensively studied. With their high frequency, terahertz waves are also suitable for extreme broadband communications.

However, so far, the terahertz frequency band region has very few daily applications. This has led to the expression "THz gap," which loosely describes the lack of sufficient technology to effectively bridge the gap between microwave frequencies below 1 THz and optical frequencies above 6 THz. Frequency bands, in particular, lack practical sources with useful power levels in this particular frequency range. Now, semiconductor electronics and laser optics work in opposite directions to narrow this terahertz gap. Advanced semiconductor technologies, including silicon-complementary metal-oxide semiconductor (Silicon-CMOS), silicon-germanium heterojunction bipolar transistor (SiGe HBT), and compound semiconductor HEMT devices (high electron mobility transistors), have greatly facilitated mm development of wave technology. However, the expected achievable frequency by the most powerful and cost-effective SiGe HBT technology is currently around 0.5 THz. In optics, modern solid-state lasers relying on transitions from well-defined electronic states encounter serious challenges in breaking the 6 THz barrier, since the energy of light at such frequencies is equal to the energy of thermal fluctuations at room temperature, i.e. kT = 26 millielectrons Volts (meV).

Currently, access to the THz band is possible through passive components such as frequency multipliers. However, such devices generally have significant power losses, which results in impractically small power-to-system volume ratios when using these devices in practical applications. Therefore, small and efficient active THz devices are the only solution. Vacuum electronics, including klystrons, have been considered as a way to bridge the THz gap. Such devices may be applied to military and aerospace fields, but it is foreseeable that their large size, significant energy consumption, and poor reliability will hinder their penetration into broad civilian fields such as safety and health. Therefore, solid-state electronics based on advanced semiconductors are the only ones that can be used in our daily life, especially portable terahertz systems using battery power.

A CMOS-based solution operating at 1 THz requires transistors with channel lengths of 10 nanometers (nm). However, at this gate length, the transistor outputs very low power due to quantum tunneling. With superior transconductance and noise characteristics, SiGe HBT technology is generally considered to provide the most robust and cost-effective solution for the emerging high-frequency market. Currently, the underlying technology for SiGe HBTs is SiGe by chemical vapor deposition (CVD). The current state-of-the-art SiGe HBT has a cut-off frequency of 0.4THz at room temperature. The ongoing European FP7 project called "DOTFIVE", including major European semiconductor companies, is trying to launch 0.5THz SiGe HBT technology in 2013. It is worth noting that in the DOTFIVE project, the circuit design of a complete frequency multiplier chain for 0.325 THz represents the current state of the art, but this is not only a very lossy approach, but it has not yet entered the THz gap.

Contents of the invention

In one embodiment, the SiGe HBT can form an ultra-thin (for example, less than or equal to 10 nm) semiconductor heterojunction on an epitaxial metal silicide by atomic layer epitaxy (ALE). Stress engineering can be applied to some or all regions of the HBT to improve lateral hole and vertical electron conduction. SiGe HBTs have an inverted heterojunction structure and maximize frequency performance by reducing parasitics and providing better thermal budget for critical base topography control. An inverted heterojunction structure can be prepared by using ALE technology to epitaxially form an emitter region on a pre-epitaxially formed metal silicide, epitaxially form a base region on the emitter region, and then epitaxially form a collector region on the base region. A new contact method is used to provide extremely low contact resistance in some or all of the HBT terminals.

SiGe HBT can be prepared by using CMOS technology suitable for industrial production.

In one embodiment, an HBT includes an ultra-thin monocrystalline epitaxial metal silicide layer grown on a semiconductor substrate, with a thickness of 10 nm or less, on which a monocrystalline silicon emitter is formed. A base electrode is formed on the electrode, and the base electrode has a width of about 10 nm or less; and a monocrystalline silicon collector electrode is formed on the base electrode. The HBT has an inverted structure with the collector closer to the surface of the HBT.

In a further embodiment, the emitter is carbon doped.

In a further embodiment, the monocrystalline epitaxial metal suicide is an ultrathin epitaxial _NiSi2 film on a Si(100) substrate.

In a further embodiment, the emitter and collector each have a thickness of about 10 nm or less.

In a further embodiment, at least one of the emitter, base and collector is formed by at least one ALE process.

In a further embodiment, the base comprises silicon germanium (SiGe).

The HBT further includes metal suicide contacts on the emitter, base and collector respectively, and the metal suicide contacts have a very low resistivity of about 45 milliohm·cm.

In a further embodiment, the collector is stressed in the transport direction to increase electron mobility.

In a further embodiment, the collector electrode is lightly doped silicon with a metal silicide layer on the surface.

In a further embodiment, the base is subjected to stress treatment to enhance lateral hole and vertical electron conduction in the base, and further deformed in another direction.

In one embodiment, a method for manufacturing an HBT includes the following steps: epitaxially growing a single crystal metal silicide layer on a semiconductor substrate, and the metal silicide layer has a thickness of 10 nm or less; Epitaxial growth of single crystal silicon emitter on the layer; epitaxial growth of SiGe base on the emitter; epitaxial growth of single crystal silicon collector on the SiGe base.

In a further embodiment, the metal silicide layer is NiSi2 grown on Si(100) by a solid state reaction (SSR) process comprising sputter deposition of a Ni film approximately equal to ₂ nm thick and rapid thermal treatment.

In a further embodiment, the emitter is grown using an ALE process and is doped with carbon in situ during the ALE process.

In a further embodiment, photons emitted from a laser source are used in the ALE process to assist in the release of hydrogen atoms from the substrate surface.

In a further embodiment, both the silicon emitter layer and the SiGe base layer are strained, and the SiGe base layer is strained in multiple directions.

In a further embodiment, mechanical stress is applied to the collector layer from the top surface of the HBT due to the inverted structure.

Description of drawings

1 is a schematic cross-sectional view of a SiGe HBT device according to one embodiment;

2 is a flow chart of a method for fabricating a SiGe HBT device according to an embodiment;

3a to 3h are schematic cross-sectional views corresponding to each step of a method for fabricating a SiGe HBT device according to an embodiment;

4A is a transmission electron microscope (TEM) image of 6 nm thick epitaxial NiSi ₂ grown on Si(100) using SSR according to one embodiment.

Figure 4B is a RHEED image of 10 nm thick epitaxial Si grown on _NiSi2 using molecular beam epitaxy.

5 is a schematic diagram of simulation results of the relationship between the operating frequency (f _T ) and the collector current density Jc of a SiGe HBT optimized for large implant operation according to one embodiment.

detailed description

According to an embodiment of the present invention, a novel "inverted" silicon-germanium heterojunction bipolar transistor (SiGe HBT) device capable of penetrating into the terahertz gap (THz gap) frequency band from the microwave direction is provided. Preparation of SiGe by employing revolutionary thin-film technology innovations related to materials, process technologies and device structures, such as solid-state reaction (SSR) epitaxial growth of NiSi ₂ on Si and atomic layer epitaxy on NiSi ₂ , etc. HBT, the HBT device can work in the terahertz gap frequency band.

FIG. 1 is a schematic cross-sectional view of an inverted HBT 100 according to one embodiment of the present invention. As shown in FIG. 1, the inverted HBT 100 includes an epitaxial layer 110 on a semiconductor (eg, silicon) substrate 101, an emitter 120 on the epitaxial layer 110, a base 130 on the emitter 120, and a The collector electrode 140 on the electrode layer. Therefore, the order of the emitter 120, base 130, and collector 140 in the inverted HBT 100 is reversed from that in a conventional bipolar transistor. One advantage of this layout is that, unlike conventional bipolar transistors where the emitter terminal is grounded in a collector-emitter (CE) structure, the emitter in the HBT 100 of this embodiment is close to the ground in the substrate 101. low potential area. On the other hand, the collector is close to the top or surface 102 of the HBT 100, therefore, the collector is closer to or directly contacts the circuit metal layer (not shown) connected to the HBT and is easily accessible from the top of the device. As a result, the influence of parasitic effects (in particular, collector-base capacitance C _bc ) is significantly reduced, enabling a gain in performance to be achieved.

In one embodiment, the epitaxial layer 110 includes monocrystalline silicide formed during heteroepitaxial growth, and the emitter includes epitaxially grown silicon. In an improved embodiment, the emitter comprises carbon-doped silicon (Si(C)), which has a larger energy bandgap than silicon (Si), enabling more enhanced carrier injection. The epitaxial silicon emitter can bring good high frequency performance due to the ability to form a good heteroepitaxial silicon (Si) or silicon germanium (SiGe) base thereon. In one embodiment, the base is fabricated by atomic layer epitaxy (ALE), and its width w can be very thin so that the base transit time does not significantly limit the performance of the HBT.

Such an "inverted bipolar" structure can allow simple doping optimization of the collector so that special heterojunction structures can be formed, enabling devices to operate at higher current densities to reach higher frequency limits . Furthermore, the inverted structure can greatly simplify the application of deformations that are important for operation in the terahertz frequency range.

In one embodiment, the epitaxial layer 110 comprises an epitaxial metal suicide having a sheet resistance of about 50 ohms/square in order to minimize carrier transit time and series resistance and improve thermal management.

In one embodiment, the base layer comprises Si or SiGe. Higher operating frequencies can be obtained by forming the base with SiGe. Although a silicon base is also feasible, the following discussion will mainly focus on HBT 100 with a SiGe base layer, and SiGe HBT 100 is substituted for HBT 100 below. In one embodiment, the base layer employs stress engineering to enhance conduction of holes laterally and electrons vertically in the substrate. In one embodiment, in addition to using the stressed SiGe layer, the stress is applied in another direction in order to further improve the performance of the device. Well-developed stress techniques, such as heterojunction epitaxy processing and silicon nitride tensile and compressive stress, have been widely used in state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology, and can also be used in the discussion of the present invention stress application.

In one embodiment, the base 130 of the SiGe HBT 100 includes an extrinsic base region 130a and an intrinsic base region 130b. In one embodiment, the thickness of the intrinsic base region is about 10 nm or less. To avoid unnecessarily high resistance caused by such a thin intrinsic base region, the emitter strip 120 is made very narrow (e.g., about 20 nanometers or less), and the HBT 100 can have multiple emitter strips to Optimize performance. In one embodiment, the emitter is patterned using electron beam lithography or immersion lithography to achieve high resolution.

In one embodiment, the collector comprises silicon and is stress treated. In one embodiment, the collector is lightly doped silicon with a metal silicide layer on the upper surface, and is stress-treated in the transport direction to increase electron mobility. The inverted collector region structure close to the surface 102 facilitates stress application and control. In one embodiment, the size of the suicide contact region 150 on top of the collector can be as large as the collector to minimize contact resistance.

In one embodiment, SiGe HBT 100 also includes low-resistivity contact regions 150 at its terminals. For example, it can be very low contact resistance (for example, below 10 ^-8 Ωcm ² ) at the emitter and base, and a very low Schottky barrier (SBH) at the collector (for example, about 0.1eV) The nickel silicon (NiSi) contact area.

In one embodiment, advanced ALE and epitaxial silicide technologies are used to fabricate high-performance HBTs operating at frequencies exceeding 1 THz. At such high frequencies, special care should be taken to minimize all parasitic components, both internal and external, which would otherwise adversely affect active devices.

The ALE process, which deposits one atomic layer at a time, ensures that the atoms in a layer end up deposited in the correct lattice positions during the low-temperature deposition process. Therefore, ALE does not require an additional high-temperature step compared to conventional chemical vapor deposition (CVD), which requires very high deposition temperatures. Compared with molecular beam epitaxy (MBE), which can also achieve atomic-level deposition control, ALE is beneficial to obtain narrow distribution profiles that are highly desirable in practical terahertz devices. In one embodiment, ultra-high vacuum (UHV) ALE is used to grow carbon-doped silicon (denoted Si(C)) emitter, germanium-silicon base, and silicon collector.

FIG. 2 is a flowchart of a SiGe HBT fabrication process 200 according to one embodiment of the present invention. 3a to 3h are cross-sectional views corresponding to each step in the SiGe HBT manufacturing process 200. FIG. As shown in Figures 2 and 3a, a semiconductor substrate 301 is provided (step 201). The semiconductor substrate 101 may be a silicon substrate or a silicon-on-insulator (SOI) substrate.

As shown in Figures 2 and 3b, a single crystal metal silicide layer 110 is grown on a semiconductor substrate by a heterojunction epitaxy process (step 210). The epitaxial silicide layer 110 replaces the traditionally used thick highly doped silicon layer as a sub-collector, and has a sheet resistance below 50Ω suitable for terahertz frequency operation. Since the silicide layer can be very thin (≤10nm), the parasitic fringe capacitance connected to any sidewall of the sub-emitter is greatly reduced.

In one embodiment, the epitaxial silicide layer 110 is an ultra-thin NiSi ₂ film grown on the silicon substrate 100 by a solid state reaction (SSR) process. In one embodiment, the SSR process first deposits a Ni film about 2 nm thick by sputtering, followed by a brief heat treatment at about 700°C. As shown in Fig. 4A, the thickness of the 6 nm-thick epitaxial _NiSi2 film grown on Si(100) is uniform, and has sharp interfaces and smooth surfaces at the atomic layer level. In addition, the film has very low resistivity, eg, 45 μΩ-cm, or a sheet resistance of about 75Ω per unit area.

As shown in FIGS. 2 and 3 c , a carbon-doped silicon (Si(C)) emitter 120 and a SiGe base 130 are sequentially formed on the epitaxial silicide layer 110 using an ALE process (corresponding to steps 220 and 230 , respectively). In the ALE process, thickness and composition control with monoatomic layer precision can be achieved, and different chemicals and materials can be processed rapidly. The emitter 120 is doped in-situ to achieve a steep impurity distribution at the atomic layer level. ALE processes with single-atom-layer control typically rely on the cyclic processing of two precursors to form _{AxBy -} type binary compounds, such as III-V or II-VI semiconductors. A key feature of the ALE process 230 is self-limitation, which is achieved through a chemisorption process at temperatures below 400°C in an ultra-high vacuum (UHV) environment. In this way, at most one monolayer of composition A or B can be grown per cycle, independently of the length of the growth cycle. For the growth of single-element silicon films, cyclic processing can be achieved by using silicon hexachloride (Si ₂ Cl ₆ ) and silicon hexahydrogen (Si ₂ H ₆ ). However, this process is not truly self _- limiting because _Si2H6 is easily decomposed above 400 °C. In this regard, ALE of germanium-silicon alloys in base 130 is expected to be more difficult because germanium precursors such as germanium methane (GeH ₄ ) or digermanium hexahydrogenate (Ge ₂ H ₆ ) tend to be more difficult at lower temperatures. break down. In order to achieve self-limited growth at the atomic layer level, the growth process needs to be performed at a low temperature. One challenge of low-temperature growth is the desorption of hydrogen atoms from the growing silicon surface, leaving room for subsequent silicon adsorption and deposition. Using photons or plasmas can help release hydrogen atoms, enabling atomic layer epitaxy of silicon. To avoid plasmon-induced damage, epitaxy of Si and SiGe can be performed using photonic methods to achieve monoatomic layer control. A conventional ultra-high vacuum ALE or ALD system with an external laser source can be used to implement the ALE process of the present invention.

As shown in FIG. 2, the process 200 further includes: performing appropriate stress treatment on the Si emitter 120 (step 225) and the SiGe base 130 (step 235) to shorten the transit time and achieve an operating frequency (fT) greater than 1.1 Ω Hertz's SiGeHBT. By introducing a combination of uniaxial and biaxial stresses in the heterojunction structure, the carrier mobility and the operating frequency of the carrier-mobility-affected devices can be significantly increased. This can be achieved by intrinsic heterojunction epitaxial growth and extrinsic strained layer deposition. Likewise, it is well known that heterojunctions are beneficial for carrier injection and carrier transport. As successfully applied in CMOS technology, the use of strained layers for stress treatment can provide more degrees of freedom for carrier mobility enhancement.

As shown in Figures 2 and 3d, silicon layer 140 is formed by a heterojunction epitaxial process (step 240). In order to maintain a steep doping profile between different layers, and taking the formation of an NPN HBT as an example, the emitter 120, the base 130 and the collector 140 are respectively N-type, P-type and N-type in-situ doped during the ALE process. miscellaneous. For an NPN HBT according to one embodiment, during normal operation, the bias voltage between the base and emitter (V _BE ) is positive and the bias voltage between the base and collector (V _BC ) is negative.

As shown in FIGS. 2 , 3e to 3f , the emitter 120 , base 130 and collector 140 are patterned and etched in step 145 to form the emitter 120 , base 130 and collector 140 . As shown in FIG. 3 g , an insulating dielectric layer 103 is deposited, then planarized, and then contact holes are formed in the insulating dielectric layer 103 . The contact holes 160 are used to subsequently form contact regions on the emitter, base and collector.

As shown in Figures 2 and 3h, contact regions are formed on the emitter, base and collector (step 250). In one embodiment, a nickel silicide (NiSi) contact region can be formed using a conventional self-aligned CMOS process without an additional photolithography mask. The emitter and base have ultra-low contact resistance (for example, lower than 10 ^-8 Ωcm ² ), using the metal-semiconductor contact impurity separation (DS: dopant segregation) technology developed in CMOS research, the metal of the collector Semiconductor contacts can reach very low Schottky barrier heights (SBH) (eg, about 0.1 eV). This will further improve the frequency performance of SiGe HBT100. So far, electrical contact regions have received little attention in conventional HBT studies. Considering the structural constraints of HBTs and their associated processes, the usual heavy doping techniques and proper metal selection with low contact resistance are not easy to implement, thus, the contact area becomes an important issue for THz devices. In order to reduce the contact resistance of all three terminals, techniques such as impurity separation can be used to change the Schottky barrier height between the metal silicide and the semiconductor.

Accordingly, SiGe HBTs are formed by atomic layer epitaxy (ALE), specifically, the formation of ultra-thin (eg, less than 10 nanometers) semiconductor heterojunctions on epitaxial metal suicides. Stress techniques are applied on some or all regions of the HBT, resulting in simultaneous enhancement of lateral hole and vertical electron conduction. SiGeHBT has an inverted heterojunction structure and maximizes frequency performance by reducing parasitic effects and providing better thermal budget for critical base topography and distribution control. A new contact strategy is employed to obtain extremely low contact resistance in some or all of the HBT terminals.

Therefore, a good inverted SiGe HBT capable of operating in the terahertz frequency band can be fabricated using a semiconductor-based process using the ALE process to form Si, SiGe, and carbon-doped silicon Si(C) structures on single-crystal silicide films. Alternatively, molecular beam epitaxy (MBE) can also be used for semiconductor growth. The surface and interfacial properties obtained by epitaxial _NiSi2 films are important to facilitate epitaxy on various Si or SiGe films. For example, as shown in the reflection high-energy electron diffraction (Reflection High-Energy Electron Diffraction, “RHEED”) image in FIG. 4B , epitaxial Si with a thickness of 10 nm can be grown on epitaxial NiSi ₂ film at 380° C. Although not carefully prepared, the quality of the growing surface is already reasonable.

FIG. 5 is a simulation result of a device structure optimized for a large injection working condition based on an embodiment of the present invention: a graph showing the relationship between SiGe HBT operating frequency (f _T ) and collector current density Jc.

The performance advantages of SiGe HBT mainly come from the small energy band gap of SiGe and the acceleration of carriers in the longitudinal electric field caused by the energy band gap gradient. However, the longitudinal electron mobility and lateral hole mobility, which are important for the base resistance, are only slightly improved. On the other hand, in CMOS technology, the key performance enhancement factor of CMOS below 90nm is the lateral field mobility enhancement achieved by stress engineering. In one embodiment, bandgap engineering and mobility engineering are combined to further improve the performance of the HBT. For example, additional stress treatments can be used to improve lateral hole mobility, thereby reducing the base resistance that limits the maximum operating frequency of SiGe HBTs.

Claims (21)

1. a kind of transistor, it is characterised in that include：

The single crystal epitaxial metal silicide layer in Semiconductor substrate；

The monocrystalline emitter being formed on the metal silicide layer；

The base stage being formed on the emitter stage；With formation monocrystal silicon colelctor electrode on said base；

The insulation dielectric layer being deposited on the emitter stage, base stage and colelctor electrode, the contact hole being formed in insulation dielectric layer；

It is formed in the contact area of the correspondence contact hole position on emitter stage, base stage and colelctor electrode；

Wherein, the transistor has inverted structure of the colelctor electrode closer to transistor surface.

2. transistor according to claim 1, it is characterised in that the single crystal epitaxial metal silicide is to be located at Si substrates On extension NiSi₂Film.

3. transistor according to claim 1, it is characterised in that the single crystal epitaxial metal silicide layer thickness be less than or Person is equal to 10 nanometers, and the base stage has the width less than or equal to 10 nanometers.

4. transistor according to claim 1, it is characterised in that the emitter stage is carbon doping.

5. transistor according to claim 1, it is characterised in that the thickness of the emitter stage and the colelctor electrode is respectively less than Or equal to 10 nanometers.

6. transistor according to claim 1, it is characterised in that in the emitter stage, the base stage and the colelctor electrode At least one is formed by least one ALE techniques.

7. transistor according to claim 1, it is characterised in that the base stage includes SiGe SiGe.

8. transistor according to claim 1, further distinguishes on the emitter stage, the base stage and the colelctor electrode Comprising Metal-silicides Contact area；The Metal-silicides Contact area has the resistivity of low-down 45 micro-ohm cm.

9. transistor according to claim 1, it is characterised in that the colelctor electrode is strained in carrier transport direction Process.

10. transistor according to claim 1, it is characterised in that the extremely lightly doped silicon of the current collection and in upper surface There is metal silicide layer.

11. transistors according to claim 1, it is characterised in that the base stage carries out strained handling.

12. transistors according to claim 11, it is characterised in that the base stage is further entered in an extra direction Row strained handling.

13. a kind of manufacture methods of transistor, it is characterised in that comprise the steps of：

Epitaxial growth single-crystal metal silicide layer on a semiconductor substrate；

In the metal silicide layer Epitaxial growth monocrystalline emitter；

In the emitter stage Epitaxial growth base stage；

Epitaxial growth monocrystal silicon colelctor electrode on said base；

Insulation dielectric layer is deposited on the emitter stage, base stage and colelctor electrode, contact hole is formed in insulation dielectric layer；

The correspondence contact hole position forms contact area on emitter stage, base stage and colelctor electrode.

14. according to claim 13 transistor manufacture method, it is characterised in that the metal silicide layer is using solid State reaction SSR techniques are grown in the NiSi on Si₂Film.

15. according to claim 14 transistor manufacture method, it is characterised in that the SSR is processed and is included following sub-step Suddenly：

Ni film of the sputtering sedimentation thickness less than or equal to 2 nanometers；

Heat treatment.

16. according to claim 13 transistor manufacture method, it is characterised in that the emitter stage is given birth to by ALE techniques It is long.

17. according to claim 16 transistor manufacture method, it is characterised in that the emitter stage is in ALE technical processs In carry out carbon doping in situ.

18. according to claim 16 transistor manufacture method, it is characterised in that in ALE technical processs, using from swash The photon that light source sends helps the hydrogen atom on release liners surface.

19. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：To Si Emitter layer carries out strained handling.

20. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：It is right SiGe base layers carry out strained handling in multiple directions.

21. according to claim 16 transistor manufacture method, it is characterised in that further comprise the steps of：To collection Electrode layer applies mechanical stress from the top surface of the transistor.