CN103000649B - A kind of cmos image sensor encapsulating structure and manufacture method thereof - Google Patents

Abstract

A CMOS image sensor packaging structure and a manufacturing method thereof belong to the field of sensors. The optical interaction area is located in the center of the first surface of the front side of the silicon substrate, a metal interconnection layer is formed above the optical interaction area, the microlens array is placed above the metal interconnection layer, and there is a first protective layer outside the metal interconnection layer; Through-silicon holes and redistribution layers that do not penetrate the silicon substrate are made on the surface, and the I/O around the optical interaction area is connected to the through-silicon holes through the redistribution layer; the walls of the through-silicon holes are filled with a passivation layer; There is a second protective layer on the distribution layer; the silicon substrate is bonded to the glass sheet, and a cavity is set between the glass sheet and the silicon substrate; the second surface of the silicon substrate is thinned to expose through-silicon holes; the silicon substrate second A circuit layer is made on the surface to connect the TSV to the pad, and a solder mask is made on the circuit layer to expose the pad; solder balls are on the pad. The invention improves the delamination problem between the glass and the silicon substrate in the packaging structure, improves the reliability, and the packaging structure is suitable for larger size chips.

Description

A kind of CMOS image sensor packaging structure and manufacturing method thereof

technical field

The invention relates to the technical field of manufacturing semiconductor components. The invention provides a package structure of a CMOS image sensor and a manufacturing method of the CMOS image sensor.

Background technique

Image sensors belong to the optoelectronic components category in the optoelectronic industry. It is a semiconductor module and a device that converts an optical image into an electronic signal. The electronic signal can be used for further processing or digitized and stored, or used to transfer the image to another display device for display, etc. It is widely used in digital cameras and other electro-optical devices. Image sensors are now mainly divided into charge-coupled devices (CCD) and CMOS image sensors (CIS, CMOS Image Sensor). Although CCD image sensors are superior to CMOS image sensors in terms of image quality and noise, CMOS sensors can be manufactured with traditional semiconductor production techniques at lower production costs. At the same time, due to the relatively small number of components used and the short signal transmission distance, CMOS image sensors have the advantages of low power consumption, reduced capacitance, inductance, and parasitic delay.

Compared with CCD image sensors, CMOS image sensors have a more convenient driving mode and can realize various scanning types; meanwhile, integrating signal processing circuits (ICs) into a single chip makes it possible to miniaturize CMOS image sensors. Furthermore, by using widely compatible CMOS technology, CMOS image sensors contribute to lower power consumption and lower manufacturing costs. Therefore, CMOS image sensors have wider applications.

Figure 1 shows a schematic diagram of a conventional CMOS image sensor (CIS) package. The shown CMOS sensor generally includes: a ceramic substrate 2 on which an integrated circuit 4 (IC) is mounted on the top surface, and an adhesive layer 3 is located between the integrated circuit 4 (IC) and the ceramic substrate 2 . On the surface of the integrated circuit 4 (IC), there is a prepared pad 6 on the surface of the IC, which is connected to a pad 8 on the surface of the ceramic substrate 2 through a lead 7 . The image photosensitive area 5 is located on the top of the integrated circuit 4 (IC), and the image photosensitive area 5 includes an array of optical interactive elements (such as photodiodes, photodiodes) capable of receiving light and generating electrical signals. The glass lens 10 corresponding to the optical interactive element is installed on the frame 1 , and the frame 1 is connected with the ceramic substrate 2 through an adhesive 9 .

The CMOS sensor structure shown in Figure 1 has many aspects that could be improved. First, because the package uses a bulky glass lens 10 , which is extremely unfavorable for reducing the package volume, so the package volume can be reduced by using a micro lens. Second, the ceramic base 2 can be replaced by a silicon substrate, and the I/O (not shown) on the edge of the integrated circuit 4 (IC) is connected to the I/O on the surface of the base by making a redistribution layer (RDL) on the surface of the silicon substrate. The pads 8 are connected, which can further reduce the size of the package structure. Third, the package structure shown is not capable of using lower cost wafer-level processing and surface mount technologies.

With the development of CMOS technology, the degree of integration is getting higher and higher, which makes the area of the image sensing area more and more small to realize a larger photosensitive area. For the CIS packaging structure that uses glass-to-wafer bonding, the larger viewing area will lead to more and more serious delamination between the glass and the silicon substrate.

In order to solve the above problems, the present invention provides a CMOS image sensor (CIS) packaging structure. By setting a stepped protrusion structure in the bonding area between the glass and the semiconductor substrate, the bonding reliability between the semiconductor substrate and the glass is enhanced, thereby improving the bond between the glass and the silicon substrate in the existing packaging structure delamination issues, improving package reliability while making the package structure suitable for chip size packages with larger chip sizes. At the same time, the embodiment of the present invention also provides a manufacturing method of the CMOS image sensor (CIS) package, by making through-silicon vias (TSVs) on the front side of the silicon substrate, and through the circuit redistribution layer and the outer periphery of the optical interaction area. The I/Os are connected to the backside of the silicon substrate via TSVs. The implementation of the present invention not only reduces the volume size after packaging, reduces the packaging cost, improves the packaging efficiency, but also meets the requirements of high-density packaging; at the same time, due to the short data transmission path and high stability, this packaging is reduced in size. While reducing energy consumption, it also improves the speed and stability of data transmission.

Contents of the invention

The first aspect of the present invention is to provide an improved CMOS image sensor (CIS) packaging structure to be suitable for CMOS image sensor (CIS) packaging with a larger chip size.

The CMOS image sensor of the present invention includes: a silicon substrate 200, the front of the silicon substrate 200 is the first surface 201 formed with a microlens 230, a metal interconnection layer 220 and an optical interaction region 210, the silicon substrate The back side of the bottom 200 is the second surface 202 . Wherein the optical interaction area 210 is located in the center of the first surface 201 of the front side of the silicon substrate 200, and a metal interconnection layer 220 is formed above the optical interaction area 210, and the microlens 230 array is placed on the metal interconnection layer 220, and the metal interconnection layer A first protection layer 235 is formed on the outer side of 220 . By making through-silicon vias 260 (TSVs) and redistribution layers (RDLs) that do not penetrate the silicon substrate 200 on the first surface 201, the I/Os around the optical interaction region 210 are connected to the silicon through the redistribution layer (RDL). Through vias 260 (TSVs). A passivation layer 265 is formed on the hole wall of the through-silicon via 260 (TSV), and the hole is filled by an electroplating process. The second protective layer 240 is made of a polymer material on the redistribution layer (RDL) and has a stepped protrusion or groove structure. The silicon substrate 200 and the glass sheet 250 are bonded together through a polymer bonding glue 255 , and a cavity is formed between the glass sheet 250 and the silicon substrate 200 through exposure and development. By grinding and etching the second surface 202 of the silicon substrate 200 , the silicon substrate is thinned and the through silicon vias 260 (TSVs) are exposed. By making a circuit layer on the second surface 202 of the silicon substrate 200, the through-silicon via 260 (TSV) is connected to the pad pad 290, and a solder mask 280 (SMF) is made on the circuit layer and exposes the pad pad 290 to The circuit layer on the second surface 202 is protected. Solder balls 295 are formed on the pads 290 .

The protective layer material is silicon nitride. The polymer material is composed of resin, solvent, photosensitive compound and additives.

A second aspect of the present invention provides a method of manufacturing the CMOS image sensor, comprising the following steps:

Step 1: Provide the silicon substrate

The silicon substrate includes a first surface formed with a micro lens, an integrated circuit IC and an optical interaction area, and a second surface opposite to the first surface.

Step 2: Etch TSV holes on the first surface of the silicon substrate

In this step, a layer of photoresist is first coated on the front side of the silicon substrate, and an etching window is formed through exposure and development; a dry etching process is used to form TSV holes, and the dry etching process includes Deep Reactive Ion Etching (DRIE) .

Step 3: Form a passivation layer inside the TSV hole and on the first surface of the silicon substrate

A passivation layer is formed in the TSV hole and on the front surface of the silicon substrate by using plasma chemical vapor deposition (PECVD), and the material of the passivation layer is a polymer dielectric material.

Step 4: Expose the I/O on the periphery of the optical interaction area

The etching window is formed by exposing and developing the passivation layer deposited on the first surface of the silicon substrate, and the I/Os on the periphery of the optical interaction area are exposed by dry etching.

Step 5: Electroplating and filling TSV to realize electrical interconnection

The formed TSV holes are filled and covered by the electroplating process to cover the first surface, so that the through-silicon vias (TSVs) are connected with the I/Os on the periphery of the optical interaction area to form a redistribution layer (RDL) to realize electrical interconnection.

Step 6: Form the protective layer and place the micro lens

When the second protective layer is formed on the first surface of the silicon substrate, the second protective layer with a stepped protrusion or groove structure is formed on the bonding area between the silicon substrate and the glass through exposure, development and etching processes; A microlens is disposed over the metal interconnection layer on the first surface of the bottom.

Step 7: Bond the silicon substrate to the glass

In this step, the polymer bonding glue is first coated on the glass surface that has been pre-treated and cleaned. The pre-treatment cleaning includes pickling neutralization, plasma cleaning, etc.; A cavity is formed; finally, the silicon substrate is bonded to the glass by coating a layer of resin glue on the surface of the polymer bonding glue and using a bond and a machine.

Step 8: Grinding and etching the second surface of the silicon substrate

In this step, the second surface of the silicon substrate is firstly ground and thinned; secondly, the second surface of the ground silicon substrate is subjected to stress relief plasma etching to remove the internal stress remaining in the wafer due to grinding, Reduces wafer warpage and exposes through-silicon vias (TSVs).

Step 9: Make the circuit layer on the second surface of the silicon substrate

In this step, an insulating layer is first deposited on the back of the silicon substrate; then a layer of metal is sputtered and patterned to form a circuit layer and pad pad; finally, a layer of solder mask is coated on the circuit layer layer (SMF) and expose the pad pad and protect the formed lines.

Step Ten: Make the Solder Balls

Solder balls are formed on the pads through a ball planting process.

In the seventh step, the polymer glue can also be selected as a dry film (Dry Film), and the dry film is composed of resin, solvent, photosensitive compound and additives, etc., and the surface of the polymer glue can be omitted. The bonding with the wafer is completed through the one-step process of applying adhesive, and the dry film used can be directly bonded with the wafer without applying adhesive, which reduces the process flow.

The invention effectively increases the bonding strength between the glass and the silicon substrate by making a stepped protrusion or groove structure on the front of the silicon substrate, improves the delamination between the glass and the wafer, and improves the reliability of the package. characteristics, making the package suitable for a CIS package with a larger chip size. Simultaneously according to the embodiment of the present invention, the manufacturing method of the described CMOS image sensor that provides, has adopted dry film at first as the bonding material between glass and wafer; The internal stress generated by grinding in the wafer can be effectively removed, and the warpage of the wafer is improved, thereby further facilitating subsequent process operations. These steps reduce the process flow, improve product reliability and production efficiency, and at the same time improve product yield and reduce production cost.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional CMOS sensor (CIS).

FIG. 2 is a schematic diagram of a CMOS image sensor package drawn according to an embodiment of the present invention.

3( a ) to ( j ) are cross-sectional schematic diagrams of the manufacturing process of a CMOS sensor drawn according to an embodiment of the present invention.

In the figure: 1. Frame, 2. Ceramic substrate, 3. Adhesive layer, 4. Integrated circuit, 5. Image photosensitive area, 6. Welding pad on IC surface, 7. Lead wire, 8. Welding pad on substrate surface, 9. Adhesive, 10. Glass lens, 200. Silicon substrate, 201. First surface, 202. Second surface, 210. Optical interaction area, 220. Metal interconnect layer, 225. Hole, 230. Microlens , 235. First protection layer, 240. Second protection layer, 250. Glass sheet, 255. Polymer bonding glue, 260. Through silicon via, 261. TSV hole, 265. Passivation layer, 270. Insulation layer, 280. Solder mask, 290. Land pad, 295. Solder ball.

Detailed ways

The present invention enhances the bonding force between the glass sheet 250 and the silicon substrate 200 by making a stepped protrusion or groove structure on the first surface 201 of the silicon substrate 200, and improves the delamination problem between the glass and the silicon substrate , which improves the reliability of the package and is suitable for CMOS image sensor (CIS) packages with larger chip sizes. FIG. 2 is a schematic diagram of a CIS package of a stepped protrusion structure fabricated on a first surface 201 of a silicon substrate 200 according to an embodiment of the present invention.

As shown in FIG. 2, the CMOS image sensor (CIS) of the embodiment of the present invention includes: a silicon substrate 200, the front side of the silicon substrate 200 is formed with a microlens 230, a metal interconnection layer 220 and an optical interaction region 210 The first surface 201 , the back side of the silicon substrate 200 is the second surface 202 . Wherein the optical interaction area 210 is located in the center of the first surface 201 above the silicon substrate 200, and a metal interconnection layer 220 is formed above the optical interaction area 210, and the microlens 230 array is placed on the metal interconnection layer 220, and the metal interconnection layer A first protection layer 235 is formed on the outer side of 220 . By making through-silicon vias 260 (TSVs) and redistribution layers (RDLs) that do not penetrate the silicon substrate 200 on the first surface 201, the I/Os around the optical interaction region 210 are connected to the silicon through the redistribution layer (RDL). Through vias 260 (TSVs). A passivation layer 265 is formed on the wall of the through-silicon via 260 (TSV), and the hole is filled by an electroplating process. And the second protection layer 240 with stepped protrusion or groove structure is fabricated on the redistribution layer (RDL) with polymer material. The silicon substrate 200 and the glass sheet 250 are bonded together through a polymer bonding glue 255 , and a cavity is formed between the glass sheet 250 and the silicon substrate 200 through exposure and development. By grinding and etching the second surface 202 of the silicon substrate 200 , the silicon substrate is thinned and the through silicon vias 260 (TSVs) are exposed. By making a circuit layer on the second surface 202 of the silicon substrate 200, the through-silicon via 260 (TSV) is connected to the pad pad 290, and a solder mask 280 (SMF) is made on the circuit layer and exposes the pad pad 290 to The circuit layer on the second surface 202 is protected. Solder balls 295 are formed on the pads 290 .

The manufacturing process of the CMOS image sensor of this embodiment will be described in detail below with reference to FIGS. 3( a ) to ( j ). 3( a ) to ( j ) are cross-sectional schematic diagrams of the manufacturing process of a CMOS image sensor drawn according to an embodiment of the present invention.

First, referring to FIG. 3( a ), a silicon substrate 200 is provided. The front side of the silicon substrate 200 is a first surface 201 for forming electronic devices, and the back side of the silicon substrate 200 is a second surface 202 . The figure includes: an optical interaction region 210 , a metal interconnection layer 220 and a first protection layer 235 . The optical interaction area 210 is located in the center of the first surface 201 of the silicon substrate 200, and a metal interconnection layer 220 is formed above the optical interaction area 210. The microlens 230 array is placed above the metal interconnection layer 220, and the metal interconnection layer 220 outside A first protection layer 235 is formed. There are a plurality of photosensitive diodes and a plurality of transistors (not shown in the figure) respectively correspondingly connected to the photodiodes in the optical interaction area 210 .

Referring next to FIG. 3( b ), a TSV hole 261 is etched on the first surface 201 of the silicon substrate.

This step includes the following steps: (a) coating a layer of photoresist on the first surface 201 of the silicon substrate by a glue spinner, and exposing and developing the photoresist to form an etching window at the position where holes need to be formed; (b ) to form the TSV hole 261 by using a dry etching process, and the dry etching process includes deep reactive ion etching (DRIE).

Referring next to FIG. 3( c ), a passivation layer 265 is formed in the TSV hole 261 and the front surface 201 of the silicon substrate.

The passivation layer 265 can be made by plasma chemical vapor deposition (PECVD), and the material of the passivation layer 265 can be oxide (such as silicon dioxide) or nitride (such as silicon nitride).

Next please refer to FIG. 3( d ), which exposes the I/Os on the periphery of the optical interaction area 210 .

By exposing and developing the passivation layer 265 deposited on the first surface 201 of the silicon substrate, an etching window is formed at the corresponding position of the peripheral I/O (not shown in the figure) of the optical region 210, and then a hole 225 is formed by dry etching to expose I/O at the periphery of the optical interaction area 210 .

Next, please refer to Figure 3(e), electroplating filling.

The filling of the TSV hole 261 and the hole 225 is completed by an electroplating process to form a through-silicon via 260 (TSV) structure, and the filling material can be a conductive substrate of metal or alloy material; The substrate is patterned to form a redistribution layer (RDL) for electrical connection from the I/Os at the periphery of the optical interaction region 210 to the through-silicon vias 260 (TSVs).

Referring next to FIG. 3( f ), a second protection layer 240 is formed on the first surface 201 of the silicon substrate and a microlens 230 is placed.

This step includes the following steps: (a) making a second protective layer 240 on the first surface 201 of the silicon substrate; (b) forming an etching window on the second protective layer 240 by exposure and development; (c) forming an etching window on the silicon substrate by etching 200 and the second protective layer 2240 of the bonding area of the glass sheet 250 to form a stepped protrusion or groove structure, by etching the top of the optical interaction area 210 and the metal interconnection layer 220 to form an optical opening groove for placing a micro lens 230; (d) fabricating an array of microlenses 230 within the optical opening groove.

Next please refer to FIG. 3( g ), the silicon substrate 200 is bonded to the glass sheet 250 .

This step includes the following steps: (a) performing pretreatment cleaning on the glass sheet 250, the pretreatment cleaning includes pickling neutralization, plasma cleaning, etc.; (b) forming a layer of polymer bonding glue 255 on the glass surface, and Exposing and developing the polymer bonding glue 255 to form the polymer bonding glue 255 with a cavity structure; (c) bonding the silicon substrate 200 to the glass sheet 250 through a bonding machine.

Next, referring to FIG. 3( h ), grinding and etching are performed on the second surface 202 of the silicon substrate.

This step includes the following steps: (a) grinding the second surface 202 of the silicon substrate to reduce the thickness of the silicon substrate 200 from 600 to 700 microns to about 100 to 150 microns; (b) grinding the second surface of the silicon substrate 202 performs stress-relieving plasma etching, so as to remove the internal stress in the silicon substrate 200 due to grinding, improve the warpage of the structure, and expose the through-silicon vias 260 (TSVs).

Next, referring to FIG. 3(i), the wiring layer on the second surface 202 of the silicon substrate is fabricated.

This step includes the following steps: (a) deposit an insulating layer 270 on the second surface 202 of the silicon substrate, and expose through-silicon vias 260 (TSVs) through exposure and development; (b) use physical vapor deposition on the surface of the insulating layer 270 (PVD) sputtering a conductive substrate of a metal or alloy, and patterning it by exposure and development to form a circuit layer and a pad pad 290, and connect the through-silicon via 260 (TSV) to the pad pad 290; (c) Forming a solder resist layer 280 (SMF) on the circuit layer of the second surface 202 of the silicon substrate and exposing the pad 290 .

Next, referring to FIG. 3(j), solder balls 295 are fabricated.

Solder balls 295 are formed on the pads 290 by a ball planting process.

The description of the embodiments of the invention has been made for the purpose of effectively illustrating and describing the invention, but by way of example only and should not be construed as limiting the scope of the invention as defined by the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Protection for the present invention therefore covers modifications within the spirit and scope of the invention as defined by the claims.

Claims (4)

1. A CMOS image sensor packaging structure is characterized in that: it comprises silicon substrate (200), and the front side of described silicon substrate (200) is formed with microlens (230), metal interconnection layer (220) and The first surface (201) of the optical interaction area (210), the back side of the silicon substrate (200) is the second surface (202); wherein the optical interaction area (210) is located on the first surface of the front side of the silicon substrate (200) In the center of (201), a metal interconnection layer (220) is formed above the optical interaction area (210), and the microlens (230) array is placed above the metal interconnection layer (220), outside the metal interconnection layer (220) A first protective layer (235) is formed; by making a through-silicon hole (260) and a redistribution layer that do not penetrate the silicon substrate (200) on the first surface (201), the I/O around the optical interaction area (210) O is connected to the through-silicon hole (260) through the redistribution layer; a passivation layer (265) is made on the hole wall of the through-silicon hole (260), and the hole is filled with an electroplating process; a polymer material is used to make a passivation layer on the redistribution layer The second protective layer (240) of stepped structure; the silicon substrate (200) and the glass sheet (250) are bonded together by polymer bonding glue (255), and the glass sheet (250) and the silicon substrate ( 200) is provided with a cavity formed by exposure and development; by grinding and etching the second surface (202) of the silicon substrate (200), the silicon substrate (200) is thinned to expose through-silicon holes (260); on the second surface (202) of the silicon substrate (200), make a circuit layer to connect the through-silicon hole (260) to the pad pad (290), make a solder resist layer (280) on the circuit layer and The pad pad (290) is exposed to protect the circuit layer on the second surface (202); solder balls (295) are formed on the pad pad (290). 2. A CMOS image sensor packaging structure according to claim 1, characterized in that: the stepped structure on the second protective layer (240) is a protrusion or a groove structure. 3. A method for manufacturing the CMOS image sensor packaging structure as claimed in claim 1, characterized in that: comprising the following steps: Step 1: Provide a silicon substrate; The silicon substrate includes a first surface formed with a micro lens, an integrated circuit IC and an optical interaction area, and a second surface opposite to the first surface; Step 2: etching TSV holes on the first surface of the silicon substrate; In this step, first coat a layer of photoresist on the front side of the silicon substrate, and form an etching window through exposure and development; use a dry etching process to form TSV holes, and the dry etching process includes deep reactive ion etching; Step 3: forming a passivation layer in the TSV hole and on the first surface of the silicon substrate; A passivation layer is formed in the TSV hole and on the front side of the silicon substrate by plasma chemical vapor deposition, and the material of the passivation layer is a polymer dielectric material; Step 4: Expose the I/O on the periphery of the optical interaction area; forming an etching window by exposing and developing the passivation layer deposited on the first surface of the silicon substrate, and exposing the I/O on the periphery of the optical interaction area by dry etching; Step 5: Electroplating and filling TSV to realize electrical interconnection; Fill the formed TSV holes and cover the first surface through the electroplating process, so that the through-silicon vias (TSVs) are connected with the I/Os on the periphery of the optical interaction area to form a redistribution layer (RDL) to realize electrical interconnection; Step 6: Form a protective layer and install the micro lens; When the second protective layer is formed on the first surface of the silicon substrate, the second protective layer with a stepped protrusion or groove structure is formed on the bonding area between the silicon substrate and the glass through exposure, development and etching processes; A micro-lens is placed above the metal interconnection layer on the first surface of the bottom; Step 7: Bond the silicon substrate to the glass; In this step, the polymer bonding glue is first coated on the glass surface that has been pre-treated and cleaned. The pre-treatment cleaning includes pickling neutralization, plasma cleaning, etc.; Form a cavity; finally, bond the silicon substrate to the glass by coating a layer of resin glue on the surface of the polymer bonding glue and using a bond and a machine; Step 8: Grinding and etching the second surface of the silicon substrate; In this step, the second surface of the silicon substrate is firstly ground and thinned; secondly, the second surface of the ground silicon substrate is subjected to stress relief plasma etching to remove the internal stress remaining in the wafer due to grinding, Reduce wafer warpage and expose TSVs; Step 9: making a circuit layer on the second surface of the silicon substrate; In this step, an insulating layer is first deposited on the back of the silicon substrate; then a layer of metal is sputtered and patterned to form a circuit layer and pad pad; finally, a layer of solder mask is coated on the circuit layer layer (SMF) and expose the pad and protect the formed lines; Step 10: Make solder balls; Solder balls are formed on the pads through a ball planting process. 4. The production method according to claim 3, characterized in that: in the seventh step, the polymer bonding glue is replaced by a dry film, and the dry film is composed of free resin, solvent, photosensitive compound and additive materials, at this time, the step of coating the adhesive on the surface of the polymer bonding adhesive is omitted to complete the bonding with the wafer, and the dry film used is directly bonded to the wafer without applying the adhesive Combined, reducing the process flow.