CN103000526B - A kind of electricallyerasable ROM (EEROM) and manufacture method - Google Patents

Abstract

The invention discloses an electric erasable read-only memory and a manufacturing method, which are used to improve the performance of the electric erasable read-only memory. The manufacturing method includes: covering a first floating gate oxide layer on a substrate embedded with a source and a drain; forming a floating gate on the first floating gate oxide layer through a patterning process, wherein the floating gate The top layer is covered with a protective layer; growing a second floating gate oxide layer on the sidewall of the floating gate covered with the protective layer; removing the protective layer covered by the top layer of the floating gate, and growing on the top layer of the floating gate A third suspended gate oxide layer; forming a control gate on the third suspended gate oxide layer to complete the electrically erasable read-only memory.

Description

An electrically erasable read-only memory and its manufacturing method

technical field

The invention relates to the technical field of semiconductor chips, in particular to an electrically erasable read-only memory and a manufacturing method.

Background technique

Electrically Erasable Programmable Read-Only Memory (EEPROM) is a memory chip whose data is not lost after power failure. In addition, EEPROM can erase stored data and reprogram.

As shown in FIG. 1 , the EEPROM device includes: a source 110 and a drain 120 embedded in a substrate 100 , a control gate 200 , and a floating gate 300 located between the substrate 100 and the control gate 200 . Wherein, the source 110 , the drain 120 , and the control gate 200 are all led out by an electrode; the floating gate 300 is not led out by an electrode, but is surrounded by an oxide, that is, the floating gate 300 is surrounded by a floating gate oxide layer.

The erasing and writing process of the above EEPROM device is realized by changing the voltage values on the control gate, drain and source. The specific process is: the control gate is connected to a high voltage, the drain and source are connected to a low voltage, and the charge is transferred from The drain flows to the floating gate to realize the writing process; the control gate is connected to a low voltage, the drain and the source are both connected to a high voltage, and the charge flows from the floating gate to the drain to realize the erasing process.

Since the floating gate is surrounded by a floating gate oxide layer, charges need to flow in the floating gate oxide layer during the erasing and writing process of the EEPROM device. Therefore, the floating gate oxide layer is a very critical structure in the EEPROM device. The quality determines the charge storage capacity on the floating gate and the reliability of the device.

Wherein, the thickness of the floating gate oxide layer between the floating gate and the control gate cannot be too thick, that is, the thickness of the oxide layer at the top of the floating gate cannot be too thick, because when data is written and erased, the top of the floating gate The thicker the oxide layer, the greater the voltage required, which will affect and limit the application range of the device. At the same time, the oxide layer around the floating gate should not be too thin, that is, the thickness of the oxide layer on the sidewall of the floating gate should not be too thin. The thinner the oxide layer on the sidewall of the floating gate, the easier it is for the charge stored on the floating gate to Leakage, so that the difference between the turn-on voltage of the device in the two states becomes smaller, and the logical distinction between "0" and "1" becomes smaller.

Due to the particularity of EEPROM devices, there are different performance requirements for the sidewall and top oxide layer of the floating gate. In the current EEPROM manufacturing process, the sidewall and top oxide layer of the floating gate are grown in the same process step. , can only set the same process conditions and technical parameters, it is difficult to realize the difference in thickness and performance between the oxide layer on the side wall of the floating gate and the oxide layer on the top of the floating gate, so the current process method largely limits the processing The process window of the process makes the control of the process more difficult.

Contents of the invention

Embodiments of the present invention provide an EEPROM and a manufacturing method for improving the performance of the EEPROM.

An embodiment of the present invention provides a method for manufacturing an electrically erasable read-only memory, including:

covering the first floating gate oxide layer on the substrate embedded with source and drain;

forming a floating gate on the first floating gate oxide layer through a patterning process, wherein the top layer of the floating gate is covered with a protective layer;

growing a second floating gate oxide layer on the sidewall of the floating gate covered with a protection layer;

removing the protective layer covering the top layer of the floating gate, and growing a third floating gate oxide layer on the top layer of the floating gate;

A control gate is formed on the third floating gate oxide layer to complete the electrically erasable read-only memory.

An embodiment of the present invention provides an electrically erasable read-only memory including: a substrate 100, a source 110 and a drain 120 embedded in the substrate 100, a control gate 200, and a floating gate 300, wherein,

There is a first floating gate oxide layer 410 between the floating gate 300 and the substrate 100;

The sidewall of the floating gate 300 has a second floating gate oxide layer 420;

There is a third floating gate oxide layer 430 between the floating gate 300 and the control gate 200 , wherein the thickness of the third floating gate oxide layer 430 is smaller than the thickness of the second floating gate oxide layer 420 .

In the embodiment of the present invention, the second floating gate oxide layer on the sidewall of the floating gate and the third floating gate oxide layer on the top of the floating gate are grown in two process steps, so that different process conditions can be set in the two process steps and technical parameters, so that the thickness of the oxide layer on the sidewall of the floating gate is different from the thickness of the top oxide layer, respectively adapting to the performance requirements of these two areas, ensuring the process window in the process of EEPROM device manufacturing, and effectively improving the device. Charge storage capability and expanded application range of programming voltage improve the performance of EEPROM devices.

Description of drawings

FIG. 1 is a schematic diagram of an axial cross-section of an EEPROM device in the prior art;

Fig. 2 is the flowchart of making EEPROM device in the embodiment of the present invention;

FIG. 3(a) is a schematic axial cross-sectional view of a device covering the first floating gate oxide layer in an embodiment of the present invention;

Figure 3(b) is a schematic axial cross-sectional view of a device deposited with a floating gate layer and a protective layer in an embodiment of the present invention;

Figure 3(c) is a schematic axial cross-sectional view of the etched device in an embodiment of the present invention;

Figure 3(d) is a schematic axial cross-sectional view of a device with a floating gate formed in an embodiment of the present invention;

3(e) is a schematic axial cross-sectional view of a device in which a second floating gate oxide layer is grown in an embodiment of the present invention;

Fig. 3 (f) is the axial sectional schematic diagram of the device that removes protective layer in the embodiment of the present invention;

3(g) is a schematic axial cross-sectional view of a device in which a third floating gate oxide layer is grown in an embodiment of the present invention;

FIG. 4 is a schematic axial cross-sectional view of an EEPROM device in an embodiment of the present invention.

detailed description

In the embodiment of the present invention, in the manufacturing process of the EEPROM device, the oxide layer on the side wall of the floating gate and the top oxide layer are grown in two process steps respectively. In this way, different process conditions and technical parameters can be set respectively, so that the side wall of the floating gate The thickness of the oxide layer is different from the thickness of the top oxide layer, respectively adapting to the performance requirements of these two regions, thereby ensuring the process window in the EEPROM device manufacturing process, and effectively improving the charge storage capacity of the device and expanding the programming. The application range of the voltage improves the performance of the EEPROM device.

In the embodiment of the present invention, a patterning (MASK) process is used to fabricate an EEPROM device, wherein the patterning process includes: masking, exposure, development, etching, stripping and other processes.

Referring to Figure 2, the process of making an EEPROM device includes:

Step 201: covering the first floating gate oxide layer on the substrate embedded with the source and the drain.

This step is consistent with the process in the prior art, and the material of the first floating gate oxide layer includes: polysilicon. In this way, a layer of polysilicon is deposited on the substrate embedded with the source and the drain, and the polysilicon can be oxidized to form the first suspension gate oxide layer.

Here, the axial cross-section of the device covering the first floating gate oxide layer is shown in FIG. 3( a ).

Step 202 : forming a floating gate whose top layer is covered with a protective layer on the first floating gate oxide layer through a patterning process.

In the prior art, the floating gate is directly formed on the first floating gate oxide layer, but in the embodiment of the present invention, the floating gate is formed on the first floating gate oxide layer, and the top layer of the floating gate is covered with a protective layer, The specific process includes:

Deposit a floating gate layer and a protective layer on the first floating gate oxide layer respectively, and apply photoresist, then, after exposing and developing the photoresist through a mask plate, the protection without photoresist protection will be removed respectively. layer and the floating gate layer are etched away to form a floating gate whose top layer is covered with a protective layer.

Here, the axial section of the device with deposited floating gate layer and protective layer is shown in Fig. 3(b). The material of the protection layer in the embodiment of the present invention includes: silicon nitride. The silicon nitride cannot be oxidized in air.

Apply photoresist, expose and develop the photoresist through a mask plate, and then etch away the protective layer and the floating gate layer without photoresist protection respectively. The cross section of the etched device is shown in the figure 3(c). Here, etching is generally dry etching. When the protective layer is made of silicon nitride, gas containing fluorine ions is used to etch the silicon nitride serving as the protective layer under the action of an electric field. The main gas components for etching the floating grid are chlorine gas and hydrogen bromide gas, these gases will etch the floating grid without photoresist protection and take away the residue after etching.

The remaining photoresist is stripped to form a floating gate with a top layer covered with a protective layer. The cross-section of the device with the floating gate formed is shown in Fig. 3(d).

Step 203: growing a second floating gate oxide layer on the sidewall of the floating gate covered with the protection layer.

Due to the particularity of the EEPROM device, there are different performance requirements for the sidewall and top oxide layer of the floating gate. Here, a second floating gate oxide layer is grown on the sidewall of the floating gate covered with the protection layer. The material of the second suspended gate oxide layer includes: polysilicon. The polysilicon is oxidized to form a second floating gate oxide layer.

Generally, the thickness of the second suspended gate oxide layer is greater than or equal to 1000 angstroms, and the height of the second suspended gate oxide layer is less than or equal to the height of the suspended gate. Here, the axial section of the device grown with the second suspended gate oxide layer is shown in FIG. 3( e ), wherein the second suspended gate oxide layer has a thickness of 1000 angstroms and a height equal to that of the suspended gate.

Step 204: removing the protective layer covering the top layer of the floating gate, and growing a third floating gate oxide layer on the top layer of the floating gate.

Since the floating gate is surrounded by the floating gate oxide layer, the protection layer covering the top layer of the floating gate must be removed. The axial section of the device with the protective layer removed is shown in Fig. 3(f).

After the protective layer is removed, a third floating gate oxide layer is grown on the top layer of the floating gate. The material of the third floating gate oxide layer includes: polysilicon. The polysilicon is oxidized to form a third floating gate oxide layer. Here, process conditions and technical parameters may be set according to the requirements of the EEPROM device for the floating gate oxide layer on the top layer of the floating gate.

Generally, the thickness of the third suspended gate oxide layer is smaller than the thickness of the second suspended gate oxide layer. Here, the axial section of the device grown with the third floating gate oxide layer is shown in Fig. 3(g). The thickness of the third floating gate oxide layer is 600 angstroms.

Step 205: Form a control gate on the third floating gate oxide layer to complete the EEPROM.

The process in this step is the same as that in the prior art, so it will not be described in detail.

The EEPROM device can be produced through the above process. Since the second floating gate oxide layer on the sidewall of the floating gate and the third floating gate oxide layer on the top of the floating gate are grown in two process steps, different process conditions and technical parameters can be set in the two process steps, so that The thickness of the second floating gate oxide layer is greater than that of the third floating gate oxide layer, so that it is suitable for the particularity of EEPROM devices, ensures the process window in the manufacturing process of EEPROM devices, and effectively improves the charge storage capacity of the device and expands programming. The application range of the voltage improves the performance of the EEPROM device.

The EEPROM device manufactured through the above process, as shown in FIG. 4 , includes: a substrate 100, a source 110 and a drain 120 embedded in the substrate 100, a control gate 200, and a floating gate 300, wherein,

There is a first floating gate oxide layer 410 between the floating gate 300 and the substrate 100;

The sidewall of the floating gate 300 has a second floating gate oxide layer 420;

There is a third floating gate oxide layer 430 between the floating gate 300 and the control gate 200 , wherein the thickness of the third floating gate oxide layer 430 is smaller than the thickness of the second floating gate oxide layer 420 .

Preferably, the thickness of the second suspended gate oxide layer is greater than or equal to 1000 angstroms, and the thickness of the third suspended gate oxide layer is 600 angstroms.

The material of the first suspended gate oxide layer, the second suspended gate oxide layer, and the third suspended gate oxide layer includes: polysilicon. In this way, oxides can be formed by air oxidation.

In the embodiment of the present invention, in the process of manufacturing the EEPROM device, the second floating gate oxide layer on the sidewall of the floating gate is first grown, and then the third floating gate oxide layer on the sidewall of the floating top layer is grown, which is divided into two parts. One process step completes the oxide layer of the sidewall of the floating gate and the top layer, and different process conditions and technical parameters can be set in the two process steps respectively, so that the thickness of the second floating gate oxide layer is greater than the thickness of the third floating gate oxide layer, thereby Applicable to the particularity of EEPROM devices, ensuring the process window in the manufacturing process of EEPROM devices, effectively improving the charge storage capacity of devices and expanding the application range of programming voltage, and improving the performance of EEPROM devices.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (7)

1. make a method for electricallyerasable ROM (EEROM), it is characterized in that, comprising:

The substrate that embedded in source electrode and drain electrode covers the first suspended gate oxide layer;

In described first suspended gate oxide layer, form suspended grid by patterning processes, wherein, the top layer of described suspended grid is coated with protective layer;

Be coated with the sidewall growth second suspended gate oxide layer of described suspended grid of protective layer;

Remove the protective layer that described suspended grid top layer covers, and in the top layer growth regulation three suspended gate oxide layer of described suspended grid;

Formation control grid in described 3rd suspended gate oxide layer, completes electricallyerasable ROM (EEROM);

Wherein, the thickness of described 3rd suspended gate oxide layer is less than the thickness of described second suspended gate oxide layer.

2. the method for claim 1, is characterized in that, describedly in described first suspended gate oxide layer, forms suspended grid by patterning processes and comprises:

Described first suspended gate oxide layer deposits suspended grid layer and protective layer respectively, and smears photoresist;

By mask plate, described photoresist exposed and after development treatment, respectively the protective layer not having photoresist to protect and suspended grid layer etched away, forming the suspended grid that top layer is coated with protective layer.

3. the method for claim 1, is characterized in that, the thickness of described second suspended gate oxide layer is greater than the thickness of described 3rd suspended gate oxide layer.

4. the method as described in claim 1 or 3, is characterized in that, the thickness of described second suspended gate oxide layer is more than or equal to 1000 dusts, and the thickness of described 3rd suspended gate oxide layer is 600 dusts.

5. method as claimed in claim 1 or 2, it is characterized in that, the height of described second suspended gate oxide layer is less than or equal to the height of described suspended grid.

6. the method for claim 1, is characterized in that, described first suspended gate oxide layer, the second suspended gate oxide layer, and the 3rd suspended gate oxide layer is formed through peroxidating by polysilicon.

7. method as claimed in claim 1 or 2, it is characterized in that, the material of described protective layer comprises: silicon nitride.