CN102999459A - Communication method of silicon wafer testing machine and built-in self test (BIST) module - Google Patents
Communication method of silicon wafer testing machine and built-in self test (BIST) module Download PDFInfo
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- CN102999459A CN102999459A CN2011102671007A CN201110267100A CN102999459A CN 102999459 A CN102999459 A CN 102999459A CN 2011102671007 A CN2011102671007 A CN 2011102671007A CN 201110267100 A CN201110267100 A CN 201110267100A CN 102999459 A CN102999459 A CN 102999459A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
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- 238000004891 communication Methods 0.000 title claims abstract description 19
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Abstract
The invention discloses a communication method of a silicon wafer testing machine and a built-in self test (BIST) module. Three independent serial communication signal lines, namely an instruction and data line (TDIO) for transmitting instruction and data, a clock line (TCLK) for transmitting clock signals and a starting line (STROBE) for transmitting starting signals, are arranged between the silicon wafer testing machine and the BIST module. When a receiving side receives the starting signals transmitted by the starting line (STROBE), the next instruction or data are about to be transmitted, and a receiving side needs to prepare for receiving the instruction or data. The communication method only needs three signals lines due to the fact that interface control signals are less, further adopt the independent starting line, and can firstly transmit a starting signal before each instruction or data are transmitted and greatly facilitates debugging in testing.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) and make the field, particularly relate to the measuring technology of nonvolatile memory (NVM, Non-Volatile Memory).
Background technology
IP kernel (IP core, Intellectual Property core, intellectual property core) be that those have been verified, can reuse, have certain IC that determines function (integrated circuit) module.NVMIP nuclear refers to have the IC module of NVM function.
What at present the NVM IP kernel is tested employing is BIST (Built-in Self Test, built-in self-test) circuit, and this BIST circuit connects respectively silicon test board and NVM IP kernel, is used for described NVM IP kernel is tested.
Existing silicon chip (wafer) tester table is when carrying out general test, and silicon chip is placed in the tester table, is connected to by the probe of special use on the weld pad (PAD) of nude film (DIE) of tested chip on the silicon chip.The silicon test board has following characteristics: one, test environment is good, and signal disturbs little.Two, tester table can only send data to by the waveform that preliminary election sets the input port of chip under test; Three, the tester table waveform that can only receive output port shows, can not make feedback according to the signal that receives.
For the NVM IP kernel is tested, the silicon test board must connect with the BIST circuit by certain interface, and sends instruction, and the signal waveform on the monitoring interface bus is tested.At present communicating by letter between silicon test board and the BIST circuit can be adopted some general serial communication protocols, such as RS-232 agreement, I2C (Inter-Integrated Circuit) agreement, SPI (Serial PeripheralInterface, Serial Peripheral Interface (SPI)) agreement etc.These serial communication protocols have advantage and range of application separately.But all there is certain defective for communicating by letter between silicon test board and the BIST circuit.
Take the I2C agreement as example, although its signal wire is few, when a large amount of instructions transmitted, the silicon test board will be debugged (DEBUG) by the signal on the universal serial bus, and relatively difficulty confirms that the starting and ending point of instruction is very inconvenient.
Summary of the invention
Technical matters to be solved by this invention provides the communication means between a kind of silicon test board and the BIST module, the method can realize all test operations to the NVM IP kernel with less interface signal and simple instruction, and guarantees the reliability of test operation and debugging.
For solving the problems of the technologies described above, the communication means of silicon test board of the present invention and BIST module is, three independently serial communication signal lines are set between silicon test board and BIST module, is respectively:
---instruction and data line TDIO, transfer instruction and data;
---clock line TCLK, transmit clock signal;
---initial STROBE, transmission commencing signal;
When the take over party receives the commencing signal of the upper transmission of initial STROBE, just represent that next instruction or data are about to transmission, thereby the take over party carries out the preparation that receives this instruction or data.
Further, described method adopts the instruction set of layering.Instruction set is divided into three layers according to test operating procedure: top level command, middle layer instruction, bottom instruction.Article one, top level command can realize the operation that some middle layer instructions and/or bottom instruction realize.Article one, the middle layer instruction can realize the operation that some bottom instructions realize.Top level command is used for proper testing, and middle layer instruction and bottom instruction are used for the debugging of test.
Communication means of the present invention has following advantage:
One, interface control signal is few, only needs three signal wires;
Its two, the independently initial STROBE of employing begins to send first a commencing signal before the transmission in every instruction or data, debugging when greatly facilitating test.
Its three, adopt the order structure of layering, can greatly make things convenient for the layering debugging of test process.
Description of drawings
Fig. 1 is the annexation synoptic diagram between silicon test board of the present invention and the BIST module;
Fig. 2 is the synoptic diagram of institute's signal transmission of three signal wires among Fig. 1.
Description of reference numerals among the figure:
1 is the silicon test board; 2 is the BIST module.
Embodiment
See also Fig. 1, the communication means of silicon test board of the present invention and BIST module is, three independently serial communication signal lines are set between silicon test board 1 and BIST module 2, is respectively:
---clock line TCLK, transmit clock signal;
---initial STROBE, transmission commencing signal;
---instruction and data line TDIO, transfer instruction and data;
When the take over party receives the commencing signal of the upper transmission of initial STROBE, just represent that next instruction or data are about to transmission, thereby the take over party carries out the preparation that receives this instruction or data.
Like this, communication means of the present invention only adopts three signal wires just can realize that the silicon test board to the control of BIST module, has satisfied the few requirement of test signal quantity.
In a specific embodiment, the present invention has also designed a kind of 32 fixed-size commands.This order format is comprised of 1 CMD territory, 1 WR territory, 5 TARGET territory, 9 ADDR territory, 16 DAT territory.Wherein the CMD territory is data and instruction flag position, when this position is 1, represent that the DAT territory is order code, otherwise the DAT territory is the data of transmission.The WR territory is the read-write operation zone bit, and when this position is 1, presentation directives carries out write operation; Be 0, presentation directives carries out read operation.The inner submodule coding of BIST of this instruction is carried out in the TARGET territory for expression.The ADDR territory represents the address value of internal register, and instruction can conduct interviews to different registers according to the setting of address value.The DAT territory is order code when CMD=1, and is the data of transmission when CMD=0.
See also Fig. 2, this is the synoptic diagram of the signal that transmits on three signal wires among Fig. 1.For example, clock signal is square wave, and is effective at rising edge; Commencing signal is square wave, and is effective when high level.When the rising edge in clock signal detects commencing signal, begin to transmit next instruction or data at the rising edge of next clock signal.Presumptive instruction or data are 32 regular lengths among Fig. 2, and suppose that every bit width is 1 TCLK clock signal.After instruction or data transmission are finished, need the time if instruction is carried out, then during internal work busy (BUSY), TDIO is set to low level by the BIST module, forbids the input of external command or data.
In the communication means of the present invention, instruction is adopted dual mode to the control of BIST module: one, directly control; Two, indirectly control.
Directly control mode is that direct steering order is read and write register, directly controls the interface signal of NVM IP kernel, the once variation of a signal of every instruction control.This is a kind of control mode of the bottom.Any test and operation to the NVM IP kernel all can adopt this mode to finish.The advantage of this mode is that instruction is simple, and control is convenient, realizes reliably guaranteeing can both realize all operations of NVM IP kernel; Shortcoming is to need a lot of bar instructions could realize a shirtsleeve operation.
The indirectly control mode then adopts middle layer and top level command.The middle layer instruction can be controlled a series of actions of some signal wires, to realize that what it was finished is a certain operation that some bottom instructions just can be finished to the operation of a certain specific time sequence of NVM IP kernel.Top level command then can be finished a certain specific function that execution is united in the instruction of some middle layers and bottom instruction, is decomposed into each middle layer instruction and the bottom instruction is carried out in the BIST inside modules.
Once complete data programing with NVM device IP is operating as example, and programming can be divided into following steps: 1, clear internal data buffer zone; 2, wipe designated storage area; 3, write data to the data buffer; 4, buffer data is write designated storage area.Here, four top level command have been defined, clear buffer zone instruction, erase operation instruction, the instruction of program storage district.Wherein, the process such as the instruction of program storage district is divided into again pre-programmed, deeply wipes, soft programming, detection of electrical leakage realizes these subprocess so defined again four middle layer instructions.
In the instruction of reality was carried out, only needing to send top level command was the execution that the instruction of program storage district will be finished a certain operation overall process.The middle layer instruction is used for when top level command goes wrong, and carries out the layering debugging and uses.The bottom instruction then is used for when the middle layer instruction can't be carried out or can't the orientation problem place, to the further segmentation realization of middle layer command operating.The classification debugging that this instruction hierarchy is conducive to test, and guarantee the carrying out of test and the location of problem.
Direct steering order (bottom instruction), middle layer instruction and top level command, this hierarchy is presented as the internal separation of BIST module physically, shows as different TARGET field codes in instruction.
The hierarchy of instruction set both can have been realized the single-step operation control to single signal, also can operate by the series of complex that single instruction is finished the NVM IP kernel.
Be the preferred embodiments of the present invention only below, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. the communication means of a silicon test board and BIST module is characterized in that, three independently serial communication signal lines are set between silicon test board and BIST module, is respectively:
---instruction and data line (TDIO), transfer instruction and data;
---clock line (TCLK), transmit clock signal;
---initial (STROBE), transmission commencing signal;
When the take over party receives the commencing signal of the upper transmission of initial (STROBE), just represent that next instruction or data are about to transmission, thereby the take over party carries out the preparation that receives this instruction or data.
2. the communication means of silicon test board according to claim 1 and BIST module, it is characterized in that, after the take over party receives the instruction of instruction and data line (TDIO) transmission, if carrying out, instruction needs the time, then when this instruction process, the BIST module is forbidden this instruction and data line (TDIO), thereby forbids other instructions or data transfer.
3. the communication means of silicon test board according to claim 1 and BIST module is characterized in that, adopts the instruction set of layering; All instructions are divided into three levels: top layer, middle layer and bottom;
Article one, the operation that realizes of top level command is realized by one or more middle layer instruction and/or bottom instruction;
Article one, the instruction operation that realizes in middle layer is realized by one or more bottom instruction.
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| CN2011102671007A CN102999459A (en) | 2011-09-09 | 2011-09-09 | Communication method of silicon wafer testing machine and built-in self test (BIST) module |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212554A (en) * | 1990-12-31 | 1993-05-18 | Thomson Consumer Electronics, Inc. | Digital method and apparatus for evaluating a frequency parameter of an if signal |
| CN1828553A (en) * | 2005-04-13 | 2006-09-06 | 威盛电子股份有限公司 | System on Chip and Test/Debugging Method Applied thereto |
| CN101382915A (en) * | 2008-10-23 | 2009-03-11 | 北京中星微电子有限公司 | Software debugging system and debugging method |
-
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- 2011-09-09 CN CN2011102671007A patent/CN102999459A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212554A (en) * | 1990-12-31 | 1993-05-18 | Thomson Consumer Electronics, Inc. | Digital method and apparatus for evaluating a frequency parameter of an if signal |
| CN1828553A (en) * | 2005-04-13 | 2006-09-06 | 威盛电子股份有限公司 | System on Chip and Test/Debugging Method Applied thereto |
| CN101382915A (en) * | 2008-10-23 | 2009-03-11 | 北京中星微电子有限公司 | Software debugging system and debugging method |
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