CN102999310A - Novel chip transistor array method - Google Patents
Novel chip transistor array method Download PDFInfo
- Publication number
- CN102999310A CN102999310A CN2012105425278A CN201210542527A CN102999310A CN 102999310 A CN102999310 A CN 102999310A CN 2012105425278 A CN2012105425278 A CN 2012105425278A CN 201210542527 A CN201210542527 A CN 201210542527A CN 102999310 A CN102999310 A CN 102999310A
- Authority
- CN
- China
- Prior art keywords
- transistor
- district
- transistors
- bit location
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a novel chip transistor array method, belonging to the field of chip design. According to the method, a processor further has the multi-system operational capability, i.e. the binary system, the decimal system, the twenty-centesimal system and the like without the code conversion. The novel chip transistor array method has the embodiment that six transistors are combined into a bit cell transistor, the bit cell transistor is internally divided into a low region, a middle region and a high region, four transistors are arranged in the lower region for representing 4 digits, one is carried into the middle region when 5 is up, one transistor is arranged in the middle region for representing the digit 5, the middle region is combined with the low region for representing the digits of 0-9, one is carried into the high region when ten is up, one transistor is arranged in the high region for representing 10, the high region is combined with the low region and the middle region for representing the digits of 0-19, one is carried into a higher region when twenty is up, the bit cell transistor can represent the digits of 0-19 and a 32-bit array, and the data are expressed as 20<32>, and the arithmetic operation is suitable for the rule of calculation with an abacus.
Description
Technical field
The present invention relates to a kind of novel chip transistor array method, traditional die has been overturned in the application of especially rechoning by the abacus rule, belongs to the chip design field.
Technical background
The development of computing machine is mainly reflected in the development of the little processing of its core component, in more than 20 year, on the chip integrated number of transistors by 2300 surges to tens million of, founder Gordon mole of Moore's Law was also once foretold, Moore's Law is about to reach capacity, so we are badly in need of developing new road, improve chip speed and computing power, satisfy social needs.
Summary of the invention
The object of the present invention is to provide a kind of new transistor array method, make processor not need code conversion, also have multi-system, comprise scale-of-two, the arithmetic capability of decimal system binary-coded decimal etc., identical in production technology, under the identical situation of array word length figure place, the multiplication of novel chip arithmetic capability, data throughout promotes hundreds of times.
In order to achieve the above object, the invention provides a kind of new transistor array method, this transistor array method is as follows:
The arithmetical unit of 2 of array word lengths on substrate, make altogether 6 transistors, per three transistors form 1 bit location transistor, are divided into a position, ten 2 bit location transistors, 2 in three transistors in each bit location transistor divide low district into, and 1 divides high district into.
Character representation: the 1st group: 2 bit location transistors are not opened, and expression 00 equals numeral 0,1 transistor in low district, individual position is opened, and expression 01 equals numeral 1,2 transistors in low district, individual position are opened, and expression 02 equals numeral 2,1 transistor in individual high district, position is opened, and expression 03 equals numeral 3,1 transistor in high district adds 1 transistor in low district to be opened, and expression 04 equals numeral 4,1 transistor in high district adds 2 transistors in low district to be opened, and expression 05 equals numeral 5;
The 2nd group: 1 transistor in ten low districts is opened, and expression 10 equals numeral 6,2 transistors are opened, and expression 20 equals numeral 7,1 transistor in high district is opened, and expression 30 equals numeral 8,1 transistor in high district adds 1 transistor in low district and opens, expression 40 equals numeral 9, and 1 transistor in high district adds 2 transistors in low district and opens, expression 50 equals numeral 10;
The 3rd group: 1 transistor in ten low districts is opened, 1 transistor in low district, individual position is opened, expression 11 equals 1 transistor in 11, ten low districts of numeral and opens, 2 transistors in low district, individual position are opened, expression 12 equals 1 transistor in 12, ten low districts of numeral and opens, 1 transistor in individual high district, position is opened, expression 13 equals 1 transistor in 13, ten low districts of numeral and opens, 1 transistor in individual high district, position adds 1 transistor in low district and opens, expression 14 equals that 1 transistor in 14, ten low districts of numeral is opened, 3 transistors in individual position are opened entirely, expression 15 equals numeral 15;
The 4th group: 2 transistors in ten low districts are opened, 1 transistor in low district, individual position is opened, expression 21 equals 2 transistors in 16, ten low districts of numeral and opens, 2 transistors in low district, individual position are opened, expression 22 equals 2 transistors in 17, ten low districts of numeral and opens, 1 transistor in individual high district, position is opened, expression 23 equals 2 transistors in 18, ten low districts of numeral and opens, 1 transistor in individual high district, position adds 1 transistor in low district and opens, expression 24 equals that 2 transistors in 19, ten low districts of numeral are opened, 3 transistors in individual position are opened entirely, expression 25 equals numeral 20;
The 5th group: 1 transistor in ten high districts is opened, 1 transistor in low district, individual position is opened, expression 31, equal 1 transistor in 21, ten high districts of numeral and open, 2 transistors in low district, individual position are opened, expression 32, equal 1 transistor in 22, ten high districts of numeral and open, 1 transistor in individual high district, position is opened, expression 33, equal that numeral 23, ten high districts 1 transistor is opened, 1 transistor in individual high district, position adds 1 transistor in low district and opens expression 34, equal numeral 24,1 transistor in ten high districts is opened, 3 transistors in individual position are opened entirely, and expression 35 equals numeral 25;
The 6th group: 1 transistor in ten high districts adds 1 transistor in low district and opens, No. 1 transistor in individual position is opened, expression 41, equal numeral 26,1 transistor in ten high districts adds 1 transistor in low district and opens, 2 transistors in low district, individual position are opened, expression 42, equal numeral 27,1 transistor in ten high districts adds 1 transistor in low district and opens, 1 transistor in individual high district, position is opened, expression 43, equaling numeral 28, ten high districts 1 transistor adds 1 transistor in low district and opens, 1 transistor in individual high district, position adds 1 transistor in low district and opens expression 44, equal numeral 29,1 transistor in ten high districts adds 1 transistor in low district and opens, 3 transistors in individual position are opened entirely, and expression 45 equals numeral 30;
The 7th group: ten 3 transistors are opened entirely, and No. 1 transistor in individual position is opened, and expression 51 equals numeral 31, ten 3 transistors are opened entirely, and No. 2 transistors in individual position are opened expression 52, equal 32, ten 3,2, No. 1 transistors of numeral, No. 3 transistors in individual position are opened, expression 53 equals 33, ten 3 transistors of numeral and entirely opens, 3, No. 2 transistors in individual position are opened, and expression 54 equals numeral 34, ten 3 transistors are opened entirely, 3 transistors in individual position are opened entirely, and expression 55 equals numeral 35; 00 ~ 55, totally 36 states, formula is: bit location transistor state and that multiply by bit location transistor state and, that is: 52.More represented word length figure place state, data be more, and such as 32 of arrays, data representation is 532.
The transistorized primary arithmetic facts computing of bit location is suitable for the rechoning by the abacus rule, and on the example one one, the transistor in low district is opened one, on two two, opens 1 again; On three three, high district opens 1 transistor, and 2 transistors in low district close; The word length multidigit, and 5 transistors are arranged in the bit location transistor, divide 2 districts into, use the rechoning by the abacus rule to need not conversion, such as 4 transistors in low district, 1 transistor in high district, 4 add 1, use the rechoning by the abacus rule: five go four once, high district transistor is opened, and 4 transistors in low district close; 9 add 1, use the rechoning by the abacus rule: one goes nine to advance one, and individual bit transistor closes, and ten low districts open 1 transistor.Multiplication: 9 take advantage of 7 to be 63, and the transistorized low district of bit location of individual position opens 3 transistors, and ten low districts open 1 transistor and a high position is opened 1 transistor; Except rule is opposite, the transistorized low district of bit location, individual position opens 2 transistors, and high district opens 1.
The present invention compared with prior art has following benefit.Identical with traditional die machine word-length figure place, data throughout is its several times 232:1032; The decimal system, man-machine interaction simple, intuitive are adopted in arithmetical operation; Numeral need not code conversion, has effectively shortened calculation process, so arithmetic speed is faster.
Used the rechoning by the abacus rule in the arithmetical operation of the present invention, gone on the world for Chinese culture and have extremely long-pending impetus.
What utilize that the present invention is born is chip, the computer that a kind of Chinese have the A to Z of property right, and economic benefit, the social effect that can produce are huge.
Description of drawings
Fig. 1 is the bit location transistor schematic that 3 transistors form;
Fig. 2 is the bit location transistor schematic that 6 transistors form;
Fig. 3 is 6 layers of 6 transistor stacks, the three-dimensional bit location transistor schematic of composition;
Specific implementation method
Following according to Fig. 2, Fig. 3, specify preferred embodiment of the present invention.
As described in Figure 2, a kind of novel chip transistor array method is that 6 transistors are combined into a bit location transistor, is divided into low district, Zhong Qu He Gao district in the bit location transistor, 4 transistors in low district, 1 transistor in middle district, 1 transistor in high district; 4 transistors in low district represent 4 numbers, meet 5 Xiang Zhong districts to advance 1,1 transistor in middle district represents 5, and low district combination expression 0 ~ 9, meets 10 Xiang Gao districts to advance 1,1 transistor in high district represents 10, high district and low, middle district combination expression 0 ~ 19 meet 20 to advance 1 to ten, and this bit location transistor can represent 0 ~ 19 number, 32 bit arrays, data are expressed as 2032 kinds.
As described in Figure 3, a kind of novel chip transistor array method is with 6 layers of single transistor stacks, the bit location transistor that forms, every layer of transistor is divided into low district, Zhong Qu He Gao district in the bit location transistor, 4 transistors in low district, 1 transistor in middle district, 1 transistor in high district; 4 transistors in low district represent 4 numbers, meet 5 Xiang Zhong districts to advance 1,1 transistor in middle district represents 5, and low district combination expression 0 ~ 9, meets 10 Xiang Gao districts to advance 1,1 transistor in high district represents 10, expression 0 ~ 19 is firmly closed in high district and low, middle district, meets 20 to advance 1 to ten, and this bit location transistor can represent 0 ~ 19 number, 32 bit arrays are 20 systems, and data are expressed as 2032 kinds.
The transistorized arithmetical operation of bit location is suitable for the rechoning by the abacus rule, only uses He Zhong district, low district during the primary arithmetic facts computing, high district need not, as on one one, the low transistor of distinguishing is opened one, on two two, opens 1 again; 4 add 1, are five to go four with the rechoning by the abacus rule, and middle district transistor is opened, and 4 transistors in low district close; 9 add 1, are nine to advance one with the rechoning by the abacus rule, and individual bit transistor closes, and ten low districts open 1 transistor.Multiplication: 9 take advantage of 7 to be 63, and the low district of the bit location transistor of individual position opens 3 transistors, and ten low districts open 1 transistor He Zhong district and open 1 transistor; Except rule is opposite, the low district of the bit location transistor of individual position opens 2 transistors, and middle district opens 1.
During compatible 2 system of bit location transistor, the transistorized subregion of cancellation bit location, controller is divided into 6 operation independent devices with 6 transistors, so can quick compatible traditional software.
A kind of binary-coded decimal chip in sum, with the scale-of-two chip not in same relatively classification, utilizing the computer of its exploitation is apparent for the economic benefit that society drives.
Although content of the present invention has been done detailed introduction by above preferred embodiment; above-mentioned description should not be considered to limitation of the invention; design centesimal system chip also is not difficult after having read foregoing, so protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. a novel chip transistor array method it is characterized in that 3 above transistors are combined into a bit location transistor.
2. described a kind of novel transistor array approach according to claim 1 it is characterized in that dividing low district, high district, a plurality of district according to the number of transistors in the bit location transistor the upper high-order carry in low district.
3. according to claim 1,2 is described, a kind of novel transistor array approach, it is characterized in that the transistorized numeral mode of described bit location is, 2 in three transistors in the bit location divide low district into, and 1 divides high district into, and three transistor contract fullys represent 0, low district opens 1 transistor and represents 1, low district opens 2 transistors and opens expression 2, and high district opens 1 transistor and represents 3, and high district opens 1 transistor and low district and opens 1 transistor and represent 4, three transistors are opened expression 5 entirely, greater than 5 to more high-order carry, 6 transistors are arranged in the bit location, can divide into low, in, high 3 districts, 4 transistors in low district, in, each 1 transistor of high district, 4 transistors in low district, expression 0～4, meet 5 Xiang Zhong district carries, middle district, the combination of low district, 10 Xiang Gao district carries are met in expression 0～10, high district, middle district, the combination of low district, expression 0～19 meets 20 to more high-order carry, and the number of transistors in the bit location is more, more represented subregion data are more.
4. according to claim 1,2,3 described, a kind of novel transistor array approach, it is characterized in that described on chip array multidigit bit location transistor, 2 of word lengths have 3 transistors in the bit location, 2 divide low district and 1 into and divide high the district into, each bit location transistor represents 0～5,6 characters, 6
2Totally 36 data, mode is 00～55, and 6 transistors are arranged in the bit location, divides basic, normal, high 3 districts into, 4 transistors in low district, each 1 transistor of middle and high district, each bit location transistor represents 0～19,20 characters, 20
2Totally 400 data, the word length figure place is more, and the number of transistors in the bit location is more, more represented subregion data are more.
5. according to claim 1,2,3,4 is described, a kind of novel transistor array approach, it is characterized in that described on chip the array multidigit, 5 above transistors are arranged in each bit location transistor, 1 transistor divides high district into, 4 transistors divide low district into, and representative digit decimally uses that the computing of rechoning by the abacus rule adds, subtracts, multiplication and division, square root.
6. according to claim 1,2 described, a kind of novel transistor array approach, it is characterized in that described bit location transistor be planar alignment on its substrate, serial or parallel connection is geometric.
7. according to claim 1,2 described, it is characterized in that described bit location transistor is single transistor one stacked one deck, superpose 3 layers, multilayer, and serial or parallel connection becomes a bit location transistorized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105425278A CN102999310A (en) | 2012-12-14 | 2012-12-14 | Novel chip transistor array method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105425278A CN102999310A (en) | 2012-12-14 | 2012-12-14 | Novel chip transistor array method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102999310A true CN102999310A (en) | 2013-03-27 |
Family
ID=47927923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105425278A Pending CN102999310A (en) | 2012-12-14 | 2012-12-14 | Novel chip transistor array method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102999310A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85104133A (en) * | 1985-01-11 | 1986-08-27 | 株式会社日立制作所 | Arithmetic operator and arithmetic operation circuit |
| CN1062804A (en) * | 1990-12-29 | 1992-07-15 | 赵锐 | Reel changing and digital lighting display card |
| EP0741354A2 (en) * | 1995-04-11 | 1996-11-06 | Canon Kabushiki Kaisha | Multi-operand adder using parallel counters |
| CN102088293A (en) * | 2010-12-24 | 2011-06-08 | 财团法人交大思源基金会 | Digital-to-analog converter |
-
2012
- 2012-12-14 CN CN2012105425278A patent/CN102999310A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85104133A (en) * | 1985-01-11 | 1986-08-27 | 株式会社日立制作所 | Arithmetic operator and arithmetic operation circuit |
| CN1062804A (en) * | 1990-12-29 | 1992-07-15 | 赵锐 | Reel changing and digital lighting display card |
| EP0741354A2 (en) * | 1995-04-11 | 1996-11-06 | Canon Kabushiki Kaisha | Multi-operand adder using parallel counters |
| CN102088293A (en) * | 2010-12-24 | 2011-06-08 | 财团法人交大思源基金会 | Digital-to-analog converter |
Non-Patent Citations (8)
| Title |
|---|
| C.MARCHAL: "记数法的简史及展望", 《自然杂志》 * |
| FRANK G.SOLTIS 著: "《罗彻斯特城堡－IBM e Server i系列技术解密 2003年8月第1版》", 31 August 2003 * |
| 周佩德，等: "《现代计算机基础（修订版)1998年6月第2版》", 31 July 2001 * |
| 周振章: "《计算技术 1996年6月第3版 2001年2月第14次印刷》", 28 February 2001 * |
| 张启斌: "《世界华人一般性科学论坛论文集 2005年第1卷》", 31 January 2007 * |
| 李伟智主编: "《神秘的热带丛林——玛雅 2006年6月第1版》", 30 June 2006 * |
| 王青建: "数字与数码", 《辽宁师范大学学报（自然科学版）》 * |
| 靖玉树: "中国心算记数方法和心算发展管见", 《珠算与珠心算》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103077183B (en) | A kind of data lead-in method and its system of distributed sequence list | |
| CN103929187B (en) | Anti-interference matrix information encoding and decoding method for merchandise outer packaging | |
| CN104112011A (en) | Method and device for extracting mass data | |
| CN101504599A (en) | Special instruction set micro-processing system suitable for digital signal processing application | |
| Salman et al. | A comparative study of energy big data analysis for product management in a smart factory | |
| CN106843803A (en) | A kind of full sequence accelerator and application based on merger tree | |
| CN102999310A (en) | Novel chip transistor array method | |
| CN102253920B (en) | Fully-interconnected route structure dynamically-reconfigurable data processing method and processor | |
| CN107423023A (en) | A kind of 16 × 16 digit redundancy decimal multipliers | |
| CN102436545B (en) | Diversity analysis method based on chemical structure with CPU (Central Processing Unit) acceleration | |
| CN102073473A (en) | Field programmable gata array (FPGA)-based metric floating-point multiplier design | |
| CN102289649A (en) | Method for identifying large number by utilizing Chinese characters | |
| CN107729577A (en) | A kind of data search method based on multidimensional Hash table, terminal device and storage medium | |
| CN116309520B (en) | Strip steel surface defect detection system | |
| Zhu et al. | Charge Transfer in Molecular Materials | |
| Qiao et al. | An analysis of the evolution in internet of things industry based on industry life cycle theory | |
| Malekmohammadi et al. | Putative local adaptive SNPs in the genus Avicennia | |
| CN201122297Y (en) | Display memory system for number of people in house | |
| Yao et al. | Electromagnetic transient parallel simulation optimisation based on GPU | |
| Lin | Overview of High Performance Computing Power Building for the Big Data of Marine Forecasting | |
| Tanaka | Rethinking of the Positivism and the Potential of the Systems Approach | |
| CN204833087U (en) | Embedded industrial control computer | |
| Vijayakumar | Engineering Life: The Promises and Perils of Synthetic Biology. | |
| Yueying et al. | Quick sorting algorithm of matrix | |
| Babu et al. | The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130327 |