CN102998614A - System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method - Google Patents
System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method Download PDFInfo
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Abstract
The invention discloses a system capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and a debugging method. The system is provided with a plurality of DSP plates. The DSP plates are provided with input JTAG interfaces, output JTAG interfaces and off-on control circuits connected between the input JTAG interfaces and the output JTAG interfaces, wherein the input JTAG interfaces and the output JTAG interfaces are arranged on the DSP plates. A first one of series-connection DSP chips on the DSP plates is connected with the input JTAG interfaces, and a last one of the series-connection DSP chips on the DSP plates is connected with the output JTAG interfaces. During single-plate debugging, the input JTAG interface of one DSP plate is directly connected with a simulator. During multi-plate debugging, the plurality of DSP plates are connected through JTAG interconnection cables. The JTAG interconnection cables are connected between the DSP plates so as to switch to a multi-plate debugging mode automatically, the JTAG interconnection cables are removed so as to switch to a single-plate mode, and the system is convenient to use. Through hard wiring between the plates, the system and the debugging method can avoid misoperation of users and have high reliability.
Description
Technical field
The present invention relates to the DSP adjustment method based on the JTAG standard, relate in particular to system and the adjustment method of a kind of DSP of realization veneer or many plates JTAG debugging.
Background technology
At present, in DSP(Digital Signal Processing digital signal processing) in the debug process of system, with JTAG(Joint Test Action Group combined testing action group) hardware capability debugging and the software algorithm of carrying out DSP verify it is the debugging method of present main flow.Jtag boundary scanning has adopted IEEE1149.1 standard, this testing standard to define hardware configuration and the working mechanism that uses JTAG.Its advantage be the circuit board testing with complexity be transformed into have good structural, can be simple and process flexibly by software.
The principle of work of JTAG can be summed up as: at a device inside definition TAP (Test Access Port, test access mouth), by the jtag test instrument of special use internal node is tested and debugged.Its basic thought is to increase a shift register cell, namely boundary scan register (Boundary-Scan Register) at the I/O pin near chip.When chip was in debugging mode, boundary scan register can be kept apart chip and peripheral I/O.By the boundary scan register unit, can realize observation and control to the chip input/output signal.For the input pin of chip, can be loaded into signal (data) in this pin by the boundary scan register unit that is attached thereto and go; For the output pin of chip, also can " catch " output signal on this pin by the boundary scan register that is attached thereto.Under normal running status, boundary scan register is transparent to chip, so normal operation can not be affected.Like this, boundary scan register provides a kind of easily mode to be used for observing and controlling the chip of required debugging.In addition, boundary scan (displacement) register cell on the chip I/O pin can be connected with each other, and forms a boundary scan chain (Boundary-Scan Chain) around the chip.Boundary scan chain is input and output serially, by corresponding clock signal and control signal, just can observe easily and control the chip that is under the debugging mode.
TAP (Test Access Port) is a general port, all data registers (DR) and the order register (IR) that can access chip provide by TAP.Control to whole TAP is finished by TAP controller (TAP Controller).In the jtag interface of DSP, mainly contain following 6 signals.Wherein, front 4 signals are mandatory requirements in the IEEE1149.1 standard.
◇ TCK: clock signal, for the operation of JTAG provide one independently, basic clock signal.
◇ TMS: mode select signal.
◇ TDI: data input signal.
◇ TDO: data output signal.
◇ TRST: reset signal.
◇ EMU: simulation data signal, this signal are open collector output.
Jtag boundary scanning is a testing standard that is mainly used in on-chip circuit, but scope is very extensive in the practical application.The range of application of JTAG mainly contains two large classes at present: a class is used for the electrical specification of test chip, and whether detection chip has problem; Another kind of for to all kinds of chips with and peripherals debug.A DSP who contains JTAG debugging interface module, as long as clock is normal, just can by jtag interface access DSP internal register, hang over equipment on the dsp bus and the register of built-in module.
Because jtag interface has above-mentioned advantage, therefore be widely used at present in the debugging and test of dsp system.
For one by many plates, every plate comprises the system that a plurality of DSP nodes form, traditional JTAG adjustment method can only utilize single emulator that the JTAG daisy chain that a plurality of DSP in the veneer form is debugged, when needs carry out combined debugging to many plates, the mode that then can only adopt a plurality of emulators independently to debug, as shown in Figure 1.
But in the dsp system of many plates multinode, jtag interface mainly contains following restriction: limited, the single jtag interface of the physical distance of connection is only supported debugging single board.Thereby under having a plurality of DSP nodes and being distributed in situation on a plurality of circuit boards, single jtag circuit can't satisfy the needs of application.No matter being external or domestic at present, is to be generally the modes that adopt a plurality of jtag circuits, use many cover emulation software and hardwares to this way to solve the problem.The realization cost of this mode is higher, reach more than the several times of single jtag circuit, and the scope of application is also more limited, can't satisfy multi-slab is debugged the application needs that higher synchronous requirement is arranged.
Summary of the invention
The technical problem to be solved in the present invention is for the defective that can't carry out to many plates multiple DSP system combined debugging in the prior art, and a kind of DSP of realization veneer or many plates JTAG system and the adjustment method of debugging are provided.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of DSP of realization veneer or the many plates JTAG system of debugging is provided, and this system comprises a plurality of dsp boards;
Comprise a plurality of dsp chips with the daisy chaining series connection on the described dsp board; Described dsp board is provided with input jtag interface and output jtag interface, and is connected to the ON-OFF control circuit between described input jtag interface and the described output jtag interface; First dsp chip of connecting on the described dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During debugging single board, the input jtag interface of single dsp board directly is connected with emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
In the system of the present invention, described ON-OFF control circuit comprises pull-up resistor and enables the single channel logic gate of control end with high level;
One end of described pull-up resistor is connected with high level signal, the other end enables control end with the high level of described single channel logic gate and is connected, this high level signal makes described single channel logic gate be in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access low level signal, make described single channel logic gate be in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
In the system of the present invention, described ON-OFF control circuit comprises pull down resistor and enables the single channel logic gate of control end with low level;
One end of described pull down resistor is connected with low level signal, the other end enables control end with the low level of described single channel logic gate and is connected, this low level signal makes described single channel logic gate be in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access high level signal, make described single channel logic gate be in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
In the system of the present invention, described single channel logic gate is logical device independently, or realizes by FPGA and CPLD device.
In the system of the present invention, described input jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard code, and pin/EMU, KEY, GND and CTL, wherein pin/EMU is the simulation data signal, this output signal is the open collector output signal, KEY is the avoiding misinsertion pin, and GND is the signal ground in the plate, CTL connect previous dsp board ON-OFF control circuit enable control end;
Described output jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard code, and pin/EMU, KEY, GND and EN, wherein EN is for enabling to control pin, connect the place dsp board ON-OFF control circuit enable control end.
In the system of the present invention, also be provided with the clock signal driving circuit on each dsp board, be connected with the clock input pin of each dsp chip.
The present invention solves another technical scheme that its technical matters adopts:
The JTAG adjustment method of the many DSP of a kind of many plates is provided, may further comprise the steps:
The mode of polylith dsp chip in the same dsp board with daisy chain is connected in the JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between described input jtag interface and described output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
In the JTAG adjustment method of the present invention, also comprise step:
During debugging single board, disconnecting described JTAG interconnect cable connects, the input jtag interface of single dsp board directly is connected with described emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop.
In the JTAG adjustment method of the present invention, also comprise each dsp chip on each dsp board is carried out the step that clock signal drives.
The beneficial effect that the present invention produces is: the present invention is by interconnected jtag interface between setting up for plate at each DSP, comprise input jtag interface and output jtag interface, between dsp board, connect the JTAG interconnect cable and can automatically switch to many plates debud mode, remove the JTAG interconnect cable and become again the veneer mode, use very convenient.The present invention can also prevent user's maloperation having higher reliability by hard wired mode between plate.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the debugging structural representation of many plates multiple DSP system in the prior art;
Fig. 2 is the structural representation of system when many plate debugging that can realize DSP veneer or many plates JTAG debugging in the embodiment of the invention;
Fig. 3 is the single plate structure synoptic diagram in the embodiment of the invention;
Fig. 4 is the realization schematic diagram one of embodiment of the invention ON-OFF control circuit;
Fig. 5 is the realization schematic diagram two of embodiment of the invention ON-OFF control circuit.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the invention can realize the system of DSP veneer or many plates JTAG debugging, comprises a plurality of dsp boards, as shown in Figure 2, comprises A plate, B plate and C plate, wherein, comprises four dsp chips on the every dsp board, such as the S0 on the A plate, S1, S2 and S3.
As shown in Figures 2 and 3, comprise a plurality of dsp chips with the daisy chaining series connection on the dsp board; Dsp board is provided with input jtag interface (JTAGIN) and output jtag interface (JTAGOUT), and is connected to the ON-OFF control circuit between input jtag interface and the output jtag interface; First dsp chip of connecting on the dsp board connects the input jtag interface, and last piece dsp chip connects the output jtag interface.
During debugging single board, the input jtag interface of single dsp board directly is connected with emulator, and ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and emulator form JTAG debugging loop.
In one embodiment of the invention, the interface definition of input jtag interface (JTAGIN) and output jtag interface (JTAGOUT) is as shown in the table:
The interface definition table of table 1JTAGIN and JTAGOUT
| JTAGIN | Signal name | JTAGOUT | Signal |
| 2 pin | /EMU | 2 pin | /EMU_OUT |
| 6 pin | TMS | 6 pin | TMS_OUT |
| 8 pin | TCK | 8 pin | TCK_OUT |
| 10 pin | /TRST | 10 pin | /TRST_OUT | |
| 12 pin | TDI | 12 pin | TDI_OUT | |
| 14 pin | TDO | 14 pin | TDO_OUT | |
| 16 | CTL | 16 pin | EN | |
| 3 pin | KEY (mistake proofing pin) | 5 pin | KEY (mistake proofing pin) | |
| Other pin | GND | Other pin | GND |
Wherein pin/TRST of JTAGIN, TCK, TMS, TDI, TDO are the signal of IEEE1149.1 standard code; / EMU is the simulation data signal, and this signal is open collector output; KEY is the avoiding misinsertion pin; GND is the signal ground in the plate; The 16 pin CTL of JTAGIN connect previous dsp board ON-OFF control circuit the single channel logic gate enable control end.
Pin/TRST_OUT of JTAGIN, TCK_OUT, TMS_OUT, TDI_OUT, TDO_OUT are the signal of IEEE1149.1 standard code; / EMU is the simulation data signal, and this signal is open collector output; KEY is the avoiding misinsertion pin; GND is the signal ground in the plate; The 16 pin EN of JTAGOUT are for enabling to control pin, connect the place dsp board ON-OFF control circuit the single channel logic gate enable control end.The interconnecting relation of JTAGIN and each signal of JTAGOUT as shown in Figure 3.
As shown in Figure 3, in the veneer A plate, the jtag interface of 4 dsp chips in the plate adopts daisy architecture, i.e. second TDI of the TDO of first access, and second TDO accesses the 3rd TDI, and is interconnected in twos, forms chain structure; DSP quantity is more when considering the cascade of many plates, and load is larger, therefore, has adopted special-purpose driver G2, G3 that TDI, TDO signal are driven in this embodiment, strengthens its load capacity; During debugging single board, the direct connection with the JTAGIN interface of debug machine emulator interface gets final product, take the A plate as example, the debug machine emulator interface links to each other with the A plate by the JTAG interconnect cable, this moment, the A plate was not connected with JTAG interconnect cable between the B plate, ON-OFF control circuit between its JTAGOUT and the JTAGIN is for disconnecting, therefore the A plate is in debugging single board and (or is called the most end node state, namely the JTAG signal on plate this moment no longer spreads out of from JTAGOUT, but directly return from JTAGIN) state, its TDI, the TDO signal automatically switches to self-loop (daisy chain) state in the plate, EMU, CLK automatically switches to direct-connected state in the plate.The JTAG mode that at this moment, can realize the A plate is independently debugged.
According to the requirement of IEEE1149.1 standard, tck signal ,/TRST signal, tms signal should adopt on the pull-up resistor and draw, and guarantees that it is in steady state (SS);
Because the tck clock of DSP reaches as high as 50MHz, therefore in veneer or many plates cascade system, must drive step by step.In one embodiment of the present of invention, also be provided with the clock signal driving circuit on each dsp board, be connected with the clock input pin (TCK) of each dsp chip.If the cascade number of many plates cascade system〉3, DSP on the veneer〉4 when above, for guaranteeing that tck clock can run on highest frequency, and each DSP node has preferably synchronizing characteristics, need to adopt the special clock delay circuit carry out the accurate adjustment that tck clock prolongs, dwindle the JTAG clock skew between the longest DSP of the shortest DSP of tck signal in the whole system and tck signal.Therefore, in this embodiment, adopted special-purpose clock signal driving circuit, guaranteed that the TCK input signal of every a slice DSP can both meet the demands.
/ TRST, tms signal, in veneer, this part signal is 4 interior DSP of access board simultaneously, and in many plates cascade system, this part signal can access all DSP simultaneously, load is larger.Therefore, in this embodiment, adopted special-purpose driver G4, G5 right/TRST, tms signal drive, and strengthens its load capacity;
/ EMU signal, because DSP /the EMU signal all is open collector output, realizes " line or " and cascade with the logic gate G1 that enables with low level.No matter in veneer or many plates cascade system, any a slice DSP /the G1 door of EMU signal on effectively all can enable link, so just signal is delivered to always the input of JTAG foremost.
When needs carry out many plates JTAG cascade, as shown in Figure 2, only need to utilize the JTAG interconnect cable, the JTAGIN of emulator and A plate is interconnected, and the JTAGIN of the JTAGOUT of A plate and B plate is interconnected, interconnected the getting final product of JTAGIN of the JTAGOUT of B plate and C plate.
In the embodiment of the invention, as shown in Figure 4, ON-OFF control circuit comprises pull-up resistor and enables the single channel logic gate of control end with high level;
One end of pull-up resistor is connected with high level signal, and the other end enables control end with the high level of single channel logic gate and is connected, and this high level signal makes the single channel logic gate be in enabled state.This enables control end and can connect power supply and obtain high level signal, and high level signal also can be realized by FPGA, CPLD or other modes that can be driven to high level.
When debugging single board, by the conducting of this single channel logic gate, plate internal daisy chain is closed, can form debugging loop in the plate; This other end also with plate between jtag interface enable control pin (EN pin) and be connected, when many plates debugging, connect the JTAG interconnect cable after, enable to control pin access low level signal, make the single channel logic gate be in disabled state, plate internal daisy chain opens.
The input end of single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
As shown in Figure 4, be a specific embodiment of ON-OFF control circuit of the present invention, utilize a slice band high level to enable between the single channel logic gate G6 of control signal and plate the JTAG interconnect cable and realize switch control;
The input signal of single channel logic gate G6 is the TDI signal in the A plate, and this signal comes from the JTAGIN interface in the plate, and draws by the 12nd pin (TDI_OUT) of JTAGOUT interface in the A plate;
The output signal of single channel logic gate G6 is the TDO signal in the A plate, this signal access first DSP(S0) TDI, and draw by the 14th pin (TDO_OUT) of the interior JTAGOUT interface of A plate;
The enable signal of single channel logic gate G6 is pulled to high level by resistance in plate, and draws by the 16th pin (EN) of JTAGOUT interface in the A plate;
When not interconnected by the JTAG interconnect cable between A plate and the B plate, the enable signal of G6 is pulled to high level by pull-up resistor, logic gate conducting this moment, the TDI signal of A plate is by G6 access first DSP(S0) TDI, realize that the JTAG daisy chain is closed in the plate, can carry out debugging single board this moment;
When passing through the JTAG cable interconnect between A plate and the B plate, the enable signal of G6 connects low level (GND) by 16 pins (CTL) of JTAGIN interface in the B plate, and this moment, logic gate was closed, and G6 is output as three-state;
By the JTAG interconnect cable, the TDI of the TDI signal of A plate access B plate, the TDO of the TDO signal access A plate of B plate forms the complete daisy chain between two plates, consists of many plates cascade JTAG loop, can carry out the uniting and adjustment of many plates;
The embodiment of the invention can expand to a plurality of integrated circuit boards, is not restricted between two integrated circuit boards;
The logic gates such as the G6 that relates to not only can by independently logical device realization, also can be realized by devices such as FPGA, CPLD;
G6 enable signal ground connection not only can be realized by ground connection, also can be driven to low level mode by FPGA, CPLD or other and realize.
In another embodiment of the present invention, ON-OFF control circuit comprises pull down resistor and enables the single channel logic gate of control end with low level;
One end of pull down resistor is connected with low level signal, the other end enables control end with the low level of single channel logic gate and is connected, this low level signal makes the single channel logic gate be in enabled state, but this enables control end ground connection and obtains low level signal, and low level signal also can be driven to low level mode by FPGA, CPLD or other and realize.
When debugging single board, by the conducting of this single channel logic gate, plate internal daisy chain is closed, can form JTAG debugging loop in the plate; This other end also with plate between jtag interface enable control pin and be connected, when many plates debugging, enable to control pin access high level signal, make the single channel logic gate be in disabled state; The input end of single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
The JTAG adjustment method of the many DSP of the many plates of the embodiment of the invention based on the above-mentioned system that realizes DSP veneer or many plates JTAG debugging, specifically may further comprise the steps:
The mode of polylith dsp chip in the same dsp board with daisy chain is connected in the JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between input jtag interface and output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects the input jtag interface, and last piece dsp chip connects the output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and emulator form JTAG debugging loop.
When debugging single board, disconnect the JTAG interconnect cable and connect, the input jtag interface of single dsp board directly is connected with emulator, and ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and emulator form JTAG debugging loop.
Because the tck clock of DSP reaches as high as 50MHz, therefore in veneer or many plates cascade system, must drive step by step, need that each dsp chip on each dsp board is carried out clock signal and drive.How realizing specifically that clock drives above has a detailed description among the embodiment, is not repeated herein.
The present invention is by interconnected jtag interface between setting up for plate at each DSP, comprise input jtag interface and output jtag interface, between dsp board, connect the JTAG interconnect cable and can automatically switch to many plates debud mode, remove the JTAG interconnect cable and become again the veneer mode, use very convenient.The present invention can also prevent user's maloperation having higher reliability by hard wired mode between plate.
Should be understood that, for those of ordinary skills, can be improved according to the above description or conversion, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (9)
1. the system that can realize DSP veneer or many plates JTAG debugging is characterized in that this system comprises a plurality of dsp boards;
Comprise a plurality of dsp chips with the daisy chaining series connection on the described dsp board; Described dsp board is provided with input jtag interface and output jtag interface, and is connected to the ON-OFF control circuit between described input jtag interface and the described output jtag interface; First dsp chip of connecting on the described dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During debugging single board, the input jtag interface of single dsp board directly is connected with emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
2. system according to claim 1 is characterized in that, described ON-OFF control circuit comprises pull-up resistor and enables the single channel logic gate of control end with high level;
One end of described pull-up resistor is connected with high level signal, the other end enables control end with the high level of described single channel logic gate and is connected, this high level signal makes described single channel logic gate be in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access low level signal, make described single channel logic gate be in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
3. system according to claim 1 is characterized in that, described ON-OFF control circuit comprises pull down resistor and enables the single channel logic gate of control end with low level;
One end of described pull down resistor is connected with low level signal, the other end enables control end with the low level of described single channel logic gate and is connected, this low level signal makes described single channel logic gate be in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access high level signal, make described single channel logic gate be in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
4. according to claim 2 or 3 described systems, it is characterized in that described single channel logic gate is logical device independently, or realize by FPGA and CPLD device.
5. according to claim 2 or 3 described systems, it is characterized in that, described input jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard code, and pin/EMU, KEY, GND and CTL, wherein pin/EMU is the simulation data signal, and this output signal is the open collector output signal, and KEY is the avoiding misinsertion pin, GND is the signal ground in the plate, CTL connect previous dsp board ON-OFF control circuit enable control end;
Described output jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard code, and pin/EMU, KEY, GND and EN, wherein EN is for enabling to control pin, connect the place dsp board ON-OFF control circuit enable control end.
6. system according to claim 5 is characterized in that, also is provided with the clock signal driving circuit on each dsp board, is connected with the clock input pin of each dsp chip.
7. the JTAG adjustment method of the many DSP of plate more than a kind is characterized in that, may further comprise the steps:
The mode of polylith dsp chip in the same dsp board with daisy chain is connected in the JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between described input jtag interface and described output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by the JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second output jtag interface that is connected to successively previous dsp board to the input jtag interface of last dsp board by the JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make and form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
8. JTAG adjustment method according to claim 7 is characterized in that, also comprises step:
During debugging single board, disconnecting described JTAG interconnect cable connects, the input jtag interface of single dsp board directly is connected with described emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop.
9. JTAG adjustment method according to claim 7 is characterized in that, also comprises each dsp chip on each dsp board is carried out the step that clock signal drives.
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