CN102983162A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102983162A CN102983162A CN2011102599748A CN201110259974A CN102983162A CN 102983162 A CN102983162 A CN 102983162A CN 2011102599748 A CN2011102599748 A CN 2011102599748A CN 201110259974 A CN201110259974 A CN 201110259974A CN 102983162 A CN102983162 A CN 102983162A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
本发明公开了一种半导体装置及其制造方法。半导体装置包括第一掺杂区、第二掺杂区、介电结构与栅极结构。第一掺杂区具有第一导电型。第二掺杂区具有相反于第一导电型的第二导电型并邻近第一掺杂区。介电结构包括互相分开的第一介电部分与第二介电部分。介电结构形成于第一掺杂区上。栅极结构位于第一掺杂区或第二掺杂区邻近第一介电部分的一部分上。
The present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first doping region, a second doping region, a dielectric structure and a gate structure. The first doping region has a first conductivity type. The second doping region has a second conductivity type opposite to the first conductivity type and is adjacent to the first doping region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doping region. The gate structure is located on a portion of the first doping region or the second doping region adjacent to the first dielectric portion.
Description
Technical field
The invention relates to a kind of semiconductor device and manufacture method thereof, particularly relevant for a kind of transistor and manufacture method thereof.
Background technology
In semiconductor technology, for instance, semiconductor device for example power device is to use lateral double diffusion metal oxide semiconductor (LDMOS).For the breakdown voltage (breakdown voltage, BVdss) that improves semiconductor device, a kind of method is to reduce the doping content of drain region and increase drift length.Yet the method can improve the opening resistor of semiconductor device.In addition, need large design area.
Insulated gate bipolar transistor in the semiconductor technology (Insulated Gate Bipolar Transistors, IGBT) has simultaneously the advantage of transistor (MOS) and bipolar junction transistor (bipolar junction transistor, BJT).Insulated gate bipolar transistor can be used in the switch application.
Summary of the invention
The invention relates to semiconductor device and manufacture method thereof.Semiconductor device has excellent usefulness, and low cost of manufacture.
According to one embodiment of the present of invention, the invention provides a kind of semiconductor device, this semiconductor device comprises the first doped region, the second doped region, dielectric structure and grid structure.The first doped region has the first conductivity type.The second doped region has in contrast to the second conductivity type of the first conductivity type and contiguous the first doped region.Dielectric structure comprises the first dielectric part separated from each other and the second dielectric part.Dielectric structure is formed on the first doped region.Grid structure is positioned on the part of the first doped region or contiguous the first dielectric part of the second doped region.
According to another embodiment of the present invention, the invention provides a kind of manufacture method of semiconductor device, the method may further comprise the steps: form the second doped region in the first doped region; The first doped region has the first conductivity type, and the second doped region has the second conductivity type in contrast to the first conductivity type; Form dielectric structure on the first doped region; Dielectric structure comprises the first dielectric part separated from each other and the second dielectric part; Form grid structure on the part of the first doped region or contiguous the first dielectric part of the second doped region.
Preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 illustrates the profile of semiconductor device among the embodiment.
Fig. 2 illustrates the profile of semiconductor device among the embodiment.
Fig. 3 illustrates the profile of semiconductor device among the embodiment.
Fig. 4 illustrates the profile of semiconductor device among the embodiment.
Fig. 5 illustrates the profile of semiconductor device among the embodiment.
Fig. 6 illustrates the profile of semiconductor device among the embodiment.
Fig. 7 shows the breakdown voltage curve under semiconductor device in off position among the embodiment.
Fig. 8 shows the ID-VD curve of semiconductor device among the embodiment.
Fig. 9 shows the linear zone electric current of semiconductor device among the embodiment.
[main element symbol description]
12,112,212,312,412,512: the first doped regions
14: the second doped regions
16,416: dielectric structure
18,418: the first dielectric part
20,420: the first dielectric part
22: grid structure
24: dielectric layer
26: conductive layer
28,30,32,128,228,328,428,528,58,60,162,362,562: doped portion
34: the three doped regions
36,136,336,536: the four doped regions
38,40,42,44: electrode
46,48: side
50,450: the first doped layers
52,452: the second doped layers
54,254: bottom
56: doped well region
264: isolation structure
266,268,270: isolated part
472: the three dielectric part
Embodiment
Fig. 1 illustrates the profile of semiconductor device among the embodiment.Please refer to Fig. 1, the first doped region 12 contiguous the second doped regions 14.The first doped region 12 comprises doped portion 28, has for example N conductivity type of the first conductivity type.The second doped region 14 can comprise doped portion 30 and doped portion 32, has the second conductivity type in contrast to the first conductivity type, for example the P conductivity type.In embodiment, doped portion 30 is by the mask layer (not shown) of patterning the first doped region 12 to be mixed to form.Doped portion 32 is by the mask layer (not shown) of patterning doped portion 30 to be mixed to form.Doped portion 32 can be heavily doped region.
In an embodiment, have the first conductivity type for example the 3rd doped region 34 of N conductivity type be by the mask layer (not shown) of patterning doped portion 30 to be mixed to form.The 4th doped region 36 is by the mask layer (not shown) of patterning the first doped region 12 to be mixed to form.The 3rd doped region 34 and the 4th doped region 36 can be heavily doped region.
Please refer to Fig. 1, dielectric structure 16 is formed on the first doped region 12.Dielectric structure 16 comprises the first dielectric part 18 separated from each other and the second dielectric part 20.The first dielectric part 18 and the second dielectric part 20 are not limited to the field oxide shown in Fig. 1, also can be isolation structure of shallow trench or other suitable insulant.
Please refer to Fig. 1, the 4th doped region 36 and the second doped region 14 lay respectively on the relative side 46,48 of dielectric structure 16.In an embodiment, the first doped layer 50 is formed on the doped portion 28 between the first dielectric part 18 and the second dielectric part 20.The first doped layer 50 has for example P conductivity type of the second conductivity type.The first doped region 12 can comprise the second doped layer 52, has for example N conductivity type and be positioned at the first doped layer 50 times of the first conductivity type.The second doped layer 52 can mix to doped portion 28 by the mask layer (not shown) of patterning and form.The first doped layer 50 can mix to the second doped layer 52 by the mask layer (not shown) of patterning and form.
Please refer to Fig. 1, bottom 54 can be positioned at the below of the first doped region 12.Bottom 54 can have for example P conductivity type of the second conductivity type.Bottom 54 can be substrate or epitaxial loayer.In an embodiment, bottom 54 is silicon-on-insulator (Silicon on insulator, SOI).The doped portion 28 of the first doped region 12 can mix to bottom 54 by the mask layer (not shown) of patterning and form.Doped portion 28 also can extension mode be formed on the bottom 54.Doped well region 56 contiguous doped portions 28 also are positioned on the bottom 54.Doped well region 56 comprises doped portion 58 and doped portion 60, has for example P conductivity type of the second conductivity type.Doped portion 58 can mix to bottom 54 by the mask layer (not shown) of patterning and form.Doped portion 58 also can extension mode be formed on the bottom 54.Doped portion 60 can mix to doped portion 58 by the mask layer (not shown) of patterning and form.Doped portion 60 can be heavily doped region.
In an embodiment, semiconductor device is set to for example horizontal double diffusion (Lateral double Diffusion) metal-oxide semiconductor (MOS) (LDMOS) of metal-oxide semiconductor (MOS) (MOS).In this example, the first doped region 12 comprises the 4th doped region 36, has for example N conductivity type of the first conductivity type.Grid structure 22 is on the doped portion 30 between doped portion 28 and the 3rd doped region 34.Electrode 40 for example drain electrode is electrically connected to the 4th doped region 36.Electrode 42 for example source electrode is electrically connected to the 3rd doped region 34.Electrode 44 for example gate electrode is electrically connected to grid structure 22.Electrode 38 for example base electrode is electrically connected to doped portion 32.Electrode 38 can be electrically connected mutually with electrode 42.
In another embodiment, semiconductor device is set to insulated gate bipolar transistor (Insulated Gate Bipolar Transistors, IGBT), at length be lateral insulated gate bipolar transistor (lateralinsulated gate bipolar transistor, LIGBT).In this example, the 4th doped region 36 has for example P conductivity type of the second conductivity type.Grid structure 22 is on the doped portion 28 between the first dielectric part 18 and the doped portion 30.Electrode 40 for example collector electrode is electrically connected to the 4th doped region 36.Electrode 38 for example emitter-base bandgap grading electrode is electrically connected to doped portion 32.Electrode 44 for example gate electrode is electrically connected to grid structure 22.Electrode 42 for example base electrode is electrically connected to the 3rd doped region 34.Electrode 38 can be electrically connected mutually with electrode 42.
The conductivity type that semiconductor device can be controlled the 4th doped region 36 simply be the first conductivity type for example the N conductivity type make (800V) laterally double-diffused transistor, or the second conductivity type for example the P conductivity type make (700V) insulated gate bipolar transistor.Semiconductor device can by CMOS technique for example 700V power CMOS technique make, so the manufacturing of semiconductor device do not need to increase extra mask (mask) or step, is conducive to be incorporated in the same wafer with other device yet.In embodiment, use dielectric structure 16 and be applied to reduce surface field (Reduced Surface Field, RESURF) (in more detail, the first doped layer 50 of concept two reduction surface field (double RESURF)) and the second doped layer 52, help to improve for example drain electrode breakdown voltage of LDMOS (drain breakdown voltage) of semiconductor device, and reduce opening resistor (Rdson).In an embodiment, semiconductor device is set to 700V or the horizontal double-diffused transistor of 820V.
For instance, be the N conductivity type at the first conductivity type, the second conductivity type is in the situation of P conductivity type, semiconductor device is set to LIGBT (N-channel LIGBT) or the LDNMOS of N passage.On the contrary, be the P conductivity type at the first conductivity type, the second conductivity type is in the situation of N conductivity type, semiconductor device is set to LIGBT (P-channel LIGBT) or the LDPMOS of P passage.
Fig. 2 illustrates the profile of semiconductor device among the embodiment.The difference of the semiconductor device that the semiconductor device that Fig. 2 illustrates and Fig. 1 illustrate is that the first doped region 112 comprises doped portion 162, has for example N conductivity type of the first conductivity type.Doped portion 162 can mix to doped portion 128 by the mask layer (not shown) of patterning and form.In this example, the 4th doped region 136 can utilize the mask layer (not shown) of patterning doped portion 162 is mixed and to form.
Fig. 3 illustrates the profile of semiconductor device among the embodiment.The difference of the semiconductor device that the semiconductor device that Fig. 3 illustrates and Fig. 1 illustrate is that isolation structure 264 surrounds the doped portion 228 of the first doped region 212.Isolation structure 264 can comprise isolated part 266, isolated part 268 and isolated part 270.For instance, the isolated part 266 that is formed on the bottom 254 is for example dielectric oxide of buried horizon.Isolated part 268 can be the deep trench isolation, comprises dielectric oxide.The isolated part 270 that is formed on the isolated part 268 is not limited to field oxide, also can be shallow trench isolation.
Fig. 4 illustrates the profile of semiconductor device among the embodiment.The difference of the semiconductor device that the semiconductor device that Fig. 4 illustrates and Fig. 3 illustrate is that the first doped region 312 comprises doped portion 362, has for example N conductivity type of the first conductivity type.Doped portion 362 can mix to doped portion 328 by the mask layer (not shown) of patterning and form.In this example, the 4th doped region 336 can utilize the mask layer (not shown) of patterning doped portion 362 is mixed and to form.
Fig. 5 illustrates the profile of semiconductor device among the embodiment.The difference of the semiconductor device that the semiconductor device that Fig. 5 illustrates and Fig. 1 illustrate is that dielectric structure 416 comprises at least one the 3rd dielectric part 472, between the first dielectric part 418 and the second dielectric part 420.The first doped region 412 have the first conductivity type for example the second doped layer 452 of N conductivity type on the doped portion 428 between the first dielectric part 418, the second dielectric part 420 and the 3rd dielectric part 472.Have the second conductivity type for example the first doped layer 450 of P conductivity type be positioned on the second doped layer 452.
Fig. 6 illustrates the profile of semiconductor device among the embodiment.The difference of the semiconductor device that the semiconductor device that Fig. 6 illustrates and Fig. 5 illustrate is that the first doped region 512 comprises doped portion 562, has for example N conductivity type of the first conductivity type.Doped portion 562 can mix to doped portion 528 by the mask layer (not shown) of patterning and form.In this example, the 4th doped region 536 can utilize the mask layer (not shown) of patterning doped portion 562 is mixed and to form.
Fig. 7 shows that semiconductor device among the embodiment is set to the breakdown voltage curve (Off-BV curve) of LIGBT under in off position, and BV is 820V.Fig. 8 shows that semiconductor device among the embodiment is set to the ID-VD curve of LIGBT, and VG is 5V.Semiconductor device is set to the linear zone electric current (idline) between LIGBT and the double RESURF LDNMOS in Fig. 9 comparing embodiment, and wherein the VG of LIGBT is 5V, and LDNMOS is 10V.
Embodiment according to above-mentioned exposure, the conductivity type that semiconductor device can be controlled the 4th doped region simply decides the horizontal double-diffused transistor of manufacturing or insulated gate bipolar transistor, and can be made by CMOS technique, therefore the manufacturing of semiconductor device is conducive to the integration of different device, and does not need extra-pay.The first doped layer and second doped layer of dielectric structure and the concept that is applied to reduce surface field (Reduced Surface Field, RESURF) help to improve the operation usefulness of semiconductor device.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.
Claims (10)
1. semiconductor device comprises:
One first doped region has one first conductivity type;
One second doped region has one second conductivity type and contiguous this first doped region in contrast to this first conductivity type;
One dielectric structure comprises one first dielectric part separated from each other and one second dielectric part, and wherein this dielectric structure is formed on this first doped region; And
One grid structure is positioned on the part of contiguous this first dielectric part of this first doped region or this second doped region.
2. semiconductor device according to claim 1, more comprise one first doped layer, has this second conductivity type, wherein this first doped layer is on this first doped region between this first dielectric part and this second dielectric part, this first doped region comprises one second doped layer, has this first conductivity type and is positioned under this first doped layer.
3. semiconductor device according to claim 1, wherein this dielectric structure more comprises at least one the 3rd dielectric part, between this first dielectric part and this second dielectric part.
4. semiconductor device according to claim 1, more comprise one the 3rd doped region, has this first conductivity type, wherein this grid structure is on this second doped region between this first doped region and the 3rd doped region, one first electrode is electrically connected to this first doped region, and one second electrode is electrically connected to the 3rd doped region.
5. semiconductor device according to claim 4, wherein this first electrode is drain electrode, and this second electrode is source electrode, and this semiconductor device is set to LDMOS.
6. semiconductor device according to claim 1 comprises that more one the 4th doped region has this second conductivity type, and wherein this second doped region and the 4th doped region lay respectively on the relative side of this dielectric structure.
7. semiconductor device according to claim 6, wherein one first electrode is electrically connected to this second doped region, and one second electrode is electrically connected to the 4th doped region.
8. semiconductor device according to claim 7, wherein this first electrode is the emitter-base bandgap grading electrode, and this second electrode is the collector electrode, and this semiconductor device is set to the lateral insulated gate bipolar transistor.
9. semiconductor device according to claim 1, wherein this semiconductor device is set to lateral double diffusion metal oxide semiconductor or insulated gate bipolar transistor.
10. the manufacture method of a semiconductor device comprises:
Form one second doped region in one first doped region, this first doped region has one first conductivity type, and this second doped region has one second conductivity type in contrast to this first conductivity type;
Form a dielectric structure on this first doped region, wherein this dielectric structure comprises one first dielectric part separated from each other and one second dielectric part; And
Form a grid structure on the part of this first doped region or contiguous this first dielectric part of this second doped region.
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| CN2011102599748A CN102983162A (en) | 2011-09-05 | 2011-09-05 | Semiconductor device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
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|---|---|---|---|---|
| US5146298A (en) * | 1991-08-16 | 1992-09-08 | Eklund Klas H | Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor |
| CN1374703A (en) * | 2001-03-07 | 2002-10-16 | 株式会社东芝 | Semiconductor with insulation grid type double-polar transistor |
| CN101036231A (en) * | 2004-09-16 | 2007-09-12 | 飞兆半导体公司 | Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region |
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| US20110180813A1 (en) * | 2009-04-10 | 2011-07-28 | Sumitomo Electric Industries, Ltd. | Insulated gate bipolar transistor |
| CN102169903A (en) * | 2011-03-22 | 2011-08-31 | 成都芯源系统有限公司 | LDMOS devices |
-
2011
- 2011-09-05 CN CN2011102599748A patent/CN102983162A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146298A (en) * | 1991-08-16 | 1992-09-08 | Eklund Klas H | Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor |
| CN1374703A (en) * | 2001-03-07 | 2002-10-16 | 株式会社东芝 | Semiconductor with insulation grid type double-polar transistor |
| CN101036231A (en) * | 2004-09-16 | 2007-09-12 | 飞兆半导体公司 | Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region |
| US20110180813A1 (en) * | 2009-04-10 | 2011-07-28 | Sumitomo Electric Industries, Ltd. | Insulated gate bipolar transistor |
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| CN102169903A (en) * | 2011-03-22 | 2011-08-31 | 成都芯源系统有限公司 | LDMOS devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
| CN113540223B (en) * | 2020-04-22 | 2023-11-10 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
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Application publication date: 20130320 |