CN102983075B - Application stress closes on the manufacture method of the semiconductor device of technology - Google Patents
Application stress closes on the manufacture method of the semiconductor device of technology Download PDFInfo
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- CN102983075B CN102983075B CN201110264364.7A CN201110264364A CN102983075B CN 102983075 B CN102983075 B CN 102983075B CN 201110264364 A CN201110264364 A CN 201110264364A CN 102983075 B CN102983075 B CN 102983075B
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Abstract
Disclosed herein and a kind ofly apply the manufacture method that stress closes on the semiconductor device of technology, comprising: semi-conductive substrate is provided, described Semiconductor substrate is formed with grid; Described gate lateral wall forms grid curb wall, and described grid curb wall comprises oxide layer and is positioned at the nitration case outside oxide layer, and the material of described nitration case is boron-doping silicon nitride or mixes phosphorous nitride silicon; Source area and drain region is formed in the Semiconductor substrate of described grid both sides; Described grid, described source area and drain region form metal silicide layer; Plasma etching is utilized to remove all or part of described nitration case; Cover stressor layers on the semiconductor substrate.The manufacture method of semiconductor device of the present invention, utilizes stress to close on the basis of technology, and protection metal silicide layer is not etched damage, and then improves the performance of semiconductor device.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of application stress and close on technology (StressProximityTechnology, SPT).
Background technology
Along with in semiconductor technology production process, the size of transistor constantly reduces, and the voltage and current of transistor unit need of work constantly reduces, and the speed of transistor switch is also accelerated thereupon, requires significantly to improve to semiconductor technology each side thereupon.For improving the performance of semiconductor device, for improving the performance of the semiconductor device such as CMOS transistor, industry introduces stress memory technique.
Stress memory technique by introducing stress in the raceway groove of Semiconductor substrate, and to make the performance of semiconductor device improve, the technique being improved device performance by stress has become the common technological means of semiconductor applications.In prior art, stress memory technique is included in semiconductor device disposed thereon stressor layers (such as nitration case etc.), then, carrying out high-temperature annealing process is remembered on the semiconductor device to make stress, is removed stressor layers at stress by behind the active area remembered in grid polycrystalline silicon or diffusion region or Semiconductor substrate.Thus use the lattice structure of stress changes Semiconductor substrate, thus improve the mobility in electronics or hole, improve the performance of overall device.Especially the nmos pass transistor in CMOS transistor, stress memory technique is stress application (namely during compression) in a longitudinal direction, the electron mobility of nmos pass transistor can be improved, improve nmos pass transistor drive current (Idrive), and then improve the performance of nmos pass transistor.
In order to effect of stress can be produced better, introduce stress and close on technology (StressproximityTechnology, SPT), namely by the thickness of the grid curb wall of reduction of gate both sides, deposition stressor layers, to reduce stressor layers and the distance between Semiconductor substrate and grid, and then improve the effect of stress of stressor layers to Semiconductor substrate and grid, improve performance of semiconductor device further.
But, in the prior art, removing nitration case adopts the dry etching of fluorine ion or phosphoric acid wet etching to remove usually, but fluorine ion and phosphoric acid all can corrode the metal silicide layer that the source region of Semiconductor substrate, drain region and grid are formed, cause this metal silicide layer thinning, cause the extraction ability decline that is electrically connected, the resistance of semiconductor device is raised, electric current reduces, and causes the hydraulic performance decline of semiconductor device.
Summary of the invention
The object of this invention is to provide and a kind ofly apply the manufacture method that stress closes on the semiconductor device of technology, the metal silicide layer in protection semiconductor device, to improve the performance of semiconductor device.
For solving the problem, the present invention is a kind of applies the manufacture method that stress closes on the semiconductor device of technology, comprising:
Semi-conductive substrate is provided, described Semiconductor substrate is formed with grid;
Described gate lateral wall forms grid curb wall, and described grid curb wall comprises oxide layer and is positioned at the nitration case of oxide layer sidewall, and the material of described nitration case is boron-doping silicon nitride or mixes phosphorous nitride silicon;
Source area and drain region is formed in the Semiconductor substrate of described grid both sides;
Described grid, described source area and drain region form metal silicide layer;
Plasma etching is utilized to remove all or part of described nitration case;
Cover stressor layers on the semiconductor substrate.
Further, chemical vapor deposition method is adopted to form described nitration case
Further, when the material of described nitration case is boron-doping silicon nitride, the reacting gas of described chemical vapor deposition method comprises methane, diborane, ammonia and nitrogen.
Further, when the material of described nitration case is for mixing phosphorous nitride silicon, the reacting gas of described chemical vapor deposition method comprises methane, hydrogen phosphide, ammonia and nitrogen.
Further, the reaction temperature of described chemical vapor deposition method is 400 DEG C ~ 600 DEG C.
Further, the thickness of described nitration case is 100 dust ~ 500 dusts.
Further, the etching gas of described plasma etch process comprises forming gas and oxygen, and the volume ratio of described oxygen and described forming gas is 0.1: 1 ~ 2: 1.
Further, described forming gas comprises nitrogen and hydrogen, and the volume ratio that described hydrogen accounts for described forming gas is 4% ~ 20%.
Further, the material of described metal silicide layer is nickel silicide.
Further, the material of described stressor layers is nitration case, and thickness is 200 dust ~ 600 dusts.
Compared to prior art; manufacture in the process of semiconductor device utilizing stress technology of closing on; the material forming grid curb wall mixes phosphorous nitride silicon or boron-doping silicon nitride; and the plasma adopting forming gas and oxygen to be formed removes all or part of silicon nitride layer; this plasma can not damage the metal silicide layer be positioned on source area, drain region and grid; thus maintain the thickness of metal silicide layer; and then on the basis that application stress closes on technology, protect the thickness of metal silicide layer, improve the overall performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of method, semi-conductor device manufacturing method in the embodiment of the present invention one.
Fig. 2 ~ Fig. 7 is the structural representation in the embodiment of the present invention one in fabrication of semiconductor device.
Fig. 8 ~ Figure 10 is the structural representation in the embodiment of the present invention two in fabrication of semiconductor device.
Figure 11 is the relation schematic diagram that the volume ratio of oxygen and forming gas in the embodiment of the present invention two and the nitration case of grid curb wall remove thickness.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is: manufacture in the process of semiconductor device utilizing stress technology of closing on; form the material of the silicon nitride layer of grid curb wall for mixing phosphorous nitride silicon or boron-doping silicon nitride; when removing all or part of silicon nitride layer; the plasma adopting forming gas and oxygen to be formed is removed; this plasma can not damage the metal silicide layer be positioned on source area, drain region and grid; thus application stress close on technology basis on protect the thickness of metal silicide layer, protect the device performance of semiconductor device further.
Embodiment one
Fig. 1 is the schematic flow sheet of method, semi-conductor device manufacturing method in the embodiment of the present invention one, Fig. 2 ~ Fig. 7 is the structural representation in the embodiment of the present invention one in fabrication of semiconductor device, shown in Fig. 1 ~ Fig. 4, the invention provides and a kind ofly apply the manufacture method that stress closes on the semiconductor device of technology, comprise the following steps:
Step S01: as shown in Figure 2, provides semi-conductive substrate 100, described Semiconductor substrate is formed with grid 102;
Described Semiconductor substrate 100 can be monocrystalline silicon, the semi-conducting materials such as polysilicon or germanium silicon compound, the necessary structure in order to form semiconductor device such as various isolated component and various doped regions is also formed in described Semiconductor substrate 100, described isolated component is such as fleet plough groove isolation structure (STI) 102, described doped region (not indicating in Fig. 1) is such as N trap, P trap and lightly-doped source drain region (LDD), said structure is determined according to actual semiconductor device manufacture craft process, be well known to those skilled in the art technology contents, do not repeat them here.
Described grid 102 comprises gate dielectric layer 102a and is formed at the grid conducting layer 102b on described gate dielectric layer 102a, described gate dielectric layer 102a can adopt common dielectric material, such as, one in oxide, nitride, nitrogen oxide or its combination, described gate dielectric layer 102a can adopt thermal oxidation method or chemical vapour deposition technique (CVD) to be formed.The material of described grid conducting layer 102b can be polysilicon, and chemical vapour deposition technique can be adopted to be formed, and the thickness of described grid conducting layer 102b is such as 500 dust ~ 3000 dusts.
Step S02: as shown in Figure 3, described grid 102 sidewall forms grid curb wall 104, described grid curb wall 104 comprises oxide layer 104a and is positioned at the nitration case 104b outside oxide layer 104a, and the material of described nitration case 104b is boron-doping silicon nitride or mixes phosphorous nitride silicon.
In the present embodiment, described grid curb wall 104 is oxide-nitride structure (ON structure), the material of described oxide layer 104a is silica, the material of described nitration case 104b is boron-doping silicon nitride or mixes phosphorous nitride silicon, chemical vapour deposition technique can be adopted to form described boron-doping silicon nitride or mix phosphorous nitride silicon, preferably reaction temperature is 400 DEG C ~ 600 DEG C, the thickness of described nitration case 104 is 100 dust ~ 500 dusts, the preferably thickness of nitration case 104b is 300 dusts, and this thickness can produce good stress.The reacting gas of wherein said boron-doping silicon nitride comprises methane, diborane, ammonia and nitrogen, and the reacting gas of described boron-doping silicon nitride comprises methane, hydrogen phosphide, ammonia and nitrogen.Described nitration case 104b can using plasma etching remove in subsequent steps, to reduce the stressor layers of follow-up formation and the distance between Semiconductor substrate and grid, enable the stress of stressor layers act in Semiconductor substrate and grid better, improve the performance of semiconductor device.
Step S03: as shown in Figure 4, forms source area 106 and drain region 107 in the Semiconductor substrate 100 of described grid 104 both sides;
In the present embodiment, the source and drain of carrying out Doped ions in the Semiconductor substrate 100 of described grid 104 both sides is injected, to form source area and drain region, the source and drain of nmos device then being carried out to N-type Doped ions is injected, and the source and drain of PMOS device then being carried out to P type Doped ions is injected.
Step S04: as shown in Figure 5, described grid 104, described source area 106 and drain region 107 form metal silicide layer 108a, 108b, 108c;
Described grid 104, described source area 106 and drain region 107 form metal silicide layer 108a, 108b, 108c, its forming process is as follows, first, adopt chemical vapour deposition (CVD) (CVD) or the mode of physical vapour deposition (PVD) (PVD) metal to be deposited on the surface of grid 104, described source area 106 and drain region 107, metal forms metal silicide with pasc reaction in high-temperature annealing process.The material of described metal silicide layer 108a, 108b, 108c can be one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.Metal silicide layer 108a, 108b, 108c is nickel-silicon compound in the present embodiment, nickel beam-plasma is utilized to be sputtered onto in described Semiconductor substrate 100, with the silicon generation chemical reaction in described Semiconductor substrate 100 in subsequent high temperature annealing process, thus form nickel-silicon compound.Described metal silicide layer 108a, 108b, 108c for improve source area 106 in Semiconductor substrate 100, drain region 107 and grid 102 and follow-up formation metal interconnecting wires between the resistance characteristic at interface, contribute to the electrical extraction of source area 106, drain region 107 and grid 102.
Step S05: as shown in Figure 6, utilizes plasma etching to remove all or part of described nitration case 104b;
In the present embodiment, can according to actual size requirement, select to remove all or part of nitration case 104b, wherein said plasma gas comprises forming gas (FormingGas) and oxygen, the volume ratio of described oxygen and described forming gas is 0.1: 1 ~ 2: 1, wherein, described forming gas comprises nitrogen and hydrogen, and the volume ratio that described hydrogen accounts for described forming gas is 4% ~ 20%.Forming gas is gas conventional in semiconductor technology, can produce good etching removal ability when described hydrogen accounts for volume ratio 4%, 10% of described forming gas.In described forming gas containing hydrogen, Hydrogen Energy enough penetrates in nitration case 104b destroys silicon-nitrogen key, form nitrogen-hydrogen bond and silicon-hydrogen bond, after Doping Phosphorus or boron, its valence link combines with silicon, unnecessary valence link more easily adsorbs hydrogen ion, hydrogen ion is combined with silicon, destroy silicon-nitrogen key quickly, the speed that nitration case 104b is removed is faster, simultaneously, hydrogen ion can not with the metal silicide layer 108a of the materials such as nickel-silicon compound, 108b, 108c reacts, thus reach removal silicon nitride layer 104b and do not damage metal silicide layer 108a, 108b, the object of 108c.
Step S06: as shown in Figure 7, described Semiconductor substrate 100 covers stressor layers 110.Described stressor layers 110 covers described grid 102, grid curb wall and Semiconductor substrate 100, and wherein, the material of described stressor layers 106 is silicon nitride, and its thickness range is 200 dust ~ 600 dusts.Silicon nitride is as stressor layers 110, and its stress memory is good, and silicon nitride is common material in semiconductor technology, and manufacturing cost is relatively low.Can using plasma chemical vapour deposition (CVD) (PECVD), low-pressure chemical vapor deposition (LPCVD), the method such as rapid thermalization chemical vapour deposition (CVD) (RTCVD) or high density plasma deposition (HDP) being formed of stressor layers 110, the reacting gas of employing can comprise SiH
4, SiH
2cl
2, SiH
2f
2and NH
3, described stressor layers 110 preferably thickness is 200 ~ 1000 dusts, can reach preferably stress memory effect in subsequent high temperature annealing process.
After this, the manufacturing process of semiconductor device of the present invention can also comprise other processing steps, carries out high-temperature annealing process, and the annealing temperature of described high-temperature annealing process is 900 DEG C ~ 1300 DEG C, in this step, stressor layers 110 pairs of Semiconductor substrate 100 and grid 102 produce effect of stress; Then, described Semiconductor substrate 100 covers formation first medium layer; Then, carry out the processing step such as contact hole, metal lead wire etc., be those skilled in the art's common technique means, do not repeat at this.
Embodiment two
Fig. 8 ~ Figure 10 is the structural representation in the embodiment of the present invention two in fabrication of semiconductor device.As shown in Figure 8, in the present embodiment, described semiconductor device is CMOS transistor, and described CMOS transistor comprises nmos pass transistor 20 and PMOS transistor.The manufacture process of described CMOS transistor, on the basis of embodiment one, comprises the steps:
First, as shown in Figure 8, follow the process of step S01 described in embodiment one, NMOS grid 202 and PMOS grid 302 is formed respectively in described Semiconductor substrate 100, described NMOS grid 202 comprises NMOS gate dielectric layer 202a and NMOS grid conducting layer 202b, and described PMOS grid 302 comprises PMOS gate dielectric layer 302a and PMOS grid conducting layer 302b; Follow the process of step S02 described in embodiment one, NMOS grid curb wall 204 is formed in described NMOS grid 202 both sides, described NMOS grid curb wall 204 comprises the first oxide layer 204a and the first nitration case 204b, PMOS side wall 304 is formed in described PMOS grid 302 both sides, described PMOS side wall 304 comprises the first oxide layer 304a and the first nitration case 304b, and the technique forming NMOS grid curb wall 204 and PMOS side wall 304 all follows the step S02 of embodiment one.
Then, as shown in Figure 9, follow the process of step S03 described in embodiment one, the source and drain of carrying out N-type Doped ions in the Semiconductor substrate 100 to NMOS grid 202 both sides is injected, form nmos source district 206 and NMOS drain region 207, the source and drain of carrying out P type Doped ions in the Semiconductor substrate 100 to PMOS grid 302 both sides is injected, form PMOS source polar region 306 and PMOS drain region 307, follow the process of step S04 described in embodiment one, at the grid 202 of described nmos pass transistor 20, source area 206, drain region 207 is formed metal silicide layer 208a, 208b, 208c, with the grid 302 of described PMOS transistor 30, source area 306 and drain region 307 form metal silicide layer 308a, 308b, 308c.
Finally, as shown in Figure 10, follow the process of step S05 described in embodiment one, plasma etching is utilized to remove all or part of nitration case 202b of NMOS grid curb wall 202, remove all or part of nitration case 302b of PMOS grid curb wall 302, follow the process of step S06 described in embodiment one, described Semiconductor substrate 100 covers stressor layers 110, in subsequent high temperature annealing process, described stressor layers 110 pair nmos transistor 20 and PMOS transistor 30 play stress memory effect, improve the device performance of nmos pass transistor 20 and PMOS transistor 30.
After this, the manufacturing process of semiconductor device of the present invention also comprises other processing steps, carries out high-temperature annealing process, and the annealing temperature of described high-temperature annealing process is 900 DEG C ~ 1300 DEG C, in this step, stressor layers 110 pairs of Semiconductor substrate 100 produce effect of stress; Then, described Semiconductor substrate 100 covers formation first medium layer; Then, carry out the processing step such as contact hole, metal lead wire etc., be those skilled in the art's common technique means, do not repeat at this.
Figure 11 is the relation schematic diagram that the volume ratio of oxygen and forming gas in the unit interval in the embodiment of the present invention two and the nitration case of grid curb wall remove thickness.As shown in figure 11, the volume range of oxygen and forming gas is 0.1 ~ 2, for PMOS transistor, when described volume ratio is 0.1: 1, the removal speed of grid curb wall nitration case is best, for nmos pass transistor, when described volume ratio is 0.1 ~ 2: 1, it is substantially constant that grid curb wall nitration case removes speed, therefore, in plasma oxygen and forming gas preferably volume ratio be 0.1: 1, best removal speed can be reached, reduce the process time, improve process rate.
In sum, compared to prior art, manufacture in the process of semiconductor device utilizing stress technology of closing on, the material forming the silicon nitride layer of grid curb wall adopts mixes phosphorous nitride silicon or boron-doping silicon nitride, and when removing all or part of silicon nitride layer, the plasma adopting forming gas and oxygen to be formed is removed, this plasma can not damage and be positioned at source area, metal silicide layer on drain region and grid, thus maintain the thickness of metal silicide layer, and then on the basis that application stress closes on technology, protect the thickness of metal silicide layer, improve the overall performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (8)
1. apply the manufacture method that stress closes on the semiconductor device of technology, comprising:
Semi-conductive substrate is provided, described Semiconductor substrate is formed with grid;
Described gate lateral wall forms grid curb wall, and described grid curb wall comprises oxide layer and is positioned at the nitration case of oxide layer sidewall, and the material of described nitration case is boron-doping silicon nitride or mixes phosphorous nitride silicon;
Source area and drain region is formed in the Semiconductor substrate of described grid both sides;
Described grid, described source area and drain region form metal silicide layer;
Plasma etching is utilized to remove all or part of described nitration case, the etching gas of described plasma etch process comprises forming gas and oxygen, the volume ratio of described oxygen and described forming gas is 0.1: 1 ~ 2: 1, described forming gas comprises nitrogen and hydrogen, the volume ratio that described hydrogen accounts for described forming gas is 4% ~ 20%, not to be etched damage to protect metal silicide layer;
Cover stressor layers on the semiconductor substrate.
2. application stress as claimed in claim 1 closes on the manufacture method of the semiconductor device of technology, it is characterized in that, adopts chemical vapor deposition method to form described nitration case.
3. application stress as claimed in claim 2 closes on the manufacture method of the semiconductor device of technology, it is characterized in that, when the material of described nitration case is boron-doping silicon nitride, the reacting gas of described chemical vapor deposition method comprises methane, diborane, ammonia and nitrogen.
4. application stress as claimed in claim 2 closes on the manufacture method of the semiconductor device of technology, it is characterized in that, when the material of described nitration case is for mixing phosphorous nitride silicon, the reacting gas of described chemical vapor deposition method comprises methane, hydrogen phosphide, ammonia and nitrogen.
5. the application stress as described in Claims 2 or 3 or 4 closes on the manufacture method of the semiconductor device of technology, it is characterized in that, the reaction temperature of described chemical vapor deposition method is 400 DEG C ~ 600 DEG C.
6. application stress as claimed in claim 1 closes on the manufacture method of the semiconductor device of technology, and it is characterized in that, the thickness of described nitration case is 100 dust ~ 500 dusts.
7. application stress as claimed in claim 1 closes on the manufacture method of the semiconductor device of technology, and it is characterized in that, the material of described metal silicide layer is nickel-silicon compound.
8. application stress as claimed in claim 1 closes on the manufacture method of the semiconductor device of technology, and it is characterized in that, the material of described stressor layers is nitration case, and thickness is 200 dust ~ 600 dusts.
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| CN103489781A (en) * | 2012-06-13 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device by utilizing stress memory technology |
| CN105097684B (en) * | 2014-04-22 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN111681961B (en) * | 2020-07-24 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| US20060099763A1 (en) * | 2004-10-28 | 2006-05-11 | Yi-Cheng Liu | Method of manufacturing semiconductor mos transistor device |
| JP5091397B2 (en) * | 2005-10-27 | 2012-12-05 | パナソニック株式会社 | Semiconductor device |
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