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CN102981591A - Method and system capable of reducing power consumption of computer system in sleep mode - Google Patents

Method and system capable of reducing power consumption of computer system in sleep mode Download PDF

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Publication number
CN102981591A
CN102981591A CN2011102610855A CN201110261085A CN102981591A CN 102981591 A CN102981591 A CN 102981591A CN 2011102610855 A CN2011102610855 A CN 2011102610855A CN 201110261085 A CN201110261085 A CN 201110261085A CN 102981591 A CN102981591 A CN 102981591A
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computer system
output voltage
normal mode
sleep pattern
storer
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杨景翔
陈志诚
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Acer Inc
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Acer Inc
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Abstract

The invention relates to a method for reducing power consumption of a computer system in a sleep mode and a related computer system. Before a computer system enters a sleep mode from a normal mode, a state data is written into a memory in the computer system. After entering the sleep mode, a first output voltage is provided to the memory and power supply to other components in the computer system is stopped. And before returning to the normal mode from the sleep mode, supplying a second output voltage to the memory, wherein the value of the first output voltage is smaller than that of the second output voltage. The power consumption in the sleep mode can be further reduced, and the sleep standby time can be prolonged.

Description

可降低电脑系统在睡眠模式下功率消耗的方法及系统Method and system capable of reducing power consumption of computer system in sleep mode

技术领域 technical field

本发明涉及一种可降低电脑系统功率消耗的方法及相关电脑系统,尤指一种可降低电脑系统在睡眠模式下运行时功率消耗的方法及相关电脑系统。The invention relates to a method for reducing power consumption of a computer system and a related computer system, especially to a method for reducing power consumption of a computer system in sleep mode and a related computer system.

背景技术 Background technique

高级配置和电源接口(Advanced Configuration and Power Interface,ACPI)是由Intel、Microsoft、Phoenix、HP和Toshiba等厂商共同制定的电脑电源管理规格,目的是让操作系统可以直接地管理各种装置利用电源的状况。Advanced Configuration and Power Interface (ACPI) is a computer power management specification jointly developed by manufacturers such as Intel, Microsoft, Phoenix, HP, and Toshiba. The purpose is to allow the operating system to directly manage the use of power by various devices. situation.

现行ACPI架构下定义出电脑系统运作时的不同状态和电源模式:正常工作状态G0包含S0模式,睡眠状态G1包含S1~S4模式,而开机状态G2包含S5模式。以下简述在S0~S5模式下电脑系统中主要组件的供电情形:Under the current ACPI architecture, different states and power modes of the computer system are defined: the normal working state G0 includes the S0 mode, the sleep state G1 includes the S1-S4 modes, and the power-on state G2 includes the S5 mode. The following is a brief description of the power supply of the main components in the computer system in the S0~S5 mode:

S0模式:电脑系统的操作系统以及应用程序都在执行,且持续供电给所有组件;S0 mode: The operating system and application programs of the computer system are running, and power is continuously supplied to all components;

S1模式:中央处理单元(central processing unit,CPU)停止执行指令,但仍持续供电给CPU和其它组件;S1 mode: the central processing unit (central processing unit, CPU) stops executing instructions, but continues to supply power to the CPU and other components;

S2模式:停止供电给CPU,但仍持续供电给其它组件;S2 mode: Stop supplying power to the CPU, but continue to supply power to other components;

S3模式:仅持续供电给存储器,但停止供电给其它组件;S3 mode: only continuously supplies power to the memory, but stops supplying power to other components;

S4模式:将存储器资料写入硬盘,停止供电给所有组件;S4 mode: Write the memory data into the hard disk, stop supplying power to all components;

S5模式:完全关闭所有组件。S5 Mode: Completely shut down all components.

S3模式又可称之为STR(Suspend to RAM)模式,在微软XP或者Linux操作系统中叫做待机状态(stand-by),而在微软Vista或者Mac OS X操作系统中则叫做睡眠状态(sleep)。在S3模式下,电脑系统会将暂存资料载入存储器,并且让存储器以外的零件都停止工作。因此,若使用者暂时不需使用,可让电脑系统进入S3模式以节省耗电,而在需要使用时亦可快速立即回复电脑状态。S3 mode can also be called STR (Suspend to RAM) mode, which is called standby state (stand-by) in Microsoft XP or Linux operating system, and called sleep state (sleep) in Microsoft Vista or Mac OS X operating system . In the S3 mode, the computer system will load the temporary data into the memory, and stop the parts other than the memory. Therefore, if the user does not need to use it temporarily, the computer system can enter the S3 mode to save power consumption, and it can also quickly and immediately restore the computer state when it needs to be used.

在现有技术中ACPI架构下的电脑系统中,并未另外针对S3模式做省电设计,存储器的供电状况并非最佳化,因此仍有可能造成不必要的能量消耗。In the prior art, in the computer system under the ACPI architecture, there is no power-saving design for the S3 mode, and the power supply of the memory is not optimized, so unnecessary energy consumption may still be caused.

发明内容 Contents of the invention

本发明提供一种可降低一电脑系统在一睡眠模式下运行时功率消耗的方法,其包含在从一正常模式进入该睡眠模式前,将一资料写入该电脑系统中一存储器;在进入该睡眠模式后,将一第一输出电压供电给该存储器,并停止供电给该电脑系统中其它组件;以及在从该睡眠模式进入该正常模式前,将一第二输出电压供电给该存储器,其中该第一输出电压的值小于该第二输出电压的值。The present invention provides a method for reducing power consumption when a computer system operates in a sleep mode, which includes writing a data into a memory in the computer system before entering the sleep mode from a normal mode; After the sleep mode, supplying power to the memory with a first output voltage, and stopping power supply to other components in the computer system; and before entering the normal mode from the sleep mode, supplying power to the memory with a second output voltage, wherein The value of the first output voltage is smaller than the value of the second output voltage.

本发明另提供一种可降低一睡眠模式下功率消耗的电脑系统,其包含一存储器;一中央处理单元,用来在从一正常模式进入该睡眠模式前,将一资料写入该存储器;一电源供应;以及一微处理器,用来调整该电源供应使其在该睡眠模式下将一第一输出电压供电给该存储器,以及在从该睡眠模式回到该正常模式前将一第二输出电压供电给该存储器,其中该第一输出电压的值小于该第二输出电压的值。The present invention also provides a computer system capable of reducing power consumption in a sleep mode, which includes a memory; a central processing unit, used to write a data into the memory before entering the sleep mode from a normal mode; power supply; and a microprocessor, which is used to adjust the power supply to supply a first output voltage to the memory in the sleep mode, and a second output voltage before returning to the normal mode from the sleep mode A voltage is supplied to the memory, wherein the value of the first output voltage is less than the value of the second output voltage.

在本发明中,在睡眠模式下存储器仅需微小的自我刷新电流即可维持资料,电源供应仅通过执行自我刷新所需的最小电压来供电给存储器,能更进一步降低睡眠模式下的耗电量,藉以提升睡眠待机时间。In the present invention, the memory only needs a small self-refresh current to maintain data in the sleep mode, and the power supply only supplies power to the memory through the minimum voltage required to perform self-refresh, which can further reduce power consumption in the sleep mode , so as to improve the sleep standby time.

附图说明 Description of drawings

图1为本发明中一低耗能电脑系统的示意图。FIG. 1 is a schematic diagram of a low energy consumption computer system in the present invention.

图2为本发明电脑系统运行时的流程图。Fig. 2 is a flowchart of the operation of the computer system of the present invention.

其中in

10-CPU    20-电源供应    30-存储器10-CPU 20-Power Supply 30-Memory

40-微处理器    100-电脑系统40-microprocessor 100-computer system

具体实施方式 Detailed ways

图1为本发明中一低耗能电脑系统100的示意图。电脑系统100包含一CPU 10、一电源供应20、一存储器30,以及一微处理器40,可在一正常模式和一睡眠模式之间切换。FIG. 1 is a schematic diagram of a low power consumption computer system 100 in the present invention. The computer system 100 includes a CPU 10, a power supply 20, a memory 30, and a microprocessor 40, which can be switched between a normal mode and a sleep mode.

图2为本发明电脑系统100运行时的流程图,其包含下列步骤:FIG. 2 is a flowchart of the operation of the computer system 100 of the present invention, which includes the following steps:

步骤210:供电给电脑系统100内所有组件以在正常模式下运作,执行步骤220。Step 210 : Provide power to all components in the computer system 100 to operate in the normal mode, go to step 220 .

步骤220:判断是否需要进入睡眠模式:若是,执行步骤230;若否,执行步骤210。Step 220: Determine whether to enter the sleep mode: if yes, execute step 230; if not, execute step 210.

步骤230:将资料写入存储器30,执行步骤240。Step 230: Write the data into the memory 30, go to step 240.

步骤240:将一第一输出电压供电给存储器30,并停止供电给电脑系统100内其它组件以进入睡眠模式,执行步骤250。Step 240 : Supply a first output voltage to the memory 30 , and stop supplying power to other components in the computer system 100 to enter the sleep mode, go to step 250 .

步骤250:判断是否需要离开睡眠模式:若是,执行步骤260;若否,执行步骤240。Step 250: Determine whether to leave the sleep mode: if yes, execute step 260; if not, execute step 240.

步骤260:将一第二输出电压供电给存储器30,执行步骤210。Step 260 : Supply a second output voltage to the memory 30 , go to step 210 .

在本发明的实施例中,正常模式可为ACPI的S0模式,即在步骤210中电源供应20会供电给电脑系统100中所有组件。此时CPU 10和存储器30之间可透过数据总线来进行传输,进而执行操作系统以及应用程序。In the embodiment of the present invention, the normal mode can be the S0 mode of ACPI, that is, the power supply 20 supplies power to all components in the computer system 100 in step 210 . At this time, the CPU 10 and the memory 30 can transmit through the data bus, and then execute the operating system and the application program.

在本发明的实施例中,睡眠模式可为ACPI的S3模式,若是在步骤220中判断需进入睡眠模式,此时CPU 10会在步骤230中将涉及操作系统、所有应用程序和被开启档案的状态等资料写入存储器30中,如此当之后回到正常模式后,电脑系统100可快速地回复至进入睡眠模式前的初始状态。In an embodiment of the present invention, the sleep mode can be the S3 mode of ACPI. If it is judged in step 220 that it needs to enter the sleep mode, then the CPU 10 will involve the operating system, all application programs, and opened files in step 230. The status and other data are written into the memory 30, so that when returning to the normal mode later, the computer system 100 can quickly return to the initial state before entering the sleep mode.

在步骤240中,CPU 10会在启动微处理器40后被关闭,并停止供电给电脑系统100内其它组件以进入睡眠模式。在睡眠模式下,微处理器40会调整电源供应20使其能提供第一输出电压给存储器30。若是在步骤250中判断需离开睡眠模式,微处理器40会调整电源供应20使其能提供第二输出电压给存储器30。In step 240, the CPU 10 will be shut down after starting the microprocessor 40, and stop supplying power to other components in the computer system 100 to enter the sleep mode. In the sleep mode, the microprocessor 40 adjusts the power supply 20 to provide the first output voltage to the memory 30 . If it is determined in step 250 that the sleep mode needs to be exited, the microprocessor 40 adjusts the power supply 20 to provide the second output voltage to the memory 30 .

在本发明之实施例中,存储器30可为一种非永久性存储器(volatile memory),例如动态随机存取存储器(Dynamic Random AccessMemory,DRAM),主要的作用原理是利用电容内存存电荷的多少来代表一个二进位位是1还是0。在实际应用中,电容无可避免地会有漏电情形。为了避免电荷漏失影响资料的完整性,存储器30必须周期性地执行自我刷新(self refresh)的充电动作。In an embodiment of the present invention, the memory 30 can be a non-permanent memory (volatile memory), such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), the main principle of action is to use the amount of charge stored in the capacitor to Represents whether a binary bit is 1 or 0. In practical applications, capacitors will inevitably have leakage. In order to prevent the charge leakage from affecting the integrity of the data, the memory 30 must perform a self-refresh charging operation periodically.

微处理器40可为一低功率的电压调整电路,例如利用电阻分压来调整电源供应20的输出电压。在本发明中,第一输出电压的值在睡眠模式下存储器30的可正常工作范围内,第二输出电压则为电源供应20的正常输出电压。由于在睡眠模式下存储器30仅需微小的自我刷新电流即可维持资料,因此第一输出电压的值小于第二输出电压。The microprocessor 40 can be a low-power voltage adjustment circuit, such as using resistor divider to adjust the output voltage of the power supply 20 . In the present invention, the value of the first output voltage is within the normal operating range of the memory 30 in the sleep mode, and the second output voltage is the normal output voltage of the power supply 20 . Since the memory 30 only needs a small self-refresh current to maintain data in the sleep mode, the value of the first output voltage is smaller than the second output voltage.

在本发明中,进入睡眠模式后电源供应20仅通过执行自我刷新所需的最小电压来供电给存储器30,在离开睡眠模式前再以正常输出电压供电给存储器30,因此能更进一步降低睡眠模式下的耗电量,藉以提升睡眠待机时间。In the present invention, after entering the sleep mode, the power supply 20 only supplies power to the memory 30 through the minimum voltage required to perform self-refresh, and then supplies power to the memory 30 with a normal output voltage before leaving the sleep mode, so that the sleep mode can be further reduced. Lower power consumption, in order to improve sleep standby time.

以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,都应属于本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. the method for a power consumption can reduce a computer system and under a sleep pattern, move the time, its step comprises:
Before entering this sleep pattern from a normal mode, a data is write a storer in this computer system;
After entering this sleep pattern, one first output voltage is powered to this storer, and stop power supply to other assembly in this computer system;
And before entering this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
2. the method for claim 1 is characterized in that, also be included in enter this normal mode after, continued power is given all component in this computer system.
3. the method for claim 1 is characterized in that, but also comprises the value that decides this first output voltage according to the operating voltage range of this storer when the charging of carrying out a self-refreshing is moved.
4. the method for claim 1 is characterized in that, but also comprises the value that decides this first output voltage according to this reservoir required minimum operating voltage when the charging of carrying out a self-refreshing is moved.
5. the method for claim 1 is characterized in that, this normal mode is the S0 pattern under an ACPI (ACPI) framework, and this sleep pattern is the S3 pattern under this ACPI framework.
6. the method for claim 1 is characterized in that, judging whether needs to enter this sleep pattern from this normal mode, or enters this normal mode from this sleep pattern.
7. the method for claim 1 is characterized in that, this data relates under this normal mode the be unlocked state of archives of an operating system, an application program or in this computer system.
8. computer system that can reduce power consumption under the sleep pattern, it comprises:
One storer:
One CPU (central processing unit) is used for before entering this sleep pattern from a normal mode data being write this storer:
One power supply supply; And
One microprocessor, being used for adjusting this power supply supply powers one first output voltage to this storer it under this sleep pattern, and before getting back to this normal mode from this sleep pattern, one second output voltage is powered to this storer, wherein the value of this first output voltage is less than the value of this second output voltage.
9. computer system as claimed in claim 8 is characterized in that, this microprocessor is controlled this power supply supply and made it stop power supply to this CPU (central processing unit) in order to after entering this sleep pattern.
10. computer system as claimed in claim 9 is characterized in that, adopts an ACPI framework, and this normal mode is the S0 pattern under this ACPI framework, and this sleep pattern is the S3 pattern under this ACPI framework.
CN2011102610855A 2011-09-05 2011-09-05 Method and system capable of reducing power consumption of computer system in sleep mode Pending CN102981591A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9348770B1 (en) 2014-11-20 2016-05-24 Industrial Technology Research Institute Non-volatile semiconductor memory device with temporary data retention cells and control method thereof
CN106560761A (en) * 2015-10-01 2017-04-12 联想企业解决方案(新加坡)有限公司 Computer system and method for providing both main power and auxiliary power on a single power bus
CN106775491A (en) * 2016-12-30 2017-05-31 北京联想核芯科技有限公司 Data processing method and storage device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060198225A1 (en) * 2005-03-04 2006-09-07 Seagate Technology Llc Reducing power consumption in a data storage system
US20080082845A1 (en) * 2006-09-29 2008-04-03 Kabushiki Kaisha Toshiba Information processing apparatus and system state control method
CN101581962A (en) * 2009-06-19 2009-11-18 北京红旗胜利科技发展有限责任公司 Method for reducing CPU power consumption and CPU
US20100250981A1 (en) * 2009-03-30 2010-09-30 Lenova (Singapore) Pte. Ltd. Dynamic memory voltage scaling for power management
CN101916138A (en) * 2010-08-06 2010-12-15 北京中星微电子有限公司 Method and device for switching working state and sleep state of central processing unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060198225A1 (en) * 2005-03-04 2006-09-07 Seagate Technology Llc Reducing power consumption in a data storage system
US20080082845A1 (en) * 2006-09-29 2008-04-03 Kabushiki Kaisha Toshiba Information processing apparatus and system state control method
US20100250981A1 (en) * 2009-03-30 2010-09-30 Lenova (Singapore) Pte. Ltd. Dynamic memory voltage scaling for power management
CN101581962A (en) * 2009-06-19 2009-11-18 北京红旗胜利科技发展有限责任公司 Method for reducing CPU power consumption and CPU
CN101916138A (en) * 2010-08-06 2010-12-15 北京中星微电子有限公司 Method and device for switching working state and sleep state of central processing unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9348770B1 (en) 2014-11-20 2016-05-24 Industrial Technology Research Institute Non-volatile semiconductor memory device with temporary data retention cells and control method thereof
CN106560761A (en) * 2015-10-01 2017-04-12 联想企业解决方案(新加坡)有限公司 Computer system and method for providing both main power and auxiliary power on a single power bus
CN106775491A (en) * 2016-12-30 2017-05-31 北京联想核芯科技有限公司 Data processing method and storage device
CN106775491B (en) * 2016-12-30 2019-05-31 北京联想核芯科技有限公司 Data processing method and storage equipment

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Application publication date: 20130320