CN102970093B - The synchro system of compatible multiple clock and synchronous method thereof - Google Patents

Abstract

The invention discloses a synchronization system compatible with multiple clocks and a synchronization method thereof. The system includes units such as an external clock matching amplifying unit, and the external clock matching amplifying unit is connected with a first multivibrator 10MHz frequency selection unit and a clock driving unit. The first 10MHz bandpass filter amplifying unit is connected with the first multivibrator 10MHz frequency selection unit and the internal and external reference clock selection unit, the internal time base signal generation unit is connected with the second multivibrator 10MHz frequency selection unit, and the second 10MHz bandpass The filter amplifying unit is connected with the second multivibrator 10MHz frequency selection unit, the internal and external reference clock selection unit, and the clock drive unit is connected with the control unit and the internal and external reference clock selection unit. The present invention is compatible with various clock inputs of 1MHz, 2MHz, 5MHz and 10MHz, provides a default 10MHz clock output, and can select 1MHz, 2MHz, and 5MHz clock outputs according to the external input clock frequency to solve the problem that different clock frequencies cannot be synchronized.

Description

A Synchronization System Compatible with Multiple Clocks and Its Synchronization Method

technical field

The invention relates to a synchronization system, in particular to a synchronization system compatible with multiple clocks and a synchronization method thereof.

Background technique

With the development of testing technology, there are more and more cases where various measuring instruments are used together, and there are more and more cases where various measuring instruments are used to build test systems for testing. In order to ensure the accuracy and accuracy of measurement, eliminate Due to the measurement error introduced by the clock asynchrony of each measuring instrument, it is often necessary to synchronize the clock signals of the measuring instruments used. However, due to the different standard clock frequencies selected by various instrument manufacturers, the output clock signals they provide are also different. For example, some provide 1MHz clock output, some provide 5MHz clock output, and some provide 10MHz clock output. The clock input is mostly 10MHz, which will cause the clocks of the various instruments to be out of synchronization, thereby increasing the measurement error.

Existing solutions can basically be classified into two types. The first solution is a frequency multiplication and division clock synchronization solution. The first solution realizes the synchronization of internal and external clocks through frequency multiplication or frequency division. Specifically, when the selected standard clock is lower than 10MHz, in order to provide a standard 10MHz output clock, the clock synchronization system is often designed as a frequency multiplication circuit, as shown in Figure 1 and Figure 2. When the selected standard clock is 1MHz, a 10-frequency multiplication unit is required to generate an output clock of 10MHz. When the selected standard clock is 5MHz, it needs to go through a 2 frequency multiplication unit to generate an output clock of 10MHz. At the same time, in order to be able to synchronize with the external clock of the instrument, a corresponding frequency division circuit must be designed to generate the internal clock signal.

The second solution is to directly select the 10MHz time base for clock synchronization, that is, regardless of the cost, directly select the 10MHz clock as the internal standard clock of the instrument, so that the 10MHz reference clock output can be directly provided.

The disadvantages of the first solution are as follows: poor compatibility, only 10MHz clock can be synchronized, when the external reference is 1MHz, 2MHz, 5MHz commonly used clock frequency, it is still impossible to achieve clock synchronization.

The disadvantages of the second scheme are as follows: the cost is high, and the 10MHz standard time base should be selected as the internal reference clock when the instrument does not need to use the 10MHz clock, and the price of the 10MHz standard time base is 30% to 50% more expensive than the price of the 5MHz or 1MHz time base. %about. At the same time, there is also the same problem of poor compatibility as the first solution, which can only synchronize the 10MHz clock, and cannot synchronize common clocks of other frequencies.

Contents of the invention

The technical problem to be solved by the present invention is to provide a synchronization system and synchronization method compatible with multiple clocks, which can be compatible with 1MHz, 2MHz, 5MHz and 10MHz multiple clock inputs, and provide a default 10MHz clock output. Select 1MHz, 2MHz, 5MHz clock output to solve the problem that different clock frequencies cannot be synchronized, so as to ensure the accuracy of instrument measurement and eliminate measurement errors caused by clock asynchrony.

The present invention solves the above-mentioned technical problems through the following technical solutions: a synchronous system compatible with multiple clocks, characterized in that it includes an external clock matching amplifier unit, an internal time base signal generating unit, a first multivibrator 10MHz Frequency selection unit, second multivibrator 10MHz frequency selection unit, first 10MHz bandpass filter amplification unit, second 10MHz bandpass filter amplification unit, internal and external reference clock selection unit, clock drive unit and control unit, external clock matching The amplifying unit is connected with the first multivibrator 10MHz frequency selection unit and the clock drive unit, the first 10MHz bandpass filter amplifying unit is connected with the first multivibrator 10MHz frequency selection unit, and the internal and external reference clock selection unit, and the internal time base signal is generated The unit is connected to the second multivibrator 10MHz frequency selection unit, the second 10MHz bandpass filter amplifying unit is connected to the second multivibrator 10MHz frequency selection unit, the internal and external reference clock selection unit, the clock drive unit is connected to the control unit, internal and external reference clock Select the cell connection.

Preferably, the function of the external clock matching amplifying unit is mainly to block and impedance-match the clock signal provided externally by the instrument with a frequency of 1, 2, 5 or 10 MHz, and at the same time input the clipping protection circuit for clipping, and then enter the A two-stage amplifier circuit composed of triodes is used for amplification.

Preferably, the first multivibrator 10MHz frequency selection unit is triggered by a 1, 2, 5 or 10MHz clock signal input after limiting amplification, and through a 10MHz frequency selection network composed of LC circuits, the 1, 2, 5 Or the 10MHz clock signal is converted into a 10MHz clock signal.

Preferably, the first 10MHz bandpass filter amplifying unit filters the 10MHz external clock signal after frequency selection by the first multivibrator 10MHz frequency selection unit through an LC bandpass filter composed of inductance and capacitance, and then performs two Stage amplification, so that the 10MHz clock signal meets the requirements for level conversion from sinusoidal to TTL, and is provided to the internal and external reference clock selection unit.

Preferably, the internal and external reference clock selection unit includes a time base detection unit, a first NAND gate, a second NAND gate, a third NAND gate, the time base detection unit and the first NAND gate, the second NAND gate connected, the third NAND gate is connected with the first NAND gate and the second NAND gate.

The present invention also provides a synchronization method for a synchronization system compatible with multiple clocks, characterized in that the synchronization method for a synchronization system compatible with multiple clocks uses the above-mentioned synchronization system compatible with multiple clocks, and the synchronization system compatible with multiple clocks The synchronization method of the synchronization system includes the following steps:

S1. The external clock matching amplifying unit performs DC blocking, impedance matching, limiting and amplifying the clock signal with a frequency of 1, 2, 5 or 10 MHz;

S2. The first multivibrator 10MHz frequency selection unit converts the 1, 2, 5 or 10MHz clock signals processed by the external clock matching amplifier unit into 10MHz external clock signals;

S3. The first 10MHz bandpass filter amplifying unit filters and amplifies the 10MHz external clock signal after the frequency selection by the first multivibrator 10MHz frequency selection unit, and provides it to the internal and external reference clock selection unit after filtering and amplifying;

S4. The internal time base signal generation unit selects 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator as the internal time base standard according to the needs;

S5. The second multivibrator 10MHz frequency selection unit converts the 1MHz, 2MHz, 5MHz or 10MHz clock signals of the internal time base signal generating unit into 10MHz internal clock signals;

S6. The second 10MHz bandpass filter amplifying unit filters and amplifies the 10MHz internal clock signal after the frequency selection by the second multivibrator 10MHz frequency selection unit, and provides it to the internal and external reference clock selection unit after filtering and amplifying;

S7. The internal and external reference clock selection unit selects a 10MHz external clock signal or a 10MHz internal clock signal as required;

S8. The clock signal selected by the internal and external reference clock selection unit becomes multi-channel clock output after being driven by the clock drive unit;

S9. As for the clock provided for external use, it is controlled by the control unit to select whether the output is a 10 MHz clock or an externally provided 1, 2 or 5 MHz clock.

The positive progress effect of the present invention is: one, the present invention can be compatible with the clock input signal of four different frequencies of 1MHz, 2MHz, 5MHz and 10MHz, the output clock signal that provides simultaneously except 10MHz, can also select according to the clock signal of external input The output is a 1MHz, 2MHz or 5MHz clock, which solves the problem that the signals of different clock frequencies cannot be synchronized. Two, no matter what the internal time base of the present invention selects is 1MHz, 2MHz, 5MHz or 10MHz, all can use the synchronous system of the present invention compatible with multiple clocks and its synchronous method to produce 10MHz clock signal, the circuit is simple, cost is low, compatibility is good .

Description of drawings

FIG. 1 is a functional block diagram of an internal and external clock synchronization system when the existing internal clock is 1 MHz.

FIG. 2 is a functional block diagram of an internal and external clock synchronization system when the existing internal clock is 5 MHz.

Fig. 3 is a functional block diagram of the synchronization system compatible with multiple clocks of the present invention.

Fig. 4 is a functional block diagram of the external clock matching amplifying unit in the present invention.

Fig. 5 is a functional block diagram of the first multivibrator 10MHz frequency selection unit in the present invention.

Fig. 6 is a functional block diagram of the first 10MHz bandpass filter amplifying unit in the present invention.

FIG. 7 is a functional block diagram of an internal and external reference clock selection unit in the present invention.

Fig. 8 is a functional block diagram of a clock driving unit and a control unit in the present invention.

Detailed ways

The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings to describe the technical solution of the present invention in detail.

As shown in Figure 3, the synchronous system compatible with multiple clocks of the present invention includes an external clock matching amplifying unit, an internal time base signal generating unit, a first multivibrator 10MHz frequency selection unit, a second multivibrator 10MHz frequency selection unit, and a second multivibrator 10MHz frequency selection unit. A 10MHz band-pass filter (Band-PassFilter, BPF) amplifying unit, a second 10MHz band-pass filter amplifying unit, an internal and external reference clock selection unit, a clock drive unit and a control unit, an external clock matching amplifying unit and the first multivibrator The 10MHz frequency selection unit is connected to the clock drive unit, the first 10MHz bandpass filter amplifying unit is connected to the first multivibrator 10MHz frequency selection unit, and the internal and external reference clock selection unit, and the internal time base signal generation unit is connected to the second multivibrator 10MHz The frequency selection unit is connected, the second 10MHz bandpass filter amplifying unit is connected with the second multivibrator 10MHz frequency selection unit, the internal and external reference clock selection unit, and the clock drive unit is connected with the control unit and the internal and external reference clock selection unit.

The function of the external clock matching amplifier unit is mainly to provide a clock signal with a frequency of 1, 2, 5 or 10MHz (the clock signal is a sinusoidal signal or a square wave signal with an amplitude greater than 0.6Vp-p) provided by the instrument, as shown in Figure 4. The external The clock matching amplifying unit includes a DC blocking unit, an impedance matching unit, a limiting protection circuit and an amplifying circuit. The DC blocking unit, an impedance matching unit, a limiting protection circuit and an amplifying circuit are connected in sequence. Matching, and at the same time, the input limit protection circuit limits the limit to prevent the input signal from being too large. Then it enters into a two-stage amplifier circuit composed of triodes for amplification to meet the input signal requirements of the first multivibrator 10MHz frequency selection unit. Taking a sinusoidal signal with an input frequency of 1MHz and an amplitude of 0.6Vp-p as an example, it becomes a sinusoidal signal with an amplitude of 2.4Vp-p after matching and amplifying by an external clock, which satisfies the minimum high level of the first multivibrator 10MHz frequency selection unit. 2V trigger requirement.

The first multivibrator 10MHz frequency selection unit converts the 1, 2, 5 or 10MHz clock signals processed by the external clock matching amplifier unit into 10MHz external clock signals, as shown in Figure 5, the first multivibrator 10MHz frequency selection unit It includes a multivibrator unit and a frequency selection unit, and the multivibrator unit is connected to the frequency selection unit. The specific working process is as follows: the 1, 2, 5 or 10MHz clock signal input after limiting amplification is used as a trigger, and the monostable multivibrator is selected. The oscillator (model 74LS221) is designed as a multivibrator unit. The output signal of the multivibrator unit is a series of harmonic signals of the frequency of the external clock signal with a pulse width of 50ns, and passes through a 10MHz frequency selection network composed of LC circuits. , converting 1, 2, 5 or 10MHz clock signals into 10MHz clock signals. The first multivibrator 10MHz frequency selection unit may be composed of a multivibrator.

As shown in FIG. 6 , the first 10 MHz bandpass filter amplifying unit includes an LC bandpass filter and a triode. The function of the first 10MHz bandpass filter amplifying unit is as follows: the first 10MHz bandpass filter amplifying unit passes the 10MHz external clock signal after the frequency selection of the first multivibrator 10MHz frequency selection unit through the LC bandpass filter composed of inductors and capacitors filter, and then use the triode for two-stage amplification, so that the 10MHz clock signal meets the requirements for level conversion from sinusoidal to TTL, and provides it to the internal and external reference clock selection unit.

The internal time base signal generation unit can choose 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator as the internal time base standard according to the needs of the instrument. Then, like the external clock signal, enter the second multivibrator 10MHz frequency selection unit, the second multivibrator 10MHz frequency selection unit converts the 1MHz, 2MHz, 5MHz or 10MHz clock signal of the internal time base signal generation unit into a 10MHz internal clock After the signal is filtered and amplified by the second 10MHz band-pass filter amplifying unit, it is provided to the internal and external reference clock selection unit. The internal time base channel of the internal time base signal generation unit adopts the same processing method as the external time base channel, and uses the second multivibrator 10MHz frequency selection unit to replace the frequency multiplication unit in the implementations shown in Figures 1 and 2. The advantage is that it can be used The crystal oscillator with low price and low frequency is used as the internal time base reference, and the internal time base with different frequencies can realize 10MHz reference output with a set of circuits. The circuit is simple, compatible and versatile. The functional block diagram of the second multivibrator 10MHz frequency selection unit is the same as the functional block diagram of the first multivibrator 10MHz frequency selection unit shown in Figure 5, and the functional block diagram of the second 10MHz bandpass filter amplification unit is the same as that shown in Figure 6 The block diagram of the first 10MHz bandpass filter amplification unit is the same.

Selection of internal and external reference clock selection unit Select 10MHz external clock signal or 10MHz internal clock signal as required. The functional block diagram of internal and external reference clock selection unit is shown in Figure 7. The internal and external reference clock selection unit includes a time base detection unit and a first NAND gate U1 -A, the second NAND gate U1-B, the third NAND gate U1-C, the time base detection unit is connected with the first NAND gate U1-A, the second NAND gate U1-B, the third NAND gate U1-C is connected to the first NAND gate U1-A and the second NAND gate U1-B. The internal and external reference clock selection unit first converts the sinusoidal signal into a TTL signal, which is sent from the first 10MHz bandpass filter amplification unit. The external clock signal becomes a TTL signal and the TTL signal is divided into two paths, one path is used as an input of the second NAND gate U1-B, and the other path is sent to the time base detection unit. The time base detection unit uses a retriggerable multivibrator (model 74LS123) to form an automatic detection circuit. The width of the trigger pulse is designed to be 1.2μs, and the external clock becomes a signal with a pulse width of 50ns after conversion. When there is an external clock signal input, the Q terminal output of the multivibrator is high level, and the /Q terminal output is low level; when there is no external clock signal input, the Q terminal output is low level, and the /Q terminal output is high level. The output signal of the Q terminal of the time base detection unit is connected to the other input terminal of the second NAND gate U1-B to control the output of the NAND gate. After the internal time base signal becomes TTL level, it is used as one input of the 2-input first NAND gate U1-A, and the other input of the first NAND gate U1-A is output from the /Q terminal of the time base detection unit. When there is an external clock signal, the output of the Q terminal of the time base detection unit is high level, the output of the /Q terminal is low level, the output of the NAND gate U1-A is high level, the internal clock signal is prohibited, and the external clock The signal is valid and can be output to the third NAND gate U1-C; otherwise, the output of the Q terminal of the time base detection unit is low level, the output of the /Q terminal is high level, and the output of the second NAND gate U1-B is High level, the external clock signal is disabled, the internal clock signal is valid, and can be output to the third NAND gate U1-C, so as to realize the automatic switching of internal and external clock signals.

The main function of the clock drive unit is to convert the clock signal (i.e. 10MHz signal) selected by the internal and external reference clock selection unit into multiple clock outputs after being driven by the clock drive unit, and provide them for the internal use of the instrument and the external use of the instrument respectively. NOR gate line driver (such as 74128 model) can be used as a clock drive unit. As shown in FIG. 8, the clock driving unit may include a first NOR gate U2-A, a second NOR gate U2-B, and a third NOR gate U2-C.

As for the clock provided for external use, it can be selected to output a 10MHz clock or an externally provided 1, 2 or 5MHz clock through the control of the control unit. As shown in Figure 8, the control unit includes a first AND gate U3-A, a second AND gate U3-B and a fourth NOR gate U2-D, the first AND gate U3-A, the second AND gate U3-B are all Connect with the fourth NOR gate U2-D. The first control signal CTRL1 and the second control signal CTRL2 come from the central processing unit (CPU). When the first control signal CTRL1 is high level and the second control signal CTRL2 is low level, the output of the first AND gate U3-A is 10MHz, the output of the second AND gate U3-B is low level, so the clock output of the fourth NOR gate U2-D is 10MHz. When the first control signal CTRL1 is at low level and the second control signal CTRL2 is at high level, the output of the first AND gate U3-A is at low level, and the output of the second AND gate U3-B is an externally input 1MHz, 2MHz or 5MHz, so the clock output of the fourth NOR gate U2-D is 1MHz, 2MHz or 5MHz. Thus, the function of providing a default 10MHz clock output and optional 1MHz, 2MHz or 5MHz clock output according to the external input clock is realized.

The synchronization method of the synchronization system compatible with multiple clocks of the present invention comprises the following steps:

S1. The external clock matching amplifying unit performs DC blocking, impedance matching, limiting and amplifying the clock signal with a frequency of 1, 2, 5 or 10 MHz;

S2. The first multivibrator 10MHz frequency selection unit converts the 1, 2, 5 or 10MHz clock signals processed by the external clock matching amplifier unit into 10MHz external clock signals;

S3. The first 10MHz bandpass filter amplifying unit filters and amplifies the 10MHz external clock signal after the frequency selection by the first multivibrator 10MHz frequency selection unit, and provides it to the internal and external reference clock selection unit after filtering and amplifying;

S4. The internal time base signal generation unit selects 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator as the internal time base standard according to the needs;

S5. The second multivibrator 10MHz frequency selection unit converts the 1MHz, 2MHz, 5MHz or 10MHz clock signals of the internal time base signal generating unit into 10MHz internal clock signals;

S6. The second 10MHz bandpass filter amplifying unit filters and amplifies the 10MHz internal clock signal after the frequency selection by the second multivibrator 10MHz frequency selection unit, and provides it to the internal and external reference clock selection unit after filtering and amplifying;

S7. The internal and external reference clock selection unit selects a 10MHz external clock signal or a 10MHz internal clock signal as required;

S8. The clock signal selected by the internal and external reference clock selection unit becomes multi-channel clock output after being driven by the clock drive unit;

S9. As for the clock provided for external use, it is controlled by the control unit to select whether the output is a 10 MHz clock or an externally provided 1, 2 or 5 MHz clock.

The working principle of the present invention is as follows: when the external input clock signal is 1MHz, 2MHz, 5MHz or 10MHz, firstly after matching and amplifying, it enters into the first multivibrator 10MHz frequency selection unit, and the first multivibrator 10MHz frequency selection unit The output signal is a series of harmonic signals of the external clock signal with a pulse width of 50ns. For example, when the external clock is 1MHz, the output signal of the first multivibrator 10MHz frequency selection unit is composed of the fundamental wave of 1MHz and various harmonics, of which the 10th harmonic is the 10MHz signal; when the external clock is 2MHz, the first multivibrator The output of the harmonic oscillation 10MHz frequency selection unit is composed of 2MHz fundamental wave and various harmonics, among which the 5th harmonic is the 10MHz signal; when the external clock is 5MHz, the output of the first multivibrator 10MHz frequency selection unit is composed of 5MHz The fundamental wave and various harmonics are composed, and the second harmonic is 10MHz; when the external input is 10MHz, the output of the first multivibrator 10MHz frequency selection unit is composed of the fundamental wave and various harmonics of 10MHz, among which The fundamental wave is 10MHz; in this way, through the 10MHz frequency selection unit, the 10MHz signal is retained, and the rest of the harmonic signals are attenuated, thus realizing the conversion of 1MHz, 2MHz, 5MHz or 10MHz signals into 10MHz signals. After being filtered and amplified by the first 10MHz bandpass filter amplifying unit, it is sent to the internal and external reference clock selection unit. The internal time base signal generation unit can choose 1, 2, 5 or 10MHz crystal oscillator as the internal time base standard according to the needs, which is the same as the external input clock. After the second multivibrator 10MHz frequency selection unit, it also becomes The 10MHz signal is sent to the internal and external reference clock selection unit after being filtered and amplified by the second 10MHz bandpass filter amplifying unit. As shown in Figure 7, when there is an external clock 10MHz signal (this 10MHz is 10MHz after multivibrator frequency selection and amplification), the output of the Q terminal of the time base detection unit is a high level 1, and the output of the /Q terminal is a low level. Level 0, the output of U1-C is an external clock; when there is no external clock, the output of the Q terminal of the time base detection unit is low level 0, the output of /Q terminal is high level 1, the third NAND gate U1-C The output is the internal clock. After being selected by the internal and external reference, it is provided to the driving circuit, and after being driven, it becomes a multi-channel signal for internal and external use of the instrument respectively. As shown in FIG. 8 , the signal provided for external use can be controlled by the first control signal CTRL1 and the second control signal CTRL2 to realize whether the output is 10 MHz or 1, 2 or 5 MHz. When the first control signal CTRL1 is high level 1 and the second control signal CTRL2 is low level 0, the clock output of the fourth NOR gate U2-D is 10MHz; when the first control signal CTRL1 is low level 0, If the second control signal CTRL2 is high level 1, the clock output of the fourth NOR gate U2-D is 1, 2 or 5 MHz. Therefore, the present invention can realize compatibility with 1, 2, 5 or 10MHz external clock reference, provide default 10MHz clock output, and select 1, 2 or 5MHz clock output according to the externally input clock. In summary, the present invention can be compatible with clock input signals of four different frequencies of 1MHz, 2MHz, 5MHz and 10MHz, and the output clock signal can be 1MHz, 2MHz or 5MHz clock according to the external input clock besides 10MHz. Regardless of whether the internal time base is 1MHz, 2MHz, 5MHz or 10MHz, the synchronization system and synchronization method compatible with multiple clocks of the present invention can be used to generate a 10MHz clock signal.

Various modifications and changes can be made to the present invention by those skilled in the art. Thus, the present invention covers the modifications and changes that come within the scope of the appended claims and their equivalents.

Claims (6)

1. the synchro system of a compatible multiple clock, it is characterized in that, it comprises external clock coupling amplifying unit, internal timebase signal generation unit, first multi-harmonic-oscillations 10MHz frequency-selecting unit, second multi-harmonic-oscillations 10MHz frequency-selecting unit, one 10MHz band pass filter amplifying unit, 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver cell and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, clock driver cell connects, one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, clock driver cell and control unit, inside and outside reference clock selected cell connects,

External clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;

1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;

10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by the one 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;

Internal timebase signal generation unit needs to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;

Second multi-harmonic-oscillations 10MHz frequency-selecting unit all converts 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;

10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;

Inside and outside reference clock selected cell is selected to select 10MHz external timing signal or 10MHz internal clock signal as required;

Clock signal after inside and outside reference clock selected cell selection becomes multipath clock and exports after clock driver cell drives;

1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.

2. the synchro system of compatible multiple clock as claimed in claim 1; it is characterized in that; the function of described external clock coupling amplifying unit by the frequency that instrument outside provides be mainly 1,2,5 or 10MHz clock signal carry out every straight, impedance matching; input saturation protective circuit carries out amplitude limit simultaneously, then enters the two-stage amplifying circuit be made up of triode and amplifies.

3. the synchro system of compatible multiple clock as claimed in claim 2, it is characterized in that, described first multi-harmonic-oscillations 10MHz frequency-selecting unit with input after limited range enlargement 1,2,5 or 10MHz clock signal for trigger, through the 10MHz frequency-selective network be made up of lc circuit, 1,2,5 or 10MHz clock signal are all converted to 10MHz clock signal.

4. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, a described 10MHz band pass filter amplifying unit is by the LC band-pass filter of the 10MHz external timing signal after the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being made up of inductance capacitance, then triode is utilized to carry out two-stage amplification, make 10MHz clock signal meet the requirement changed to Transistor-Transistor Logic level by sine, be supplied to inside and outside reference clock selected cell.

5. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, base detecting unit, the first NAND gate, the second NAND gate, the 3rd NAND gate when described inside and outside reference clock selected cell comprises, time base detecting unit be connected with the first NAND gate, the second NAND gate, the 3rd NAND gate is connected with the first NAND gate, the second NAND gate.

6. the synchronous method of the synchro system of a compatible multiple clock, it is characterized in that, the synchronous method of the synchro system of described compatible multiple clock adopts the synchro system of compatible multiple clock according to claim 1, and the synchronous method of the synchro system of described compatible multiple clock comprises the following steps:

S1, external clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;

1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;

10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S3, a 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;

S4, internal timebase signal generation unit need to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;

S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;

10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S6, the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;

S7, inside and outside reference clock selected cell are selected to select 10MHz external timing signal or 10MHz internal clock signal as required;

Clock signal after the selection of S8, inside and outside reference clock selected cell becomes multipath clock and exports after clock driver cell drives;

S9, be 1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.