CN102969697B - Control method for overvoltage protection and control circuit for power supply controller - Google Patents

Abstract

A control circuit for a power supply controller and a method of controlling over-voltage protection. The power controller is powered by an operating power supply terminal. The operating power supply terminal has an operating power supply voltage. When the operating power voltage exceeds an overvoltage reference value, the power controller stops the power conversion of a power converter. The control circuit includes a slope detector. The slope detector detects a change slope of the operating power supply voltage. And when the change slope exceeds a descending slope, the slope detector recovers the power conversion of the power converter. When the power conversion of the power converter is recovered, the power controller compares the operating power voltage with the overvoltage reference value.

Description

Control method for overvoltage protection and control circuit for power supply controller

technical field

The present invention relates to a control circuit and a control method in a power controller, especially to a control circuit and a control method for over voltage protection in a power controller.

Background technique

A power converter is an indispensable electronic device in electronic products, which is used to provide the voltage or current power required by other electronic devices. The power converter must also be designed to provide many different protections, such as over load protection (OLP), over temperature protection (OTP), output short protection (output short protection), over voltage protection ( over voltage protection) and so on. These protections are used to prevent disasters that may be caused by the power converter in abnormal conditions.

When the feedback loop that senses the output voltage is broken, OVP prevents the output voltage from going high because the power converter keeps increasing its output power. Excessively high output voltages can cause damage to powered electronic devices.

FIG. 1 shows a known power converter 8 including a flyback topology 10 , an operation power supply 12 , and a power controller 18 . The operating power supply 12 provides an operating power voltage V _CC to supply power to the power controller 18 . The power controller 18 can be a monolithic integrated circuit.

When the feedback loop for detecting the output voltage V _OUT on the output terminal OUT is broken, the output voltage V _OUT may surge abnormally high. Correspondingly, the operating power voltage V _CC supplied by the operating power supply 12 will also increase. When the operating power voltage V _CC reaches a certain level, the power controller 18 will stop the power conversion of the power converter 8 to reach OVP.

FIG. 2 illustrates the power controller 18 , which includes an oscillation circuit 40 , a pulse-width modulator 44 , an OVP control circuit 30 , and a gate logic controller 42 . The oscillator circuit 40 provides the clock for the power controller 18 . The pulse width regulator 44 determines the current duty cycle. The OVP control circuit 30 uses the power good signal S _PG to tell the logic circuit 42 whether the operating power voltage V _CC is normal (power good). The logic circuit 42 controls the power switch 15 through the gate terminal GATE.

FIG. 3A shows the operating power voltage V _CC and the power good signal S _PG when a general OVP occurs. In FIG. 3A , the operating power supply voltage V _CC initially rises slowly. At time point _t1 , the operating power supply voltage V _CC is higher than the overvoltage reference value V _REF-OVP , the comparator 34 resets the SR recorder 32, and the power good signal S _PG transitions to logic 0. , so the logic circuit 42 determines that the current operating power supply voltage V _CC is not good (not good), so the power switch 15 is kept in the closed state, and the power conversion is stopped.

The power conversion stops, and the operating power supply voltage V _CC will gradually decrease due to the power consumption of the power controller 18 . If the operating power supply voltage V _CC is lower than the reference voltage V _REF-RSTRT , the logic circuit 42 restarts (restarts) to start power conversion, and pulls up the operating power supply voltage V _CC . However, only when the operating power supply voltage V _CC recovers to be higher than the reference voltage V _REF-UV , as shown at time _t2 , the comparator 36 and the one-shot circuit 38 will make the power good signal S _PG transition to a logical state. 1, informs the logic circuit 42 that the current operating power supply voltage V _CC is normal (good).

FIG. 3B shows the operating power voltage V _CC and the power good signal S _PG when noise appears briefly at the operating power terminal VCC. As shown in FIG. 3B , at the time point t ₃ , due to noise, the operating power supply voltage V _CC suddenly rises, thus triggering the OVP. Although the noise disappears quickly, the operating power supply voltage V _CC is still the same as in Figure 3A. It needs to slowly drop to the reference voltage V _REF-RSTRT to restart the power conversion, and then recover to a value higher than the reference voltage V _REF-UV At the time point t ₄ , the operating power supply voltage V _CC is considered normal. It can be seen from FIG. 3B that the power conversion of the power controller 18 in FIG. 2 will go through a rather long stagnation period T _HOLD .

Contents of the invention

An embodiment of the present invention provides a control method for overvoltage protection, including: detecting an operating power supply voltage; comparing the operating power supply voltage with an overvoltage reference value; when the operating power supply voltage exceeds the overvoltage reference value, stopping Power conversion of a power converter; detecting a change slope of the operating power supply voltage; and, when the change slope exceeds a falling slope, resuming power conversion of the power converter.

The embodiment of the invention also provides a control circuit for a power controller. The power controller is powered by an operating power terminal. The operating power terminal has an operating power voltage. When the operating power supply voltage exceeds an overvoltage reference value, the power controller stops power conversion of a power converter. The control circuit includes a slope detector. The slope detector detects a change slope of the operating power supply voltage. And when the changing slope exceeds a falling slope, the slope detector resumes the power conversion of the power converter. After the power conversion of the power converter is resumed, the power controller compares the operating power voltage with the overvoltage reference value.

Description of drawings

Figure 1 shows a known power converter.

Figure 2 illustrates a power controller.

FIG. 3A shows the operating power voltage V _CC and the power good signal S _PG of FIG. 2 when a general OVP occurs.

FIG. 3B shows the operating power voltage V _{CC and the power good signal S PG in} FIG. 2 when noise appears briefly at the operating power terminal VCC.

FIG. 4 shows an OVP control circuit implemented according to the present invention.

FIG. 5A shows the operating power voltage V _CC , the reverse overvoltage signal S _OVP-B , the set signal S _SET , and the power good signal S _PG in FIG. 4 when a general OVP occurs.

FIG. 5B shows the operating power voltage V _CC , the reverse overvoltage signal S _OVP-B , the set signal S _SET , and the power good signal S _PG in FIG. 4 when noise appears temporarily at the operating power terminal VCC.

[Description of main component labels]

8 Power Converter 10 Flyback Architecture

12 Operating the power supply 15 Power switch

18 Power Controller 30 OVP Control Circuit

32 SR Recorder 34 Comparator

36 Comparator 38 Single pulse circuit

40 oscillating circuit 42 logic circuit

44 Pulse Width Regulator 60 OVP Control Circuit

62 Low Pass Filter 64 Comparator

66 Multiplexer 68 Comparator

70 AND Gate GATE Gate End

OUT output terminal S _OVP-B reverse overvoltage signal

S _PG power ready signal S _SET setting signal

t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , t ₆ , t ₇ , t ₈ , t ₉ , t ₁₀ time points

T _HOLD stagnation period V _CC operating power supply voltage

V _CC-LPF filtered voltage V _OUT output voltage

V _REF-OVP overvoltage reference value V _REF-RSTRT reference voltage

V _REF-UV reference voltage

Detailed ways

FIG. 4 shows an OVP control circuit 60 implemented according to the present invention, which can replace the OVP control circuit 30 in FIG. 2 . The OVP control circuit 60 can quickly resume power conversion after the short-term noise disappears, and can shorten the excessively long stagnation period T _HOLD in FIG. 3B .

The OVP control circuit 60 has a comparator 64 , a comparator 68 , a multiplexer (multiplexer) 66 , a low-pass filter 62 , and an AND gate (And Gate) 70 .

The low-pass filter 62 detects the operating power supply voltage V _CC and performs low-pass filtering to generate a filtered voltage V _CC-LPF . As can be known from simple circuit theory, the low-pass filter 62 is equivalent to limiting the response speed of the filtered voltage V _CC-LPF to the operating power supply voltage V _CC , and the distance between the operating power supply voltage V _CC and the filtered voltage V _CC-LPF The difference substantially corresponds to the change slope of the operating power supply voltage V _CC . For example, when the operation power supply voltage V _CC drops faster, the filtered voltage V _CC-LPF is higher than the operation power supply voltage V _CC by more.

When the inverse overvoltage signal S _OVP-B output by the comparator 64 is logic 1, the multiplexer 66 provides the overvoltage reference V _REF-OVP to the non-inverting input terminal of the comparator 64 . When the reverse overvoltage signal S _OVP-B is logic 0, the multiplexer 66 provides the filtered voltage V _CC-LPF to the non-inverting input terminal of the comparator 64 .

Therefore, when the reverse overvoltage signal S _OVP-B is logically 1, which means that no overvoltage has occurred, the comparator 64 compares the detected operating power supply voltage V _CC with the overvoltage reference value V _REF-OVP , Check to see if overvoltage occurs. When the reverse overvoltage signal S _OVP-B is logically 0, it means that an overvoltage has occurred, and the comparator 64 compares the operating power supply voltage V _CC with the filtered voltage V _CC-LPF . In essence, the comparator 64 is equivalent to is to detect the change slope of the operating power supply voltage V _CC .

In one embodiment, the comparator 64 has a hysteresis effect. When the reverse overvoltage signal S _OVP-B output by the comparator 64 is logic 1, the operating power supply voltage V _CC is higher than the overvoltage reference value V _REF-OVP , and the reverse overvoltage signal S _OVP-B will be transition to 0. When the reverse overvoltage signal S _OVP-B is logic 0, when the filtered voltage V _CC-LPF is higher than the operating power supply voltage V _CC by a preset value (for example, 0.5V), the reverse overvoltage signal S _OVP-B will change to 1. This preset value is equal to a specific falling slope corresponding to the operating power supply voltage V _CC . In other words, the comparator 64 and the low-pass filter 62 together form a slope detector for detecting the slope of the operating power supply voltage V _CC . When the changing slope exceeds the specified falling slope, the comparator 64 makes the reverse overvoltage signal S _OVP-B transition to 1.

The comparator 68 compares the operating supply voltage V _CC and the reference voltage V _REF-UV . When the operating power supply voltage V _CC is lower than the reference voltage V _REF-UV , the comparator 68 sets the comparator 64 with the set signal S _SET to make the reverse overvoltage signal S _OVP-B logic 1. In other words, the comparator 64 is forced to compare the operating power supply voltage V _CC with the overvoltage reference value V _REF-OVP .

Only when the operating power supply voltage V _CC is between the overvoltage reference value V _REF-OVP and the reference voltage V _REF-UV , the AND gate 70 will provide the enabled power ready signal S _PG to inform the logic circuit 42 of the operating power supply voltage V _CC is normal. Otherwise, the power good signal S _PG is logic 0, indicating that the operating power voltage V _CC is not normal.

FIG. 5A shows the operating power voltage V _CC , the reverse overvoltage signal S _OVP-B , the set signal S _SET , and the power good signal S _PG in FIG. 4 when a general OVP occurs. In FIG. 5A , it may be based on detecting the disconnection of the output voltage feedback loop, the operating power supply voltage V _CC initially rises slowly, and the reverse overvoltage signal S _OVP-B is logic 1, indicating that the operating power supply voltage V _CC is lower than Overvoltage reference value V _REF-OVP .

At time t ₅ , the operating power supply voltage V _CC is higher than the overvoltage reference value V _REF-OVP , and the comparator 64 makes the reverse overvoltage signal S _OVP-B transition to logic 0. Therefore, the power good signal S _PG becomes logically 0, which informs the logic circuit 42 that the current operation power supply voltage V _CC is not good (not good), thus keeps the power switch 15 in the off state, and stops the power conversion.

After the time point _t5 , because the operating power supply voltage V _CC only drops slowly with a small slope, the reverse overvoltage signal S _OVP-B remains at logic 0 all the time.

At time point _t6 , the operating supply voltage V _CC is lower than the reference voltage V _REF-UV , so the set signal S _SET transitions to logic 1, forcing the comparator 64 to compare the operating supply voltage V _CC with the overvoltage reference value V _REF-OVP . Also because the operating power supply voltage V _CC is lower than the overvoltage reference value V _REF-OVP at this time, the reverse overvoltage signal S _OVP-B is logic 1. At this time, the power good signal S _PG is still logic 0, and the power conversion is still stopped.

When the operating power supply voltage V _CC is lower than the reference voltage V _REF-RSTRT , the logic circuit 42 restarts (restarts), starts power conversion, and pulls up the operating power supply voltage V _CC .

At time point _t7 , the operating power supply voltage V _CC is higher than the reference voltage V _REF-UV , so the set signal S _SET transitions to a logic 0, and the power ready signal S _PG becomes a logic 1 to inform the logic circuit 42 The current operating supply voltage V _CC is correct.

FIG. 5A has approximately the same power good signal S _PG as that of FIG. 3A . Therefore, it can be seen that the OVP control circuit 60 in FIG. 4 can provide the correct OVP mechanism for general overvoltages as the OVP control circuit 30 in FIG. 2 .

FIG. 5B shows the operating power voltage V _CC , the reverse overvoltage signal S _OVP-B , the set signal S _SET , and the power good signal S _PG in FIG. 4 when noise appears temporarily at the operating power terminal VCC. Very different from FIG. 3B , the stagnation period T _HOLD of the power conversion in FIG. 5B is quite short, which means that the power conversion enters normal operation soon after the noise disappears. Therefore, compared to FIG. 3B , FIG. 5B also shows a relatively stable operating power supply voltage V _CC , which has a better voltage stabilization effect.

Before the time point _t8 , the operating power supply voltage V _CC suddenly rises due to the introduction of noise. At time point _t8 , when the operating power supply voltage V _CC exceeds the overvoltage reference value V _REF-OVP , the reverse overvoltage signal S _OVP-B immediately becomes logic 0, and the power ready signal S _PG becomes logic logic 0. 0, entering the power conversion stagnation period T _HOLD .

During the period between time points _t8 to _t9 , the comparator 64 detects the change slope of the operating power supply voltage V _CC . Because the operating power supply voltage V _CC either rises or falls not fast enough, the reverse overvoltage signal S _OVP-B output by the comparator 64 is always maintained at logic 0.

During the period between time point _t9 and _t10 , the change speed of the operating power supply voltage V _CC exceeds the preset drop speed of the comparator 64 and the low-pass filter 62, so the reverse overvoltage signal S _{OVP -B} transitions from a logical 0 to a logical 1, forcing the comparator 64 to compare the operating supply voltage V _CC with the overvoltage reference V _REF-OVPP . However, at this time, the operating power supply voltage V _CC still exceeds the overvoltage reference value V _REF-OVP , so the reverse overvoltage signal S _OVP-B will change from logic 1 to logic 0 again. Therefore, the reverse overvoltage signal S _OVP-B will continuously transition between logic 0 and 1. The power good signal S _PG also continuously transitions to make the power converter switch between stopping and resuming power conversion, as shown in FIG. 5B .

Until the time point t ₁₀ , the operating power supply voltage V _CC is determined to be lower than the overvoltage reference value V _REF-OVP , so the reverse overvoltage signal S _OVP-B will be stable at logic 1, and the power good signal S _PG will also be Then it stays at a logical 1, allowing the power conversion to operate normally.

It can be seen from FIG. 5B that the power good signal S _PG returns to logic 1 almost immediately after the noise disappears, so the power conversion hold-up period T _HOLD is very short. Thus, compared with the result of FIG. 3B , the result of FIG. 5B proves that the OVP control circuit 60 of FIG. 4 has a better voltage stabilizing effect.

In another embodiment, a high-pass filter can be used to detect the change slope of the operating power supply voltage V _CC , and then a comparator can be used to determine whether the change slope exceeds a falling slope, so as to achieve a similar effect as shown in FIG. 4 Restoring the functionality of electrical energy conversion.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A control method for overvoltage protection, comprising: Detecting an operating power supply voltage; comparing the operating power supply voltage with an overvoltage reference value; When the operating power supply voltage exceeds the overvoltage reference value, stopping power conversion of a power converter; detecting a change slope of the operating power supply voltage; and When the changing slope exceeds a falling slope, the power conversion of the power converter is resumed. 2. The control method of voltage protection according to claim 1, further comprising: providing a comparator; When the operating power supply voltage exceeds the overvoltage reference value, the comparator is used to detect the change slope; and When the changing slope exceeds the falling slope, the comparator is used to compare the operating power supply voltage with the overvoltage reference value. 3. The control method for voltage protection according to claim 2, further comprising: comparing the operating power supply voltage with a reference voltage; and When the operating power supply voltage is lower than the reference voltage, the comparator is used to compare the operating power supply voltage and the overvoltage reference value. 4. The control method for voltage protection according to claim 2, wherein the comparator has a hysteresis effect. 5. The control method for voltage protection according to claim 1, further comprising: performing low-pass filtering on the operating power supply voltage to generate a filtered voltage; comparing the filtered voltage with the operating supply voltage; and When the filtered voltage is higher than the operating power supply voltage by a preset value, the power conversion of the power converter is resumed. 6. A control circuit for a power controller, the power controller is powered by an operating power terminal, the operating power terminal has an operating power voltage, when the operating power voltage exceeds an overvoltage reference value, the power control The device stops the power conversion of a power converter, and the control circuit includes: a slope detector, used to detect a change slope of the operating power supply voltage, and when the change slope exceeds a falling slope, resume the power conversion of the power converter; Wherein, after the power conversion of the power converter is resumed, the power controller compares the operating power voltage and the overvoltage reference value. 7. The control circuit according to claim 6, wherein the slope detector comprises: A low-pass filter provides a filtered voltage according to the operating power supply voltage; and a first comparator having a first input terminal coupled to the operating power supply voltage, and a second input terminal coupled to the filtered voltage; Wherein, when the operating power supply voltage is lower than the filtered voltage to a preset value, a comparison result of the first comparator restores the power conversion of the power converter. 8. The control circuit according to claim 7, wherein the slope detector further comprises: A multiplexer, including: a first signal terminal coupled to the filtered voltage; a second signal terminal coupled to the overvoltage reference value; a control terminal coupled to an output terminal of the first comparator; and A multiplexer output terminal is coupled to the second input terminal of the first comparator. 9. The control circuit according to claim 7, wherein the first comparator has a hysteresis effect. 10. The control circuit according to claim 8, further comprising: a second comparator for comparing the operating power supply voltage and a reference voltage; Wherein, when the operating power supply voltage is lower than the reference voltage, the second comparator enables the multiplexer to select the overvoltage reference value and output it to the output terminal of the multiplexer. 11. The control circuit according to claim 7, further comprising: a second comparator for comparing the operating power supply voltage and a reference voltage; Wherein, when the operating power supply voltage is lower than the reference voltage, the second comparator sets the first comparator.