CN102968956B - Scanning driver for active organic electroluminescent display and driving method thereof - Google Patents

Abstract

The invention discloses a scan driver for an active organic electroluminescence display, which includes an N-level unit scan driver; each unit scan driver includes an input signal sampling module, a signal coupling module, an output stage of a circuit, and a circuit charge discharge module; The present invention only needs one type of transmission thin film transistor, which has been improved and optimized in reducing the leakage path and reducing the extra power consumption; each unit scan driver only needs one peripheral input, one clock control line, one positive power line, Two negative power lines greatly reduce the difficulty of driving, and the output terminal is connected to a DC power supply, which avoids the coupling effect of the clock jump on the parasitic capacitance of the output stage transistor and the power consumption caused by the charging and discharging of the capacitor.

Description

Scanning driver of active organic electroluminescence display and its driving method

technical field

The invention relates to the scanning driving technology of light-emitting diode display, in particular to the scanning driver of active organic electroluminescent display and its driving method.

Background technique

Organic light emitting diode (Organic Light Emitting Diode, OLED) display is a very promising next-generation display technology. The scan driver scans each row of pixels to ensure that the data of each frame of the display is updated. For active organic light-emitting diode displays, each pixel circuit needs peripheral scanning signals to control the writing and updating of grayscale data, and to realize the display function, which is an indispensable part of active display. The technical indicators of the scanning driver mainly include: speed, power consumption and drive capability, etc.

The traditional scan driver adopts CMOS technology, which is made into a chip, and then the chip is pressed on the contact keys on the periphery of the display through a COG machine. Due to the high chip cost, large chip area and array wire consumption area, a specific COG machine is required to press the chip, resulting in a very large cost consumption in the whole process, and it is not conducive to the realization of a narrow frame, which does not conform to the aesthetics of the human eye.

With the development of display technology, the requirements for scanning drivers are getting higher and higher, not only must they meet the needs of the driver in terms of function, but also consume less and less area, so that they can be bent or folded. Integrating scan drivers on glass substrates for active organic light-emitting diode displays has become a recent research hotspot. Integrating scan drivers on glass substrates not only reduces costs, reduces substrate area consumption, and reduces process steps, but also makes scan drivers on flexible substrates. On the substrate, flexible display is realized. However, there are problems that have to be solved. Thin film transistors made on glass substrates have low mobility, single transmission type, all N-type or all P-type transistors, and threshold voltage drift when voltage is applied for a long time. It will cause some devastating results such as malfunction of the scan driver, sudden change in power consumption, and smaller output swing. Therefore, it is also a very big challenge when designing a scan driver.

Contents of the invention

In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the object of the present invention is to provide a scan driver for an active organic electroluminescent display, which only needs a transmission type thin film transistor scan driver for an active organic electroluminescent display .

Another object of the present invention is to provide a driving method for the above-mentioned organic electroluminescence display.

The object of the present invention is achieved through the following technical solutions:

A scan driver for an active organic electroluminescent display, including N-level unit scan drivers; each unit scan driver includes an input terminal IN, a clock signal input terminal CLK, a reset terminal RESET, a first output terminal COUT and a second output terminal terminal OUT; the input terminal IN of the first-level unit scanning driver receives the start input signal; the output signal of the first output terminal COUT of the first-level unit scanning driver is used as the input signal of the next-level unit scanning input terminal IN; The output signal of the first output terminal COUT of the second to N-level unit scanning drivers is used as the start signal of the reset terminal RESET of the upper-level unit scanning driver;

Each unit scan driver includes:

The input sampling module includes first, second, third and fourth transistors; wherein the first and second transistors are turned on when the clock is at a high potential to control the conduction of the third and fourth transistors, thereby sampling the input signal;

The signal coupling module includes a fifth transistor and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, and the capacitor Cp couples the sampling signal according to the clock signal to control the output signal;

The output stage of the circuit includes the sixth, seventh, eighth, ninth, tenth, and eleventh transistors; the sixth and seventh transistors form a NOT gate, which is the inversion of the sampling signal; the eighth, ninth, and 10. The eleventh transistor forms two output terminals. The eighth and tenth transistors are connected to positive power supply to provide high-level output; the ninth and eleventh transistors are respectively connected to two negative levels to provide negative-level output;

The circuit charge discharge module includes the twelfth, thirteenth, fourteenth, and fifteenth transistors; the twelfth, thirteenth, fourteenth, and fifteenth transistors form a hold and discharge circuit for the sampling signal, The thirteenth transistor is controlled by the input signal to ensure that when the input signal is high, the output stage is low; the twelfth, fourteenth, and fifteenth transistors are controlled by the output signal of the next-level unit scan driver, and the next-level When the output signal of the unit scan driver is high, the twelfth, fourteenth and fifteenth transistors are turned on to discharge the charges.

For the first to N-level unit scan drivers: the source of the first transistor is connected to the drain of the second transistor and the gate of the third transistor, the gate of the first transistor is connected to the clock control line, and the drain of the first transistor is connected to the The input signal line of the level unit scanning driver; the gate of the second transistor is connected to the clock control line, the source of the second transistor is connected to the gate of the fourth transistor and the drain of the twelfth transistor; the drain of the third transistor is connected to the positive Power line, the source of the third transistor is connected to the drain of the fourth transistor; the source of the fourth transistor is connected to the drain of the thirteenth and fourteenth transistors, and the drains of the fifth, seventh, eighth and tenth transistors Gate and one end of capacitor Cp;

The drain of the fifth transistor is connected to the clock signal, the source of the fifth transistor is connected to the drain of the fifteenth transistor, and the other end of the capacitor Cp;

The drain and gate of the sixth transistor are connected to the positive power supply VDD, the source of the sixth transistor is connected to the drain of the seventh transistor and the gates of the ninth and eleventh transistors; the source of the seventh transistor is connected to the first negative power supply VSSL; the drain of the eighth transistor is connected to the positive power supply VDD; the source of the ninth transistor is connected to the first negative power supply VSSL, the drain of the tenth transistor is connected to the positive power supply VDD, and the source of the eleventh transistor is connected to the second negative power supply VSS ;

The gate of the twelfth transistor is connected to the RESET signal output by the next-level unit scan driver, the source of the twelfth transistor is connected to the second negative power supply VSS; the gate of the thirteenth transistor is connected to the input signal line of the scan driver of this stage, The source is connected to the first negative power supply VSSL; the source of the fourteenth transistor is connected to the first negative power supply VSSL, and the source of the fifteenth transistor is connected to the second negative power supply VSS;

For the first-level unit scan driver: the source of the eighth transistor is connected to the drain of the ninth transistor, and the input terminal of the next-level unit scan driver; the source of the tenth transistor is connected to the drain of the eleventh transistor and the pixel array ; The gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver;

For the unit scanning driver of the Nth level: the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the unit scanning driver of the upper level; the source of the tenth transistor is connected to the drain of the eleventh transistor;

For the 2nd to N-1 level unit scan drivers; the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the upper unit scan driver, the input terminal of the next unit scan driver; the tenth transistor The source of the eleventh transistor is connected to the drain of the eleventh transistor and the pixel array; the gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver; the gate of the fifteenth transistor is connected to the output signal of the next-level unit scan driver. RESET signal.

The first to fifteenth transistors in the unit scan driver are N-type transistors.

The driving method of the scanning driver of the described active organic electroluminescence display, comprises the following steps:

The first half cycle of the clock signal is low level, and the second half cycle is high level; the pulse width of the VIN signal is a clock signal of one cycle;

In the nth cycle of the clock signal, when the clock signal jumps to a high level, the nth level unit scan driver receives the input signal and starts the input sampling phase;

When the clock signal enters the n+1th cycle, the nth-level unit scan driver ends the input sampling phase and performs signal coupling and output; at the same time, the n+1-th unit scan driver uses the first output terminal COUT of the n-level unit scan driver The output signal of is the input signal, and the input sampling phase starts when the clock signal enters the second half cycle of the n+1th cycle;

In the n+2th cycle of the clock signal, the n+1th unit scan driver finishes the input sampling phase and performs the signal coupling output phase; at the same time, the nth unit scan driver uses the first output of the n+1th unit scan driver The output signal of the terminal COUT is used as the start signal of the reset terminal RESET, and the output signals of the first output terminal COUT and the second output terminal OUT of the nth-level unit scan driver are both set to a negative potential, and the signal discharge phase begins; n=1, 2, . . . , N-1.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

1. The scanning driver of the active organic electroluminescent display of the present invention only needs one type of transmission thin film transistor, which can meet the driving requirements of the display, and can work normally within the range of threshold voltage drift, and has less leakage channel, which can reduce additional power consumption.

2. The unit scanning driver of the scanning driver of the active organic electroluminescent display of the present invention only needs one peripheral input, one clock control line, one positive power supply line, and two negative power supply lines, which greatly reduces the difficulty of driving, and the output terminal is connected to The DC power supply is input to avoid the coupling effect of the clock jump on the parasitic capacitance of the output stage transistor and the power consumption caused by the charging and discharging of the capacitor.

Description of drawings

FIG. 1 is an overall schematic schematic diagram of a scan driver of an active organic electroluminescent display according to the present invention.

FIG. 2 is a timing diagram of a scan driver of an active organic electroluminescent display according to the present invention.

FIG. 3 is a schematic diagram of a unit scan driver of an active organic electroluminescent display according to the present invention.

FIG. 4 is a timing diagram of a unit scan driver of an active organic electroluminescent display according to the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

Example

As shown in Figure 1, the scanning driver of the active organic electroluminescent display includes N-level unit scanning drivers (the first level unit scanning driver 11, the second level unit scanning driver 12 are shown in the figure; the third level unit scanning driver 13; the fourth-level unit scan driver 14; the fifth-level unit scan driver 15; the sixth-level unit scan driver 16); each unit scan driver includes an input terminal IN, a clock signal input terminal CLK, and a reset terminal RESET, The first output terminal COUT and the second output terminal OUT; the input terminal IN of the first-level unit scanning driver receives the start input signal; the output signal of the first output terminal COUT of the 1st to N-1 level unit scanning driver is used as the next level The input signal of the input terminal IN of the unit scanning driver; the output signal of the first output terminal COUT of the 2nd to N-level unit scanning driver is used as the start signal of the reset terminal RESET of the upper-level unit scanning driver; the 1-N-1 level unit scanning driver The second output terminals OUT( 1 )˜OUT(N-1) are respectively connected to the scan lines SCAN( 1 )˜(N-1).

As shown in Figure 2, each unit scan driver includes:

The input sampling module 01 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the first and second transistors are turned on when the clock is at a high potential, and the third and fourth transistors are controlled to turn on situation, thereby sampling the input signal;

The signal coupling module 02 includes a fifth transistor T5 and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, and the capacitor Cp couples the sampling signal according to the clock signal to control the output signal;

The output stage 03 of the circuit includes the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11; where the sixth and seventh transistors form a NOT gate, which is Inversion of the sampling signal; the eighth, ninth, tenth, and eleventh transistors form two output terminals, and the eighth and tenth transistors are connected to the positive power supply to provide high-level output; the ninth and eleventh transistors are respectively connected to Two negative levels, providing negative level output;

The circuit charge discharge module 04 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15; the twelfth, thirteenth, fourteenth, and fifteenth transistors form a pair The hold and discharge circuit of the sampling signal, the thirteenth transistor is controlled by the input signal, to ensure that when the input signal is high, the output stage is low; the twelfth, fourteenth, and fifteenth transistors are scanned by the next-level unit The output signal of the driver is controlled. When the output signal of the scanning driver of the next-level unit is high, the twelfth, fourteenth and fifteenth transistors are turned on to discharge the charge.

For the first to N-level unit scan drivers: the source of the first transistor is connected to the drain of the second transistor and the gate of the third transistor, the gate of the first transistor is connected to the clock control line, and the drain of the first transistor is connected to the The input signal line of the level unit scanning driver; the gate of the second transistor is connected to the clock control line, the source of the second transistor is connected to the gate of the fourth transistor and the drain of the twelfth transistor; the drain of the third transistor is connected to the positive Power line, the source of the third transistor is connected to the drain of the fourth transistor; the source of the fourth transistor is connected to the drain of the thirteenth and fourteenth transistors, and the drains of the fifth, seventh, eighth and tenth transistors One terminal C of the gate and the capacitor Cp;

The drain of the fifth transistor is connected to the clock signal, the source of the fifth transistor is connected to the drain of the fifteenth transistor, and the other end D of the capacitor Cp;

The drain and gate of the sixth transistor are connected to the positive power supply VDD, the source of the sixth transistor is connected to the drain of the seventh transistor and the gates of the ninth and eleventh transistors; the source of the seventh transistor is connected to the first negative power supply VSSL; the drain of the eighth transistor is connected to the positive power supply VDD; the source of the ninth transistor is connected to the first negative power supply VSSL, the drain of the tenth transistor is connected to the positive power supply VDD, and the source of the eleventh transistor is connected to the second negative power supply VSS ;

The gate of the twelfth transistor is connected to the RESET signal output by the next-level unit scan driver, the source of the twelfth transistor is connected to the second negative power supply VSS; the gate of the thirteenth transistor is connected to the input signal line of the scan driver of this stage, The source is connected to the first negative power supply VSSL; the source of the fourteenth transistor is connected to the first negative power supply VSSL, and the source of the fifteenth transistor is connected to the second negative power supply VSS;

For the first-level unit scan driver: the source of the eighth transistor is connected to the drain of the ninth transistor, and the input terminal of the next-level unit scan driver; the source of the tenth transistor is connected to the drain of the eleventh transistor and the pixel array ; The gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver;

For the unit scanning driver of the Nth level: the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the unit scanning driver of the upper level; the source of the tenth transistor is connected to the drain of the eleventh transistor;

For the 2nd to N-1 level unit scan drivers; the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the upper unit scan driver, the input terminal of the next unit scan driver; the tenth transistor The source of the eleventh transistor is connected to the drain of the eleventh transistor and the pixel array; the gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver; the gate of the fifteenth transistor is connected to the output signal of the next-level unit scan driver. RESET signal.

The first to fifteenth transistors in the unit scan driver are N-type transistors.

As shown in FIG. 3, the driving method of the scan driver of the active organic electroluminescent display of the present embodiment includes the following steps:

The first half cycle of the clock signal is low level, and the second half cycle is high level; the pulse width of the VIN signal is a clock signal of one cycle; in the nth cycle of the clock signal, when the clock signal jumps high, the nth level The unit scan driver receives the input signal and starts the input sampling phase; when the clock signal enters the n+1th cycle, the nth level unit scan driver ends the input sampling phase and performs signal coupling output; at the same time, the n+1th level unit scan driver Taking the output signal of the first output terminal COUT(n) of the n-level unit scan driver as the input signal, the input sampling phase begins when the clock signal enters the second half cycle of the n+1 cycle; at the n+th cycle of the clock signal In 2 cycles, the n+1th level unit scan driver ends the input sampling phase and proceeds to the signal coupling output phase; at the same time, the nth level unit scan driver uses the first output terminal COUT(n+1) of the n+1th level unit scan driver The output signal of the reset terminal RESET is used as the start signal of the reset terminal, and the output signals of the first output terminal COUT(n) and the second output terminal OUT(n) of the nth-level unit scan driver are both set to negative potentials, and the signal leakage starts. release stage; where n=1, 2, . . . , N-1.

As shown in Figure 4, the input sampling stage is specifically: the clock control line controls the switching states of the first and second transistors, the clock signal changes from high level to low level, and the input signal changes from low level to high level. The first and second transistors are turned off, points A and B are kept low to maintain the off state of the third and fourth transistors, the thirteenth transistor is turned on, and the potential of point C is pulled down to the first negative power supply VSSL, so that The fifth, seventh, eighth and tenth transistors are turned off, and E is charged to the positive power supply VDD through the sixth transistor, so that the ninth and eleventh transistors are turned on, and the output signal is low; the input signal remains high level, the clock signal changes from low level to high level, the first and second transistors are turned on at the same time, and the input signals at points A and B are collected, so that the third and fourth transistors are turned on at the same time, because the thirteenth transistor is input When the signal is turned on, the potential at point C maintains the level of the first negative power supply VSSL, and the output signal maintains a low level state.

As shown in Figure 4, the signal coupling output stage: when the input signal changes from high level to low level, the clock signal also changes from high level to low level, so the first, second and thirteenth transistors are all turned off, Points A and B maintain a high level, the third and fourth transistors remain on, the positive power supply VDD charges point C to a positive power supply level, and at the same time the fifth transistor is turned on, and the capacitor Cp maintains the potential of point C. At this time, the eighth transistor and the tenth transistor are turned on, the seventh transistor is turned on, and the potential of point E is pulled down to the level of the first negative power supply VSSL, so that the ninth and eleventh transistors are turned off, and the positive power supply VDD passes through the eighth and tenth transistors. The transistor charges the output terminal and outputs a high level; when the input signal remains low, the clock signal also changes from low to high, the fifth transistor continues to be turned on, the ninth and eleventh transistors are kept off, and the clock signal is sent to the capacitor Cp The D terminal is charged, and the C point jumps to a higher level, so that the eighth transistor and the tenth transistor have a better conduction state, so that the levels of the output terminals COUT and OUT are equal to the positive power supply level.

As shown in Figure 4, the signal discharge stage: the input signal continues to maintain a low level, the output RESET signal of the next-level unit scan driver is fed back to the signal discharge module of the unit scan driver at this level, and the twelfth and tenth 4. The fifteenth transistor discharges the charge on point B, point C, and point D to the first negative voltage VSSL and the second negative voltage VSS, while the potential of point E rises, and the ninth and eleventh transistors When turned on, the potential of the output terminal COUT is pulled down to the first negative voltage VSSL, and OUT is pulled down to the second negative voltage VSS.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the embodiment, and any other changes, modifications, substitutions and combinations made without departing from the spirit and principle of the present invention , simplification, all should be equivalent replacement methods, and are all included in the protection scope of the present invention.

Claims (4)

1. The scanning driver of active organic electroluminescence display is characterized in that, comprises N level unit scanning driver; Each unit scanning driver comprises an input terminal IN, a clock signal input terminal CLK, a reset terminal RESET, the first output terminal COUT and the second output terminal OUT; the input terminal IN of the first-level unit scanning driver receives the start input signal; the output signal of the first output terminal COUT of the 1st to N-1 level unit scanning driver is used as the next-level unit scanning driver The input signal of the input terminal IN; the output signal of the first output terminal COUT of the second to N-level unit scanning drivers is used as the start signal of the reset terminal RESET of the upper-level unit scanning driver; Each unit scan driver includes: The input sampling module includes first, second, third and fourth transistors; wherein the first and second transistors are turned on when the clock is at a high potential to control the conduction of the third and fourth transistors, thereby sampling the input signal; The signal coupling module includes a fifth transistor and a capacitor Cp, the sampling signal controls the conduction state of the fifth transistor, and the capacitor Cp couples the sampling signal according to the clock signal to control the output signal; The output stage of the circuit includes the sixth, seventh, eighth, ninth, tenth, and eleventh transistors; the sixth and seventh transistors form a NOT gate, which is the inversion of the sampling signal; the eighth, ninth, and The tenth and eleventh transistors form two output terminals, the eighth and tenth transistors are connected to positive power supply, and provide high-level output; the ninth and eleventh transistors are connected to two negative levels, respectively, to provide negative-level output; The circuit charge discharge module includes the twelfth, thirteenth, fourteenth, and fifteenth transistors; the twelfth, thirteenth, fourteenth, and fifteenth transistors form a hold and discharge circuit for the sampling signal , the thirteenth transistor is controlled by the input signal to ensure that when the input signal is high, the output stage is low; the twelfth, fourteenth, and fifteenth transistors are controlled by the output signal of the next-level unit scan driver, and when the next When the output signal of the stage unit scanning driver is high, the twelfth, fourteenth and fifteenth transistors are turned on to discharge the charges. 2. The scan driver of the active organic electroluminescent display according to claim 1, wherein For the first to N-level unit scan drivers: the source of the first transistor is connected to the drain of the second transistor and the gate of the third transistor, the gate of the first transistor is connected to the clock control line, and the drain of the first transistor is connected to the The input signal line of the level unit scanning driver; the gate of the second transistor is connected to the clock control line, the source of the second transistor is connected to the gate of the fourth transistor and the drain of the twelfth transistor; the drain of the third transistor is connected to the positive Power line, the source of the third transistor is connected to the drain of the fourth transistor; the source of the fourth transistor is connected to the drain of the thirteenth and fourteenth transistors, and the drains of the fifth, seventh, eighth and tenth transistors Gate and one end of capacitor Cp; The drain of the fifth transistor is connected to the clock signal, the source of the fifth transistor is connected to the drain of the fifteenth transistor, and the other end of the capacitor Cp; The drain and gate of the sixth transistor are connected to the positive power supply VDD, the source of the sixth transistor is connected to the drain of the seventh transistor and the gates of the ninth and eleventh transistors; the source of the seventh transistor is connected to the first negative power supply VSSL; the drain of the eighth transistor is connected to the positive power supply VDD; the source of the ninth transistor is connected to the first negative power supply VSSL, the drain of the tenth transistor is connected to the positive power supply VDD, and the source of the eleventh transistor is connected to the second negative power supply VSS ; The gate of the twelfth transistor is connected to the RESET signal output by the next-level unit scan driver, the source of the twelfth transistor is connected to the second negative power supply VSS; the gate of the thirteenth transistor is connected to the input signal line of the scan driver of this stage, The source is connected to the first negative power supply VSSL; the source of the fourteenth transistor is connected to the first negative power supply VSSL, and the source of the fifteenth transistor is connected to the second negative power supply VSS; For the first-level unit scan driver: the source of the eighth transistor is connected to the drain of the ninth transistor, and the input terminal of the next-level unit scan driver; the source of the tenth transistor is connected to the drain of the eleventh transistor and the pixel array ; The gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver; For the unit scanning driver of the Nth level: the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the unit scanning driver of the upper level; the source of the tenth transistor is connected to the drain of the eleventh transistor; For the 2nd to N-1 level unit scan drivers; the source of the eighth transistor is connected to the drain of the ninth transistor, and the RESET terminal of the upper unit scan driver, the input terminal of the next unit scan driver; the tenth transistor The source of the eleventh transistor is connected to the drain of the eleventh transistor and the pixel array; the gate of the fourteenth transistor is connected to the RESET signal output by the next-level unit scan driver; the gate of the fifteenth transistor is connected to the output signal of the next-level unit scan driver. RESET signal. 3 . The scanning driver for an active organic electroluminescent display according to claim 1 , wherein the first to fifteenth transistors in the unit scanning driver are N-type transistors. 4. The driving method of the scanning driver of active organic electroluminescence display as claimed in claim 1, is characterized in that, comprises the following steps: The first half cycle of the clock signal is low level, and the second half cycle is high level; the pulse width of the VIN signal is a clock signal of one cycle; In the nth cycle of the clock signal, when the clock signal jumps to a high level, the nth level unit scan driver receives the input signal and starts the input sampling phase; When the clock signal enters the n+1th period, the nth unit scanning driver ends the input sampling phase and performs signal coupling output; at the same time, the n+1th unit scanning driver uses the first output terminal COUT of the nth unit scanning driver The output signal of is the input signal, and the input sampling phase starts when the clock signal enters the second half cycle of the n+1th cycle; In the n+2th cycle of the clock signal, the n+1th unit scan driver finishes the input sampling phase and performs the signal coupling output phase; at the same time, the nth unit scan driver uses the first output of the n+1th unit scan driver The output signal of the terminal COUT is used as the start signal of the reset terminal RESET, and the output signals of the first output terminal COUT and the second output terminal OUT of the nth-level unit scan driver are both set to a negative potential, and the signal discharge phase begins; n=1, 2, . . . , N-1.