CN102968385B - Data writing method, memory controller and storage device - Google Patents

Abstract

The invention relates to a data writing method for a rewritable nonvolatile memory module, and a memory controller and a storage device using the method. The method comprises the steps of extracting a physical unit as a global random area and establishing a global random area searching table to record updating information corresponding to a logic page to which updating data temporarily stored in the global random area belongs. The method also includes receiving update data to be stored to a logic unit; and configuring an index number for the logic unit, writing the update data into the global random area, and recording corresponding update information in the global random area search table by using the index number corresponding to the logic unit. Therefore, the updating information corresponding to the logic page to which the updating data temporarily stored in the global random area belongs can be recorded by using a smaller global random area searching table.

Description

Data writing method, memory controller and storage device

technical field

The invention relates to a data writing method for a rewritable non-volatile memory, a memory controller and a memory storage device using the method.

Background technique

The rapid growth of digital cameras, mobile phones, and MP3 players has led to a rapid increase in consumer demand for storage media. Because rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size, no mechanical structure, fast read and write speed, etc., it is most suitable for portable electronic products, such as notebook type computer. A solid state drive is a memory storage device that uses flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.

The flash memory module has a plurality of physical blocks and each physical block has a plurality of physical pages. When writing data in the physical blocks, the data must be written sequentially according to the order of the physical pages. In addition, the physical pages that have been written with data need to be erased before they can be used to write data again. In particular, a physical block is the smallest unit of erasing, and a physical page is the smallest unit of programming (also known as writing). Therefore, in the management of the flash memory module, the physical block is divided into a data area and an idle area.

The physical blocks of the data area are used to store data stored in the host system. Specifically, the memory management circuit in the memory storage device converts the logical access address accessed by the host system into the logical page of the logical block and maps the logical page of the logical block to the physical page of the physical block of the data area. page. That is to say, the physical blocks in the management data area of the flash memory module are regarded as used physical blocks (for example, the data written by the host system has been stored). For example, the memory management circuit will use the logical-physical address mapping table to record the mapping relationship between the logical block and the physical block of the data area, wherein the logical pages in the logical block are sequentially corresponding to the physical blocks of the mapped physical blocks. page.

The physical blocks in the spare area are used to alternate the physical blocks in the data area. Specifically, as mentioned above, the physical block that has written data must be erased before it can be used to write data again. Therefore, the physical block in the spare area is designed to write update data to replace the mapping The physical block of the logical block. Based on this, the physical blocks in the spare area are empty or usable physical blocks, that is, no recorded data or invalid data marked as useless.

That is to say, the physical pages of the physical blocks in the data area and the free area map the logical pages of the logical blocks in an alternate manner to store data written by the host system. For example, the memory management circuit of the memory storage device will extract one or more physical blocks from the free area as a global random physical block, and when the logical access address of the host system to write update data is a corresponding storage device When a certain logical page of the logical unit is selected, the memory management circuit of the storage device writes the updated data into the physical page of the global random physical block.

In addition, when update data is written into the physical pages of the global random physical block, the memory management circuit must record update information about the updated logical pages in a global random area lookup table. That is to say, it is recorded in the global random area search table that the updated data of the updated logical pages is written into the physical pages of those global random physical blocks. Here, the record used to store the update information of an updated logical page in the global random area search table is called an entry. Each entry contains a field for recording the address of the updated logical page, a field for recording the address of the physical page that stores data belonging to the updated logical page in the global random physical block, and a field for marking whether the entry is valid fields. Since the data of any logical page may be temporarily stored in the global random area, the field used to record the address of the updated logical page in the global random area search table must contain more bits to store enough identification Information about all logical page addresses.

During the operation of the memory storage device, the GRAM table must be loaded into the buffer memory for easy access. However, for a memory storage device configured with a small-capacity buffer memory, the global random area search table cannot be loaded into the buffer memory. Therefore, it is necessary to develop a data writing method so that global random physical blocks can still be used to store data in such a memory storage device configured with a small-capacity buffer memory.

Contents of the invention

The invention provides a data writing method, a memory controller, a memory controller and a memory storage device, which can use global random physical blocks to store data under limited buffer memory capacity.

An exemplary embodiment of the present invention provides a data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical blocks, and each physical block has multiple These physical blocks are at least grouped into a data area and an idle area, and the physical blocks belonging to the data area and the idle area are grouped into multiple physical units, and the physical units in the idle area are used to replace the physical units in the data area to To write data, a plurality of logical units are configured to map physical units of the data area, and each logical unit has a plurality of logical pages. This data writing method includes extracting at least one physical unit from the spare area as a global random area, wherein the global random area temporarily stores data belonging to a plurality of updated logical pages, and these updated logical pages belong to the above logical units Multiple updated logical units. The data writing method also includes establishing a global random area search table to record a plurality of update information corresponding to the updated logical pages in the global random area. The data writing method further includes receiving a write command and update data corresponding to the write command, wherein the update data belongs to the first logical page and the first logical page belongs to the first logical unit. The data writing method also includes judging whether the data belonging to the first logical unit is stored in the global random area; less than a preset number, where the preset number is less than the total number of logical units. The data writing method also includes, when the number of these updated logical units is less than the preset number, configuring a first index number for the first logical unit, writing the updated data into the global random area and using the corresponding first logical unit The first index number of the unit records update information corresponding to the first logical page in the global random area search table.

In an embodiment of the present invention, the above-mentioned data writing method further includes, when the data belonging to the first logic unit is stored in the global random area, writing update data into the global random area and using the corresponding first logical unit The update information corresponding to the first logical page is recorded in the global random area search table with the first index number.

In an embodiment of the present invention, the above data writing method further includes, when the number of the updated logical units is not less than the preset number, extracting the first physical unit from the spare area as the corresponding first logical unit and write update data into the sub-physical unit corresponding to the first logical unit, wherein the sub-physical unit is only used to store data belonging to the first logical unit.

In an embodiment of the present invention, the above-mentioned data writing method further includes: recording the writing times corresponding to each logical unit; and distinguishing the logical units into hot logical areas and cold logical areas according to the writing times of the corresponding logical units .

In an embodiment of the present invention, the above-mentioned data writing method further includes, before judging whether the data belonging to the first logical unit is stored in the global random area, further determining whether the first logical unit belongs to the cold logical area; and only when the second When a logical unit does not belong to the cold logical area, the above step of judging whether the data belonging to the first logical unit is stored in the global random area is executed.

In an embodiment of the present invention, the above-mentioned data writing method further includes, when the first logical unit belongs to the cold logical area, extracting the first physical unit from the physical units in the spare area as the child corresponding to the first logical unit the physical unit and write the update data into the sub-physical unit corresponding to the first logical unit.

An exemplary embodiment of the present invention provides a data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical blocks, and each physical block has multiple These physical blocks are at least grouped into a data area and an idle area, and the physical blocks belonging to the data area and the idle area are grouped into multiple physical units, and the physical units in the idle area are used to replace the physical units in the data area to To write data, a plurality of logical units are configured to map physical units of the data area, and each logical unit has a plurality of logical pages. The data writing method includes extracting at least one physical unit from the idle area as the first global random area and extracting at least one physical unit from the physical units in the idle area as the second global random area, wherein the first global random area is temporarily stored data belonging to a plurality of first updated logical pages, the second global random area temporarily stores data belonging to a plurality of second updated logical pages, the first updated logical page belongs to a plurality of first updated logical units, and the second The updated logical page belongs to a plurality of second updated logical units. The data writing method also includes establishing a first global random area search table to record a plurality of update information corresponding to the first updated logical page in the first global random area and establishing a second global random area search table to record in the second A plurality of update information corresponding to the second updated logical page in the global random area. The data writing method further includes receiving a write command and update data corresponding to the write command, wherein the update data belongs to a first logical page and the first logical page belongs to a first logical unit. The data writing method also includes judging whether the first global random area or the second global random area stores data belonging to the first logic unit; and when neither the first global random area nor the second global random area stores data belonging to the first When the data of the logic unit is obtained, it is judged whether the number of the first updated logic unit is less than a preset number, wherein the preset number is less than the total number of logic units. The data writing method also includes, when the number of the first updated logical unit is less than the preset number, configuring the first index number for the first logical unit, writing the updated data into the first global random area and using the corresponding The first index number of a logical unit records update information corresponding to the first logical page in the first global random area search table. In addition, the data writing method further includes, when the number of the first updated logical units is not less than the preset number, judging whether the number of the second updated logical units is less than the preset number. The data writing method further includes, when the number of the second updated logical unit is less than the preset number, configuring a second index number for the first logical unit, writing the updated data into the second global random area and using the corresponding The second index number of the first logical unit records update information corresponding to the first logical page in the second global random area search table.

An exemplary embodiment of the present invention provides a memory controller for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical blocks, and each physical block has multiple physical pages. The memory controller includes a host interface, a memory interface and a memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used for electrically connecting to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface, and is used to at least group the physical blocks into a data area and an idle area. In addition, the memory management circuit groups the physical blocks belonging to the data area and the spare area into multiple physical units, wherein the physical units in the spare area are used to replace the physical units in the data area to write data. In addition, the memory management circuit configures a plurality of logical units to map physical units of the data area, wherein each logical unit has a plurality of logical pages. The memory management circuit extracts at least one physical unit from the physical units in the spare area as a global random area, wherein the global random area temporarily stores data belonging to a plurality of updated logical pages, and these updated logical pages belong to these logical units Multiple updated logical units of . The memory management circuit establishes a global random area search table to record a plurality of update information corresponding to the updated logical pages in the global random area. The memory management circuit receives a write command and update data corresponding to the write command, wherein the update data belongs to a first logical page and the first logical page belongs to a first logical unit among the logical units. The memory management circuit judges whether the global random area stores data belonging to the first logic unit. When the global random area does not store data belonging to the first logic unit, the memory management circuit also judges whether the number of the updated logic units is less than a preset number, wherein the preset number is less than the total number of logic units. When the number of these updated logical units is less than the preset number, the memory management circuit configures a first index number for the first logical unit, writes the updated data into the global random area and uses the first index corresponding to the first logical unit The number records the update information corresponding to the first logical page in the global random area search table.

In an embodiment of the present invention, when the data belonging to the first logical unit is stored in the global random area, the above-mentioned memory management circuit writes the updated data into the global random area and uses the first index corresponding to the first logical unit The number records the update information corresponding to the first logical page in the global random area search table.

In an embodiment of the present invention, when the number of updated logical units is not less than the preset number, the memory management circuit extracts the first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and The update data is written into the sub-physical unit corresponding to the first logical unit.

In an embodiment of the present invention, the above-mentioned memory management circuit records the writing times corresponding to each logic unit and divides the logic units into hot logic areas and cold logic areas according to the writing times corresponding to the logic units.

In an embodiment of the present invention, the above-mentioned memory management circuit also judges whether the first logic unit belongs to the cold logic area, and only when the first logic unit does not belong to the cold logic area, the memory management circuit judges whether the global random area stores There is data belonging to the first logical unit.

In an embodiment of the present invention, when the first logical unit belongs to the cold logical area, the memory management circuit extracts a first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and updates Data is written into the sub-physical unit corresponding to the first logical unit.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connector, a rewritable non-volatile memory module, and a memory controller. The connector is used to electrically connect to the host system. The rewritable non-volatile memory module has multiple physical blocks and each physical block has multiple physical pages. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module, and is used to at least group these physical blocks into a data area and an idle area. In addition, the memory controller groups the physical blocks belonging to the data area and the free area into multiple physical units, wherein the physical units in the spare area are used to replace the physical units in the data area to write data. In addition, the memory controller configures a plurality of logical units to map physical units of the data area, wherein each logical unit has a plurality of logical pages. The memory controller extracts at least one physical unit from the physical units in the spare area as a global random area, wherein the global random area temporarily stores data belonging to a plurality of updated logical pages, and the updated logical pages belong to the logical units Multiple updated logical units of . The memory controller establishes a global random area search table to record a plurality of update information corresponding to the updated logical pages in the global random area. The memory controller receives a write command and update data corresponding to the write command, wherein the update data belongs to a first logical page and the first logical page belongs to a first logical unit among the logical units. The memory controller determines whether the global random area stores data belonging to the first logic unit. When the global random area does not store data belonging to the first logic unit, the memory controller also judges whether the number of the updated logic units is less than a preset number, wherein the preset number is less than the total number of logic units. When the number of these updated logical units is less than the preset number, the memory controller configures the first index number for the first logical unit, writes the updated data into the global random area and uses the first index corresponding to the first logical unit The number records the update information corresponding to the first logical page in the global random area search table.

In an embodiment of the present invention, when the data belonging to the first logical unit is stored in the global random area, the above-mentioned memory controller writes the update data into the global random area and uses the first index corresponding to the first logical unit The number records the update information corresponding to the first logical page in the global random area search table.

In an embodiment of the present invention, when the number of updated logical units is not less than the preset number, the memory controller extracts the first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and The update data is written into the sub-physical unit corresponding to the first logical unit, wherein the sub-physical unit is only used to store data belonging to the first logical unit.

In an embodiment of the present invention, the above-mentioned memory controller records the writing times corresponding to each logical unit and divides the logical units into hot logical areas and cold logical areas according to the writing times of the corresponding logical units.

In an embodiment of the present invention, the above-mentioned memory controller also judges whether the first logical unit belongs to the cold logical area, and only when the first logical unit does not belong to the cold logical area, the memory controller judges whether the global random area stores There is data belonging to the first logical unit.

In an embodiment of the present invention, when the first logical unit belongs to the cold logical area, the memory controller extracts a first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and updates Data is written into the sub-physical unit corresponding to the first logical unit.

An exemplary embodiment of the present invention provides a data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical blocks, and each physical block has multiple Physical pages, these physical blocks are at least grouped into a data area and an idle area, the physical blocks belonging to the data area and the idle area are grouped into multiple physical units, and the physical units in the idle area are used to replace the physical units in the data area for writing For data, multiple logical units are configured to map the physical units of the data area, and each logical unit has multiple logical pages. This data writing method includes extracting at least one physical unit from the physical units in the spare area as a global random area, wherein the global random area is used to temporarily store data belonging to a plurality of updated logical pages, and these updated logical pages belong to these A number of updated logical units within the logical unit. The data writing method also includes receiving a write command and update data corresponding to the write command, wherein the update data belongs to the first logical page and the first logical page belongs to the first logical unit among the logical units. The data writing method further includes judging whether the global random area stores data belonging to the first logical unit. The data writing method includes: when the global random area stores data belonging to the first logical unit, writing update data into the global random area; and when the global random area does not store data belonging to the first logical unit, judging Whether the number of the updated logical units is less than a preset number, wherein the preset number is less than the total number of logical units. The data writing method further includes: when the number of the updated logical units is less than the preset number, writing the update data into the global random area; and when the number of the updated logical units is not less than the preset number , extracting the first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and writing update data into the sub-physical unit corresponding to the first logical unit, wherein the sub-physical unit is only used for storing Data corresponding to the first logical unit.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connector, a rewritable non-volatile memory module, and a memory controller. The connector is used to electrically connect to the host system. The rewritable non-volatile memory module has multiple physical blocks and each physical block has multiple physical pages. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module, and is used to at least group these physical blocks into a data area and an idle area. In addition, the memory controller groups the physical blocks belonging to the data area and the free area into multiple physical units, wherein the physical units in the spare area are used to replace the physical units in the data area to write data. In addition, the memory controller configures a plurality of logical units to map physical units of the data area, wherein each logical unit has a plurality of logical pages. The memory controller extracts at least one physical unit from the physical units in the spare area as a global random area, wherein the global random area temporarily stores data belonging to a plurality of updated logical pages, and the updated logical pages belong to the logical units Multiple updated logical units. Furthermore, the memory controller receives the write command and the update data corresponding to the write command, wherein the update data belongs to the first logical page and the first logical page belongs to a first logical unit among the logical units. Moreover, the memory controller judges whether the global random area stores data belonging to the first logic unit. When the global random area does not store data belonging to the first logic unit, the memory controller judges whether the number of the updated logic units is less than a preset number, wherein the preset number is less than the total number of logic units. When the number of the updated logical units is less than the preset number, the memory controller writes the updated data into the global random area. In addition, when the data belonging to the first logic unit is stored in the global random area, the memory controller writes update data into the global random area. When the number of these updated logical units is not less than the preset number, the memory controller extracts the first physical unit from the physical units in the spare area as a sub-physical unit corresponding to the first logical unit and writes the update data into Among the sub-physical units corresponding to the first logical unit, the sub-physical units are only used to store data belonging to the first logical unit.

Based on the above, in the data writing method, the memory controller, the memory controller, and the memory storage device of the exemplary embodiments of the present invention, the global random area can only store update data belonging to a predetermined number of logical units at most. The entry in the global random area search table for recording the update information corresponding to the updated logical page can be effectively reduced, so that the global random area search table can be successfully loaded into the buffer memory.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1A is a diagram illustrating a host system and a memory storage device according to a first exemplary embodiment.

FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention.

FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

FIG. 3 is a schematic block diagram of a memory controller according to the first exemplary embodiment.

FIG. 4A and FIG. 4B are exemplary schematic diagrams of managing physical blocks according to the first exemplary embodiment.

5A-5G are simplified examples of writing data using the global random area.

FIG. 6 is a simplified example of the global random region search table shown in FIG. 5G.

7A and 7B are simplified examples of writing data and performing data merging procedures using the global random area.

FIG. 8 is an example of an index number mapping table according to the first exemplary embodiment.

9 to 11 illustrate examples of using sub-physical units to write update data.

12A and 12B are flowcharts of the data writing method according to the first exemplary embodiment.

FIG. 13 is a flow chart of writing update data according to the second exemplary embodiment.

FIG. 14 is an example of configuring the global random zone according to the third exemplary embodiment.

15A and 15B are flowcharts of a data writing method according to a third exemplary embodiment.

[Description of main component labels]

1000: host system 1100: computer

1102: Microprocessor 1104: Random Access Memory

1106: input/output device 1108: system bus

1110: data transmission interface 1202: mouse

1204: keyboard 1206: monitor

1208: Printer 1212: Pen drive

1214: memory card 1216: solid state drive

1310: digital camera 1312: SD card

1314: MMC card 1316: memory stick

1318: CF card 1320: Embedded storage device

100: memory storage device 102: connector

104: memory controller 106: rewritable non-volatile memory module

202: memory management circuit 204: host interface

206: memory interface 252: buffer memory

254: Power management circuit 256: Error checking and correction circuit

410(0)～410(N): physical block 502: system area

504: data area 506: idle area

508: Replacement area 550: Global random area

610(0)～610(K): physical unit 710(0)～710(H): logical unit

800: global random area search table 810 (0) ~ 810 (4): root unit

902: first field 904: second field

906: third field 900: index number mapping table

S1201, S1203, S1211, S1213, S1215, S1217, S1219, S1221: steps of data writing method

S1301, S1303: Steps of the data writing method

550-1: First Global Random Zone

550-2: Second Global Random Area

S1501, S1503, S1511, S1513, S11515, S1517, S1519, S1521, S1523, S1525, S1527: steps of data writing method

detailed description

[First Exemplary Embodiment]

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1A is a diagram illustrating a host system and a memory storage device according to a first exemplary embodiment.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into the memory storage device 100 or read from the memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a pen drive 1212 , a memory card 1214 or a solid state drive (SSD) 1216 as shown in FIG. 1B .

In general, the host system 1000 is any system that can substantially cooperate with the memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is illustrated as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is the SD card 1312, MMC card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded type storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (EmbeddedMMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

Referring to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also be in accordance with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the high-speed peripheral component connection interface (Peripheral Component Interconnect Express , PCIExpress) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, Secure Digital (SecureDigital, SD) interface standard, Memory Stick (MemoryStick, MS) interface standard, MultiMediaCard (MultiMediaCard, MMC) interface standard, small flash ( CompactFlash (CF) interface standard, Integrated Device Electronics (IDE) standard or other suitable standards.

The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000. Fetch and erase operations.

The rewritable non-volatile memory module 106 is electrically connected to the memory controller 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical blocks 410(0)˜410(N). For example, the physical blocks 410(0)˜410(N) may belong to the same memory die or belong to different memory dies. Each physical block has a plurality of physical pages, and each physical page has at least one physical sector, wherein the physical pages belonging to the same physical block can be written independently and erased simultaneously. For example, each physical block is composed of 128 physical pages, and each physical page has 8 physical sectors. That is to say, in an example where each physical sector is 512 bytes (byte), the capacity of each physical page is 4 kilobytes (Kilobyte, K). However, it must be understood that the present invention is not limited thereto, and each physical block may be composed of 64 physical pages, 256 physical pages or any other number of physical pages.

In more detail, a physical block is the smallest unit of erasure. That is, each physical block contains a minimum number of memory cells that are erased together. A physical page is the smallest unit of programming. That is, a physical page is the minimum unit for writing data. However, it must be understood that, in another exemplary embodiment of the present invention, the smallest unit of writing data may also be a physical sector or other sizes. Each physical page generally includes a data bit field and a redundant bit field. The data bit area is used to store user data, and the redundant bit area is used to store system data (eg, error checking and correction code).

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (MultiLevelCell, MLC) NAND flash memory module. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 can also be a Single Level Cell (SLC) NAND flash memory module, other flash memory modules or other memory modules with the same characteristics.

FIG. 3 is a schematic block diagram of a memory controller according to the first exemplary embodiment.

Referring to FIG. 3 , the memory controller 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 202 has a plurality of control commands, and when the memory storage device 100 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has driver code, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to store the control code stored in the rewritable non-volatile memory module 106. The instructions are loaded into random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data. In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be implemented in a hardware form.

The host interface 204 is electrically connected to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with the PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable Data transfer standard.

The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .

In an exemplary embodiment of the present invention, the memory controller 104 further includes a buffer memory 252 , a power management circuit 254 and an error checking and correction circuit 256 . The buffer memory 252 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

The power management circuit 254 is electrically connected to the memory management circuit 202 and used to control the power of the memory storage device 100 .

The error checking and correcting circuit 256 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correction circuit 256 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECCC Code) for the data corresponding to the write command, And the memory management circuit 202 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 256 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

FIG. 4A and FIG. 4B are exemplary schematic diagrams of managing physical blocks according to the first exemplary embodiment.

Referring to FIG. 4A , the memory management circuit 202 of the memory controller 104 logically groups the physical blocks 410 ( 0 )˜410 −(N) into a data area 502 , an idle area 504 , a system area 506 and a replacement area 508 .

The physical blocks logically belonging to the data area 502 and the spare area 504 are used to store data from the host system 1000 . Specifically, the physical blocks in the data area 502 are considered as stored data, and the physical blocks in the spare area 504 are used to replace the physical blocks in the data area 502 . That is to say, when receiving the write command and the data to be written from the host system 1000, the memory management circuit 202 will extract the physical block from the spare area 504, and write the data into the extracted physical block , to replace the physical blocks of the data area 502.

The physical blocks logically belonging to the system area 506 are used to record system data. For example, the system data includes the manufacturer and model of the rewritable nonvolatile memory module, the number of physical blocks of the rewritable nonvolatile memory module, the number of physical pages per physical block, and the like.

Physical blocks that logically belong to the replacement area 508 are used in the bad physical block replacement process to replace damaged physical blocks. Specifically, if there are still normal physical blocks in the replacement area 508 and the physical blocks in the data area 502 are damaged, the memory management circuit 202 will extract normal physical blocks from the replacement area 508 to replace the damaged physical blocks piece.

Please refer to FIG. 4B, the memory management circuit 202 will group the physical blocks 410(0)-410(S-1) of the data area 502 and the spare area 504 into physical units 610(0)-610(K), and Units are used to manage physical blocks. In this exemplary embodiment, each physical unit is composed of one physical block. However, it must be understood that the present invention is not limited thereto. In another exemplary embodiment, each physical unit may also be composed of at least two physical blocks belonging to the same memory sub-module or belonging to different memory sub-modules.

In addition, the memory management circuit 202 configures the logical units 710(0)˜710(H) to map the physical units of the data area 502, wherein each logical unit has a plurality of logical pages to sequentially map the physical pages of the corresponding physical unit . In this exemplary embodiment, each physical unit is composed of one physical block, and each logical page is mapped to one physical page (that is, the capacity of each logical page is the capacity of one physical page). However, in an example where each physical unit is composed of multiple physical blocks, each logical page can also map multiple physical pages (ie, the capacity of each logical page is the capacity of multiple physical pages).

In this exemplary embodiment, the memory management circuit 202 maintains a logical unit-physical unit mapping table to record the mapping relationship between the logical units 710 ( 0 )˜710 (H) and the physical units of the data area 502 . For example, when the host system 1000 intends to access a certain logical access address, the memory management circuit 202 can convert the logical access address accessed by the host system 1000 into a corresponding logical unit, logical page, and logical sector. address, and access data in the physical page of the corresponding physical unit through the logical unit-physical unit mapping table.

In this exemplary embodiment, the memory management circuit 202 extracts physical units from the spare area 504 as a global random area, and writes the data (also called update data) included in the write command from the host system 1000 into In the physical unit of the global random area (also called the global random physical unit). In this exemplary embodiment, the global random physical unit is designed to store data respectively corresponding to different logical units.

Specifically, when the memory storage device 100 receives a write command from the host system 1000, the data in the write command from the host system 1000 can be sequentially written into the physical units of the global random area. And, when the physical unit of the global random area is full, the memory management circuit 202 will extract the physical unit from the idle area 504 as another global random physical unit, so as to continue to write the corresponding write from the host system 1000 Update data for incoming instructions. When the number of the physical units serving as the global random area reaches an upper limit, the memory management circuit 202 will execute the data merging program, so that the data stored in the global random physical units become invalid data, and then the stored data The global random physical units that are all invalid data are associated back to the spare area 504 .

5A-5G are simplified examples of writing data using the global random area.

For the convenience of description, it is assumed that the data area 502 has 5 physical units, the free area 504 has 4 physical units, each physical unit has 3 physical pages, and the data to be written to each physical unit must be in accordance with the physical page to be written in order, and the upper limit value of the number of physical units as a global random physical unit is 3.

Please refer to FIG. 5A, in the initial state of the memory storage device 100, the logical pages of the logical units 710(0)-710(4) can be sequentially mapped to the physical units 610(0)-610(4) of the data area 502. physical pages, and the spare area 504 has physical units 610(5)-610(8). That is to say, the memory management circuit 202 will record the mapping relationship between the logical units 710(0)-710(4) and the physical units 610(0)-610(4) in the logical unit-physical unit mapping table, and will The physical pages of the physical units 610(0)-610(4) are considered to have stored the data belonging to the logical pages of the logical units 710(0)-710(4) (ie, initial data ID1-ID15). It must be understood that, when the memory storage device 100 is just shipped from the factory, the initial data ID1-ID15 may be empty data. In addition, the memory management circuit 202 records the available physical units 610 ( 5 )˜ 610 ( 8 ) in the spare area 504 .

Please refer to FIG. 5B , assuming that the update data UD1 is to be programmed and the update data UD1 belongs to the first logical page of the logical unit 710(0), the memory management circuit 202 will extract the physical unit 610(5) from the spare area 504 as the global The physical unit of the random area 550 and a programming command is issued to write the update data UD1 into the 0th physical page of the physical unit 610(5).

Please refer to FIG. 5C , continuing FIG. 5B , assuming that the update data UD2 is to be reprogrammed and the update data UD2 belongs to the 0th logical page of the logic unit 710 (1), the memory management circuit 202 will issue a program instruction to update the update data UD2 Write to physical page 1 of physical unit 610(5).

Please refer to FIG. 5D , continuing to FIG. 5C , assuming that the update data UD3 is to be reprogrammed and the update data UD3 belongs to the first logical page of the logic unit 710(2), the memory management circuit 202 will issue a program instruction to update the update data UD3 Write to physical page 2 of physical unit 610(5).

Please refer to FIG. 5E , continuing FIG. 5D , assuming that the update data UD4 is to be reprogrammed and the update data UD4 belongs to the 0th logical page of the logical unit 710(3), since the global random physical unit 610(5) has no storage space, Therefore, the memory management circuit 202 will extract the physical unit 610(6) from the spare area 504 as the physical unit of the global random area 550 and issue a programming instruction to write the update data UD4 into the 0th physical unit 610(6) physical page.

Please refer to FIG. 5F , continuing to FIG. 5E , assuming that the update data UD5 is to be reprogrammed and the update data UD5 belongs to the first logical page of the logic unit 710 (3), the memory management circuit 202 will issue a program instruction to update the update data UD5 Write to physical page 1 of physical unit 610(6).

Please refer to FIG. 5G , continuing FIG. 5F , assuming that the update data UD6 is to be reprogrammed and the update data UD6 belongs to the second logical page of the logic unit 710 (0), the memory management circuit 202 will issue a program instruction to update the update data UD6 Write to physical page 2 of physical unit 610(6).

In order to be able to identify that the data stored in the physical unit of the global random area belongs to that logical page (also called updated logical page) of that logical unit (also called updated logical unit), in this exemplary embodiment, the memory The management circuit 202 will establish a global random area search table to facilitate the search of valid data. Here, the logical page to which the updated data temporarily stored in the global random area belongs is called an updated logical page and the logical unit block to which the updated logical page belongs is called an updated logical unit. In the global random area search table, the memory management circuit 202 will create multiple root units and configure a login link for each root unit. In particular, the memory management circuit 202 groups the logical pages of the logical units to respectively correspond to one of the root units, and records the update information of the updated logical pages on the login link of the corresponding root unit. Based on this, when it is desired to search for update data of a specific logical unit in the global random physical unit, it is only necessary to search for the login link of the corresponding root unit.

For example, in this exemplary embodiment, the memory management circuit 202 maps the logical pages of each logical unit to the same root unit. That is, the logical pages of the same logical unit correspond to the same root unit. It must be understood that the present invention is not limited thereto. For example, in another exemplary implementation of the present invention, a part of logical pages of a logical unit may also be grouped into a root unit and another part of logical pages of this logical unit may be grouped to another unit.

In addition, the memory management circuit 202 will configure a login link for each root unit and whenever a write command is executed, the memory management circuit 202 will create a login on the corresponding login link to record the update information about the write command . For example, each entry includes a first field (for example, field 902 in FIG. 6 ), a second field (for example, field 904 in FIG. 6 ) and a third field (for example, field 906 in FIG. 6 ), wherein the first field records The address of the updated logical page, the second field is used to record the physical address for storing the updated data of the updated logical page, and the third field is used to mark whether the registration is valid. Here, if the registration is valid, the third field will be marked as '1'; and if the registration is invalid, the third field will be marked as '0', for example. It must be understood that the method of marking valid logins and invalid logins is not limited to this. For example, it is also possible to use '1' to represent an invalid login and '0' to represent a valid login.

FIG. 6 is a simplified example of the global random region search table shown in FIG. 5G.

Please refer to FIG. 6, the global random area search table 800 includes root units 810(0)-810(4), wherein the logical page of the logical unit 710(0) corresponds to the root unit 810(0), and the logical page of the logical unit 710(1) The logical page is for root unit 810(1), the logical page for logical unit 710(2) is for root unit 810(2), the logical page for logical unit 710(3) is for root unit 810(3), and logical unit 710(2) is for root unit 810(3). The logical page of 710(4) is the corresponding root unit 810(4).

Include 2 valid logins in the login link of root unit 810(0) to record the 1st logical page (ie, information "710(0)-1") and the 2nd logical page of logical unit 710(0) (i.e., information "710(0)-2") has been updated, wherein the updated data of logical page 1 of logical unit 710(0) is written to physical page 0 of physical unit 610(5) ( That is, the updated data in the information "610(5)-0") and the second logical page of the logical unit 710(0) is written to the second physical page of the physical unit 610(6) (ie, the information " 610(6)-2″).

Include 1 valid login in the login link of root unit 810(1) to record that logical page 0 of logical unit 710(1) (i.e., information "710(1)-0") has been updated, where logical The update data of the 0th logical page of unit 710(1) is written into the 1st physical page of physical unit 610(5) (ie, information "610(5)-1").

Include 1 valid login in the login link of root unit 810(2) to record that the 1st logical page of logical unit 710(2) (i.e., information "710(2)-1") has been updated, where logical The update data of the 1st logical page of unit 710(2) is written into the 2nd physical page of physical unit 610(5) (ie, information "610(5)-2").

Include 2 valid entries in the entry link of the root unit 810(3) to record the 0th logical page (i.e., information "710(3)-0") and the 1st logical page of the logical unit 710(3) (i.e., information "710(3)-1") has been updated, wherein the updated data of the 0th logical page of logical unit 710(3) is written to the 0th physical page of physical unit 610(6) ( That is, the updated data in the information "610(6)-0") and the first logical page of the logical unit 710(3) is written to the first physical page of the physical unit 610(6) (ie, the information " 610(6)-1″).

In addition, one empty entry is included in the entry links of the root units 810 ( 0 ) to 810 ( 4 ), indicating the end of the entry links. For example, if it is desired to search for data belonging to the logical unit 710(4) in the global random physical unit, the memory management unit 202 can identify the global random physical unit according to the entry link of the root unit 810(4) with only empty entries No data belonging to the logical unit 710(4) is stored in the logical unit 710(4), so the data can be directly read from the physical page of the corresponding physical unit according to the information in the logical unit-physical unit mapping table.

By analogy, the memory management circuit 202 will sequentially write the data to be stored by the host system 1000 into the physical unit serving as the global random area. In particular, when the number of physical units in the global random area reaches 3, the memory management circuit 202 will execute the data consolidation process when executing the write command, so as to prevent the physical units in the free area from being used up.

7A and 7B are simplified examples of writing data and performing data merging procedures using the global random area.

Please refer to FIG. 7A , continuing FIG. 5G , assuming that the update data UD7 is to be reprogrammed and the update data UD7 belongs to the 0th logical page of the logical unit 710(2), since the global random physical unit 610(6) has no storage space, Therefore, the memory management circuit 202 will extract the physical unit 610(7) from the spare area 504 as a physical unit of the global random area 550 and issue a programming instruction to write the update data UD7 into the 0th physical unit 610(7) physical page. In particular, since the number of physical units serving as the global random area 550 has reached 3, the memory management circuit 202 executes the data consolidation procedure after executing the writing operation shown in FIG. 7B . That is to say, in this example, during the execution of the write command, the memory management circuit 202 will also execute the data merging procedure.

Please refer to FIG. 7B , assuming that the memory management circuit 202 selects the logical unit 710(0) for data merging, the memory management circuit 202 will recognize that the logical unit 710(0) is a mapped physical unit 610(0), and extract the physical unit 610(0) from the spare area 504. Unit 610(8), and copy valid data belonging to logical unit 710(0) in physical unit 610(0) and global random area 550 to physical unit 610(8). Specifically, the memory management circuit 202 will sequentially write the data ID1 in the physical unit 610(0), the data UD1 in the physical unit 610(5) and the data UD6 in the physical unit 610(6) to the physical unit 610 (8) in the 0th to 2nd physical pages, and mark the first physical page of the physical unit 610(5) and the second physical page of the physical unit 610(6) as invalid (as shown by the slash) . Afterwards, the memory management circuit 202 performs an erase operation on the physical unit 610(0), remaps the logical unit 710(0) to the physical unit 610(8) in the logical unit-physical unit mapping table, and transfers the physical unit 610 (0) is associated to the spare area 504 .

For example, when executing the next write instruction, the memory management circuit 202 will execute the data consolidation program on the logic unit 710(1), and then when executing the next write instruction, the memory management circuit 202 will execute the data consolidation program on the logic unit 710(2). ) to execute the data merging procedure. Therefore, when the storage space of the physical unit 610(7) is full, all the data in the physical unit 610(5) will become invalid data. Based on this, the memory management circuit 202 can perform an erase operation on the physical unit 610 ( 5 ) and associate the erased physical unit 610 ( 5 ) back to the spare area 504 .

Or, for example, when executing the next write command, the memory management circuit 202 will perform a data consolidation procedure on the logic unit 710(3). Therefore, before the storage space of the physical unit 610(7) is filled, the data in the physical unit 610(6) will become invalid data. Based on this, the memory management circuit 202 can perform an erase operation on the physical unit 610 ( 6 ) and associate the erased physical unit 610 ( 6 ) back to the spare area 504 .

Therefore, according to the above operations, the memory management circuit 202 can continuously associate the physical units storing invalid data back to the spare area 504 and extract empty physical units from the spare area 504 as global random physical units.

It is worth mentioning that, in this exemplary embodiment, the number of logical units to which the update data temporarily stored in the global random area 550 belongs is limited to not more than a preset number. That is to say, at the same time, the memory management circuit 202 only temporarily stores the update data of some logic units in the global random area 550 , and the number of this part of logic units is not greater than the preset number. That is to say, the preset number is set to be smaller than the total number of logical units.

Specifically, as mentioned above, in the global random area search table, the address of the updated logical page is identified by the information recorded in the first field. Therefore, in the global random area lookup table used in the prior art, the size of the first field must be sufficient to record information capable of distinguishing all logical pages. For example, if the number of logical units is 1024, the first field in the global random area search table used in the known technology must be configured with 10 bits to be able to distinguish the information of all logical pages.

In this exemplary embodiment, the size of the first field 902 is designed to be small and cannot record information capable of distinguishing all logical pages. For example, the size of the first field 902 is 7 bits, and can only record information (ie, index numbers) for distinguishing logical page addresses of 128 logical units. Therefore, the aforementioned preset number is set to 128 and the memory management circuit 202 only temporarily stores update data belonging to 128 logical units in the global random area 550 at most. Based on this, the size of the global random area search table 800 can be effectively reduced, so as to be loaded into the buffer memory 252 with a smaller capacity.

When the update data of the logical page belonging to a logical unit is written into the global random area 550, the memory management circuit 202 will assign an index number to the logical unit and record the logical page in the global random area search table 800 according to the index number Update information. For example, in this exemplary embodiment, the range of index numbers is '0'˜127' and the memory management circuit 202 configures an index number mapping table to record the index number currently assigned to each updated logical unit. That is to say, each update logic unit will be configured with one of the index numbers (ie, '0'～'127') and the index number will be recorded in the first field of the global random area search table 800 to replace the original record in The part of the first field about the logical unit to which the logical page belongs.

FIG. 8 is an example of an index number mapping table according to the first exemplary embodiment.

Please refer to FIG. 8 , assuming that the update data of the 0th logical page belonging to the logical unit 710 (0) is written into the global random area 550, the memory management circuit 202 will map the unused index numbers in the index number mapping table 900 '0' is assigned to logical unit 710(0).

In addition, after the data merging procedure (as shown in FIG. 7B ), if the global random area 550 does not store any updated data belonging to the logical unit 710(0), the index number '0' assigned to the logical unit 710(0) will be cancelled. Based on this, during subsequent write operations, the index number '0' can be assigned to other updating logical units.

That is to say, when the host system 1000 intends to store data in a certain logical page of a certain logical unit, the memory management circuit 202 will determine whether the global random area 550 has stored data belonging to the logical unit. For example, the memory management circuit 202 will judge whether the logical unit has been assigned an index number according to the index number mapping table, wherein when the logical unit has been assigned an index number, it means that the global random area 550 has already stored the data. When the global random area 550 has already stored the data belonging to this logical unit, the memory management circuit 202 will write the update data belonging to this logical page into the global random area 550 and use the index number assigned to this logical unit to write in the global random area The update data corresponding to this logical page is recorded in the search table.

When the global random area 550 does not store data belonging to the logical unit, the memory management circuit 202 determines whether the number of logical units to which the updated data temporarily stored in the global random area 550 belongs is less than a preset number. For example, the memory management circuit 202 will determine whether there are unassigned index numbers in the index number mapping table, wherein when there are unassigned index numbers in the index number mapping table, it means the update data temporarily stored in the global random area 550 The number of logical units it belongs to is less than the preset number.

If the number of logical units to which the update data temporarily stored in the global random area 550 belongs is less than the preset number, the memory management circuit 202 will assign an unused index number to this logical unit, and write the update data belonging to this logical page Enter the global random area 550 and use the index number assigned to this logical unit to record the update data corresponding to this logical page in the global random area lookup table.

If the number of logical units to which the update data temporarily stored in the global random area 550 belongs is not less than the preset number (that is, there is no empty index number that can be assigned to the logical unit to be written), the memory management circuit 202 will start from idle One physical unit is extracted from area 504 as a sub-physical unit to write update data.

9 to 11 illustrate examples of using sub-physical units to write update data.

Please refer to FIGS. 9 to 11 at the same time. For example, in the mapping state where the logical unit 710(0) is mapped to the physical unit 610(0), when the memory controller 104 receives a write command from the host system 1000 and wants to write When inputting data to the logical page belonging to the logical unit 710(0), the memory management circuit 202 identifies that the logical unit 710(0) is currently mapped to the physical unit 610(0) according to the logical unit-physical unit mapping table. Physical unit 610(H+1) is fetched to replace physical unit 610(0). However, when new data is written into the physical unit 610(H+1), the memory management circuit 202 can erase all the valid data in the physical unit 610(0) to the physical unit 610(H+1) immediately. Except physical unit 610(0). Specifically, the memory management circuit 202 will read from the physical unit 610(0) the valid data before the physical page to be written (that is, the data in the 0th physical page and the 1st physical page of the physical unit 610(0) ). Afterwards, the memory controller 104 will write the valid data before the physical page in the physical unit 610(0) into the 0th physical page and the 1st physical page of the physical unit 610(H+1) (as shown in FIG. 9 ), and write new data into the second to fourth physical pages of the physical unit 610 (H+1) (as shown in FIG. 10 ). At this point, the memory controller 104 completes the writing operation. Because the valid data in the physical unit 610(0) may become invalid in the next operation (for example, a write command), the valid data in the physical unit 610(0) is immediately moved to the physical unit 610(H+1 ) may cause unnecessary movement. In addition, data must be sequentially written to the physical pages in the physical unit. Therefore, the memory management circuit 202 can first move the valid data before the physical page to be written (that is, the 0th physical page stored in the physical unit 610(0) page and the data in the 0th physical page), and the remaining valid data (that is, the data stored in the 5th-K physical pages of the physical unit 610(0)) is not moved temporarily.

In this exemplary embodiment, the operation of temporarily maintaining these instantaneous relationships is called opening (opening) the parent-child block, and the original physical unit (for example, the above-mentioned physical unit 610(0)) is called the parent physical unit to replace A physical unit of a parent physical unit (for example, the aforementioned AND physical unit 610(H+1)) is called a child physical unit.

Afterwards, when the data of the physical unit 610(0) and the physical unit 610(H+1) need to be merged (merge), the memory controller 104 will merge the data of the physical unit 610(0) and the physical unit 610(H+1) The data is consolidated into one physical unit, thereby improving the efficiency of using the physical unit. Here, the operation of merging the parent and child blocks is called a data merging process or closing the parent and child blocks. For example, as shown in FIG. 11, when closing the parent-child block, the memory management circuit 202 will read the remaining valid data from the physical unit 610(0) (that is, the 5th to K physical units of the physical unit 610(0) page), write the remaining valid data in the physical unit 610(0) into the fifth physical page to the Kth physical page of the physical unit 610(H+1), and execute the erase operation on the physical unit 610(0). In the erase operation, the erased physical unit 610 ( 0 ) is associated to the spare area 504 and the physical unit 610 (H+1) is associated to the data area 502 . That is, the memory controller 104 remaps the logical unit 710(0) to the physical unit 610(H+1) in the logical unit-physical unit mapping table. It is worth mentioning that the number of physical units in the spare area 504 is limited, and therefore, the number of opened parent and child block groups will also be limited during the operation of the memory storage device 100 . Therefore, when the memory storage device 100 receives a write command from the host system 1000, if the number of opened parent and child block groups reaches the upper limit, the memory controller 104 needs to close at least one set of currently opened parent and child block groups. The write command can only be executed after that.

It is worth mentioning that although in this exemplary embodiment, when the number of logical units to which the update data temporarily stored in the global random area 550 belongs is not less than the preset number, the memory management circuit 202 uses sub-physical units to write update data. But the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory management circuit 202 may also execute the data merging program as shown in FIG. Area 504 extracts the physical unit and remaps this logical unit to this physical unit, thereby making the number of logical units to which the update data temporarily stored in the global random area 550 belongs is less than the preset number and writing new update data to in the global random area 550 .

12A and FIG. 12B are flowcharts of the data writing method according to the first exemplary embodiment, wherein FIG. 12A shows the steps of setting the global random area 550 and the global random area search table and FIG. Enter the steps to update the data.

Referring to FIG. 12A , in step S1201 , at least one physical unit is extracted from the physical units in the spare area 504 as the global random area 550 . Here, the global random area 550 can temporarily store data of a plurality of updated logical pages belonging to a plurality of updated logical units.

In step S1203, a global random area search table is established to record update information corresponding to the updated logical page in the global random area. In particular, the number of logical units to which the global random area can be allocated is less than the number of logical units possessed by the device. In addition, the information about the logical unit to which the updated logical page belongs in the global random area lookup table can be assigned by index number to record. For example, in step S1203, an index number mapping table is established to record the mapping relationship between the updated logical unit and the index number.

12B, when the host system 1000 issues a write command to write update data to the logical page (hereinafter referred to as the first logical page of the first logical unit), in step S1211, the write command and the corresponding write command The update data of will be received, and in step S1213, the global random area 550 will be judged whether the data belonging to the first logical unit is stored.

If the global random area 550 does not store data belonging to the first logical unit, then in step S1215, whether the number of updated logical units to which the update data temporarily stored in the global random area 550 belongs is judged to be less than a preset number, Wherein the preset number is less than the total number of logical units of the device.

If the number of updated logical units is less than the preset number, in step S1217, an unused index number (hereinafter referred to as the first index number) is allocated to the first logical unit. And, after that, in step S1219, the update data will be written into the global random area 550 and the update information corresponding to the first logical page will be recorded in the global random area by using the first index number corresponding to the first logical unit in the search form.

If the number of updated logical units is not less than the preset number, in step S1221, a physical unit (hereinafter referred to as the first physical unit) will be extracted from the physical units in the spare area as a child corresponding to the first logical unit The physical unit and update data will be written into the sub-physical unit corresponding to the first logical unit.

If the data belonging to the first logic unit is stored in the global random area 550, step S1219 will be executed.

[Second Exemplary Embodiment]

The difference between the second exemplary embodiment and the first exemplary embodiment is that, in addition to the block management step and the data writing step described in the first exemplary embodiment, in the second exemplary embodiment, when a write command is received When updating data, the logical unit to which the updated data belongs is also judged whether it is a frequently written area, and only the updated data belonging to the frequently written area will be written into the global random area. The hardware architecture of the memory controller and the memory storage device of the second exemplary embodiment is essentially the same as that of the first exemplary embodiment, and the second exemplary embodiment will be described below using the hardware architecture of the first exemplary embodiment.

In the second exemplary embodiment, the memory management circuit 202 of the memory controller 104 records the write times corresponding to each logical unit. For example, whenever the host system stores data into a logical unit, the write count corresponding to this logical unit will be incremented by 1. In addition, the memory management circuit 202 divides the logical units into hot logical areas that are more frequently used and cold logical areas that are less used according to the write times. For example, in this exemplary embodiment, the memory management circuit 202 sorts the logical units from the largest to the smallest according to the number of writes, and the top 80% of the logical units are grouped into the hot logical area and other logical units are grouped into the cold logical area. Distinguishing the hot logical area and the cold logical area according to the writing times is just an example, and the invention is not limited thereto.

In this exemplary embodiment, when the host system 1000 intends to store data in a certain logical page of a certain logical unit, the memory management circuit 202 will determine whether the logical unit belongs to the cold logical area.

If the logical unit belongs to the cold logical area, the memory management circuit 202 uses the sub-physical unit to write the updated data. Moreover, if the logic unit does not belong to the cold logic area, the memory management circuit 202 will decide whether to write the update data into the global random area 550 according to the storage state of the global random area 550 . That is to say, only when the logical unit to which the updated data belongs belongs to the hot logical area, the memory management circuit 202 will judge whether the global random area 550 stores data belonging to the logical unit and whether the updated data temporarily stored in the global random area 550 belongs to Whether the number of logical units is less than the preset number and whether to write the update data into the global random area 550 is determined according to the judgment (as described in the first exemplary embodiment).

FIG. 13 is a flow chart of writing update data according to the second exemplary embodiment.

Referring to FIG. 13, when the host system 1000 issues a write command to write update data to a logical page (hereinafter referred to as the first logical page of the first logical unit), in step S1211, the write command and the corresponding write command The update data of will be received, and in step S1301, the logical unit will be divided into a hot logical area and a cold logical area according to the write times and the first logical unit will be judged whether it belongs to the cold logical area.

If the first logical unit does not belong to the cold logical area, in step S1213, the global random area 550 will be judged whether there is stored data belonging to the first logical unit.

If the global random area 550 does not store data belonging to the first logical unit, in step S1215, it is determined whether the number of updated logical units to which the updated data temporarily stored in the global random area 550 belongs is less than a preset number.

If the number of updated logical units is less than the preset number, in step S1217, an unused index number (hereinafter referred to as the first index number) is allocated to the first logical unit. And then, in step S1219, the update data will be written into the global random area 550 and the update information corresponding to the first logical page will be recorded in the global random area by using the first index number corresponding to the first logical unit. table.

If the number of updated logical units is not less than the preset number, in step S1221, a physical unit (hereinafter referred to as the first physical unit) will be extracted from the physical units in the spare area as a child corresponding to the first logical unit The physical unit and update data will be written into the sub-physical unit corresponding to the first logical unit.

In addition, if the data belonging to the first logic unit is stored in the global random area 550, step S1219 will be executed.

In addition, if the first logical unit belongs to the cold logical zone, step S1221 will be executed.

Afterwards, after step S1219 and step S1221, in step S1303, the writing times corresponding to the first logical unit are updated.

[Third Exemplary Embodiment]

The difference between the third exemplary embodiment and the first exemplary embodiment is that, in addition to the block management step and the data writing step described in the first exemplary embodiment, in the third exemplary embodiment, the physical unit of the global random area are at least divided into two groups (ie, the first global random area and the second global random area) and at most the first global random area and the second global random area can be respectively written with update data belonging to a predetermined number of logical units. That is to say, in the second exemplary embodiment, two global random area search tables as described in the first exemplary embodiment will be used to record the update information corresponding to the first global random area and the update information corresponding to the second global random area. Update information. The hardware architecture of the memory controller and the memory storage device of the third exemplary embodiment is essentially the same as that of the first exemplary embodiment, and the third exemplary embodiment will be described below using the hardware architecture of the first exemplary embodiment.

FIG. 14 is an example of configuring the global random zone according to the third exemplary embodiment.

Referring to FIG. 14 , the memory management circuit 202 of the memory controller 104 extracts physical units from the spare area 504 as a first global random area 550 - 1 and a second global random area 550 - 2 . In addition, the memory management circuit 202 configures a first global random area search table and a second global random area search table for the first global random area 550 - 1 and the second global random area 550 - 2 respectively. Here, the data structure and size of the first global random area search table and the first global random area search table are the same as the global random area search table 800 in the first exemplary embodiment.

In this exemplary embodiment, the memory management circuit 202 uses the first global random area 550-1 and the second global random area 550-2 to respectively store update data belonging to different logical units, wherein the first global random area is temporarily stored The number of logic units to which the update data of 550-1 belongs will not exceed a preset number and the number of logic units to which update data temporarily stored in the second global random area 550-2 will not exceed a preset number. For example, in the case where the preset number is set to 128, the first global random area 550-1 stores update data belonging to 128 logical units at most and the second global random area 550-2 stores update data belonging to 128 logical units at most .

Specifically, when the host system 1000 intends to store data in a certain logical page of a certain logical unit, the memory management circuit 202 will determine whether the first global random area 550-1 or the second global random area 550-2 has already stored The data belonging to this logical unit.

When the first global random area 550-1 stores data belonging to the logic unit, the memory management circuit 202 will write the updated data into the first global random area 550-1 and The update information corresponding to this logical page is recorded in the first global random area search table.

When the second global random area 550-2 stores data belonging to the logic unit, the memory management circuit 202 will write the update data into the second global random area 550-2 and The update information corresponding to the logical page is recorded in the second global random area search table.

When the first global random area 550-1 and the second global random area 550-2 do not store any data belonging to the logical unit, the memory management circuit 202 will determine which update data temporarily stored in the first global random area 550-1 belongs to. Whether the number of logical units is less than a preset number.

If the number of logic units to which the update data temporarily stored in the first global random area 550-1 belongs is less than the preset number, the memory management circuit 202 will assign unused index numbers in the first global random area search table to the logical units. Write the updated data belonging to the logical page into the first global random area 550 and record the updated data corresponding to the logical page in the first global random area lookup table using the index number assigned to the logical unit.

If the number of logical units to which the updated data temporarily stored in the first global random area 550-1 belongs is not less than the preset number, the memory management circuit 202 will determine which logical unit the updated data temporarily stored in the second global random area 550-2 belongs to. Whether the number of logical units is less than a preset number.

If the number of logic units to which the update data temporarily stored in the second global random area 550-2 belongs is less than the preset number, the memory management circuit 202 will assign an unused index number in the second global random area search table to the logic unit. Write the updated data belonging to the logical page into the second global random area 550-2 and use the index number assigned to the logical unit to record the updated data corresponding to the logical page in the second global random area search table.

If the number of logical units to which the update data temporarily stored in the second global random area 550-2 belongs is not less than the preset number, the memory management circuit 202 will extract a physical unit from the idle area 504 as a sub-physical unit to write the update data.

15A and 15B are flowcharts of the data writing method according to the third exemplary embodiment, wherein FIG. 15A shows the steps of setting the global random area and the global random area search table and FIG. 15B shows the steps of writing Steps to update data.

Please refer to FIG. 15A, in step S1501, at least one physical unit will be extracted from the physical units in the idle area 504 as the first global random area 550-1 and at least one physical unit will be extracted from the physical units in the idle area 504 is extracted as the second global random area 550-2. Here, the first global random area 550-1 temporarily stores a plurality of updated logical pages (hereinafter referred to as first updated logical pages) belonging to a plurality of updated logical units (hereinafter referred to as first updated logical units). and the second global random area 550-2 temporarily stores multiple updated logical pages (hereinafter referred to as second updated logical pages) belonging to multiple updated logical units (hereinafter referred to as second updated logical units) The data.

In step S1503, the first global random area search table and the second global random area search table are respectively established, wherein the first global random area search table records the data corresponding to the first updated logical page in the first global random area The information is updated and the second global random area search table records the updated information corresponding to the second updated logical page in the second global random area. In particular, the information about the logical unit to which the updated logical page belongs is recorded by the assigned index number in the first global random area search table and the second global random area search table.

Please refer to FIG. 15B, when the host system 1000 issues a write command to write update data to the logical page (hereinafter referred to as the first logical page of the first logical unit), in step S1511, the write command and the corresponding write command The update data of will be received, and in step S1513, the first global random area 550-1 will be judged whether there is stored data belonging to the first logical unit.

If the first global random area 550-1 does not store data belonging to the first logical unit, then in step S1515, the second global random area 550-1 will be judged whether to store data belonging to the first logical unit.

If the second global random area 550-2 does not store data belonging to the first logical unit, in step S1517, the number of updated logical units to which the update data temporarily stored in the first global random area 550-1 belongs will be replaced by Determine whether it is less than the preset number.

If the number of updated logical units to which the update data temporarily stored in the first global random area 550-1 belongs is less than the preset number, in step S1519, unused index numbers in the first global random area search table (hereinafter referred to as the first index number) will be assigned to the first logical unit. And, after that, in step S1521, the update data will be written into the first global random area 550-1 and the update information corresponding to the first logical page will be recorded by using the first index number corresponding to the first logical unit in the first global index mapping table.

If the number of updated logical units to which the update data temporarily stored in the first global random area 550-1 belongs is not less than the preset number, in step S1523, the update data temporarily stored in the second global random area 550-2 belongs to It is determined whether the number of updated logical units of is less than a preset number.

If the number of updated logical units to which the update data temporarily stored in the second global random area 550-2 belongs is less than the preset number, in step S1525, unused index numbers in the second global random area search table (hereinafter referred to as the second index number) will be assigned to the first logical unit. And, after that, in step S1527, the update data will be written into the second global random area 550-2 and the update information corresponding to the first logical page will be recorded by using the second index number corresponding to the first logical unit In the second global random area search table.

If the number of updated logical units to which the updated data temporarily stored in the second global random area 550-2 belongs is not less than the preset number, in step S1529, a physical unit (hereinafter referred to as the first physical unit) will be removed from idle The physical units of the zone are extracted as sub-physical units corresponding to the first logical unit and the update data is written into the sub-physical units corresponding to the first logical unit.

In addition, if it is determined in step S1513 that the first global random area 550-1 stores data belonging to the first logic unit, then step S1521 will be directly executed. Moreover, if it is determined in step S1515 that the second global random area 550-2 stores data belonging to the first logic unit, then step S1527 will be executed.

It is worth mentioning that although in the third exemplary embodiment, two global random areas are configured for illustration, the present invention is not limited thereto, and the number of global random areas may exceed two.

To sum up, according to an exemplary embodiment of the present invention, the data writing method, the memory controller and the memory storage device will determine the logic unit to which the update data temporarily stored in the global random area belongs before writing the update data into the global random area. Whether the number is less than the preset number, and only when the number of logical units to which the update data temporarily stored in the global random area belongs is less than the preset number, the update data is temporarily stored in the global random area. Therefore, the global random table only needs to record update information of a preset number of logical units and the size of the global random table can be effectively reduced. Based on this, the memory storage device configured with a small-capacity buffer memory can also use the global random physical unit to store data and effectively increase the writing speed of the memory storage device configured with a small-capacity buffer memory. In addition, according to the data writing method, memory controller and memory storage device according to another exemplary embodiment of the present invention, logical units are divided into hot logical areas and cold logical areas, and only update data belonging to the hot logical areas are temporarily stored In the global random area, the global random area which can only temporarily store update data of a limited number of logical units can also be effectively used. In addition, according to the data writing method, memory controller, and memory storage device of another exemplary embodiment of the present invention, multiple global random areas are configured to temporarily store update data of different logical units, thereby enabling more The update data of the logic unit can be temporarily stored in the global random area, so as to further improve the writing speed of the memory storage device configured with a small-capacity buffer memory.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (20)

1. a method for writing data, for a reproducible nonvolatile memorizer module, wherein reproducible nonvolatile memorizer module has multiple physical blocks, each the plurality of physical blocks has multiple physical page, the plurality of physical blocks is at least grouped into a data field and an idle district, those physical blocks belonging to this data field and this idle district are grouped into multiple physical location, those physical locations in this idle district are in order to replace those physical locations of this data field to write data, multiple logical block is configured to those physical locations mapping this data field, and each those logical block has multiple logical page (LPAGE), this method for writing data comprises:

At least one physical location is extracted as a random district of the overall situation from those physical locations in this idle district, wherein the random district of this overall situation is in order to the temporary data belonging to multiple more new logical page, and the plurality of more new logical page to belong among those logical blocks multiple upgrades logical block;

Set up the random district's search table of an overall situation to be recorded in multiple lastest imformations of those more new logical page of correspondence in the random district of this overall situation;

Receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among those logical blocks;

Judge whether the random district of this overall situation stores the data belonging to this first logical block;

When the random district of this overall situation does not store the data belonging to this first logical block, judge whether those numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of those logical blocks; And

When the number that those have upgraded logical block is less than this preset number, for this first logical block configuration one first index number, by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

2. method for writing data according to claim 1, also comprises:

When the random district of this overall situation stores the data belonging to this first logical block, by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

3. method for writing data according to claim 1, also comprises:

When those have upgraded that the number of logical block is non-is less than this preset number, extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block, wherein this muon physics unit is only in order to store the data belonging to this first logical block.

4. method for writing data according to claim 1, also comprises:

One write number of times of record each those logical block corresponding; And

Those logical blocks are divided into a hot logic area and a cold logic area by those write number of times according to those logical blocks corresponding.

5. method for writing data according to claim 4, also comprises:

Judging the random district of this overall situation also judges whether this first logical block belongs to this cold logic area before whether storing the data belonging to this first logical block; And

Only when this first logical block is non-belong to this cold logic area time, just perform the above-mentioned the step whether random district of this overall situation stores the data belonging to this first logical block that judges.

6. method for writing data according to claim 5, also comprises:

When this first logical block belongs to this cold logic area, extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block.

7. a method for writing data, for a reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple physical blocks, each the plurality of physical blocks has multiple physical page, the plurality of physical blocks is at least grouped into a data field and an idle district, those physical blocks belonging to this data field and this idle district are grouped into multiple physical location, those physical locations in this idle district are in order to replace those physical locations of this data field to write data, multiple logical block is configured to those physical locations mapping this data field, and each those logical block has multiple logical page (LPAGE), this method for writing data comprises:

At least one physical location is extracted to extract at least one physical location using as the one second random district of the overall situation from those physical locations in this idle district as the one first random district of the overall situation from those physical locations in this idle district, wherein this random district of first overall situation keeps in the data belonging to the multiple first more new logical page, this random district of second overall situation keeps in the data belonging to the multiple second more new logical page, those first more new logical page belong to multiple first and upgrade logical block, and those second more new logical page belong to multiple second and upgrade logical block,

Set up the random district's search table of one first overall situation be recorded in this random district of first overall situation corresponding those first more new logical page multiple lastest imformation and set up the random district's search table of one second overall situation to be recorded in multiple lastest imformations of those the second more new logical page corresponding in this random district of second overall situation;

Receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block in those logical blocks;

Judge whether this random district of first overall situation or this random district of second overall situation store the data belonging to this first logical block;

When this random district of first overall situation and this random district of second overall situation all do not store the data belonging to this first logical block, judge whether those first numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of those logical blocks;

When those first numbers having upgraded logical block are less than this preset number, for this first logical block configuration one first index number, by this more new data to write in this random district of first overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in the random district's search table of this first overall situation;

When those first upgraded that the number of logical block is non-is less than this preset number time, judge whether those second numbers having upgraded logical block are less than this preset number; And

When those second numbers having upgraded logical block are less than this preset number, for this first logical block configuration one second index number, by this more new data to write in this random district of second overall situation and use should this second index number of the first logical block record should this lastest imformation of the first logical page (LPAGE) in the random district's search table of this second overall situation.

8. a Memory Controller, for controlling a reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple physical blocks, and each the plurality of physical blocks has multiple physical page, and this Memory Controller comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module; And

One memory management circuitry, is electrically connected to this host interface and this memory interface, and in order to the plurality of physical blocks to be at least grouped into a data field and an idle district,

Wherein the plurality of physical blocks belonging to this data field and this idle district is grouped into multiple physical location by this memory management circuitry, and wherein those physical locations in this idle district are in order to replace those physical locations of this data field to write data,

Wherein this memory management circuitry configures multiple logical block to map those physical locations of this data field, and wherein each those logical block has multiple logical page (LPAGE),

Wherein this memory management circuitry extracts at least one physical location as a random district of the overall situation from those physical locations in this idle district, wherein the random district of this overall situation is in order to the temporary data belonging to multiple more new logical page, and those more new logical page to belong among those logical blocks multiple upgrades logical block

Wherein this memory management circuitry sets up the random district's search table of an overall situation to be recorded in multiple lastest imformations of those more new logical page of correspondence in the random district of this overall situation,

Wherein this memory management circuitry receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among those logical blocks,

Wherein this memory management circuitry judges whether the random district of this overall situation stores the data belonging to this first logical block,

Wherein when the random district of this overall situation does not store the data belonging to this first logical block, this memory management circuitry judges whether those numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of those logical blocks,

When the number wherein having upgraded logical block when those is less than this preset number, this memory management circuitry is this first logical block configuration one first index number, by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

9. Memory Controller according to claim 8,

Wherein when the random district of this overall situation stores the data belonging to this first logical block, this memory management circuitry by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

10. Memory Controller according to claim 8,

Wherein when those have upgraded that the number of logical block is non-is less than this preset number, this memory management circuitry extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block, wherein this muon physics unit is only in order to store the data belonging to this first logical block.

11. Memory Controllers according to claim 8,

Wherein one of this memory management circuitry record each those logical block corresponding write number of times and according to those write number of times of those logical blocks corresponding, those logical blocks divided into a hot logic area and a cold logic area.

12. Memory Controllers according to claim 11, wherein this memory management circuitry also judges whether this first logical block belongs to this cold logic area, and

Only when this first logical block is non-belong to this cold logic area time, this memory management circuitry just judges whether the random district of this overall situation stores the data belonging to this first logical block,

Wherein when this first logical block belongs to this cold logic area, this memory management circuitry extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block.

13. 1 kinds of memorizer memory devices, comprising:

A connector, in order to be electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, has multiple physical blocks and each the plurality of physical blocks has multiple physical page; And

One Memory Controller, is electrically connected to this connector and this reproducible nonvolatile memorizer module, and in order to the plurality of physical blocks to be at least grouped into a data field and an idle district,

Wherein the plurality of physical blocks belonging to this data field and this idle district is grouped into multiple physical location by this Memory Controller, and wherein those physical locations in this idle district are in order to replace those physical locations of this data field to write data,

Wherein this Memory Controller configures multiple logical block to map those physical locations of this data field, and wherein each those logical block has multiple logical page (LPAGE),

Wherein this Memory Controller extracts at least one physical location as a random district of the overall situation from those physical locations in this idle district, wherein the random district of this overall situation is in order to the temporary data belonging to multiple more new logical page, and those more new logical page to belong among those logical blocks multiple upgrades logical block

Wherein this Memory Controller sets up the random district's search table of an overall situation to be recorded in multiple lastest imformations of those more new logical page of correspondence in the random district of this overall situation,

Wherein this Memory Controller receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among those logical blocks,

Wherein this Memory Controller judges whether the random district of this overall situation stores the data belonging to this first logical block,

Wherein when the random district of this overall situation does not store the data belonging to this first logical block, this Memory Controller judges whether those numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of those logical blocks,

When the number wherein having upgraded logical block when those is less than this preset number, this Memory Controller is this first logical block configuration one first index number, by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

14. memorizer memory devices according to claim 13,

Wherein when the random district of this overall situation stores the data belonging to this first logical block, this Memory Controller by this more new data to write in the random district of this overall situation and use should this first index number of the first logical block record should a lastest imformation of the first logical page (LPAGE) in this overall situation at random district's search table.

15. memorizer memory devices according to claim 13,

Wherein when those have upgraded that the number of logical block is non-is less than this preset number, this Memory Controller extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block, wherein this muon physics unit is only in order to store the data belonging to this first logical block.

16. memorizer memory devices according to claim 13,

Wherein one of this Memory Controller record each those logical block corresponding write number of times and according to those write number of times of those logical blocks corresponding, those logical blocks divided into a hot logic area and a cold logic area.

17. memorizer memory devices according to claim 16, wherein this Memory Controller also judges whether this first logical block belongs to this cold logic area, and

Only when this first logical block is non-belong to this cold logic area time, this Memory Controller just judges whether the random district of this overall situation stores the data belonging to this first logical block.

18. memorizer memory devices according to claim 17,

Wherein when this first logical block belongs to this cold logic area, this Memory Controller extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block.

19. 1 kinds of method for writing data, for a reproducible nonvolatile memorizer module, wherein reproducible nonvolatile memorizer module has multiple physical blocks, each the plurality of physical blocks has multiple physical page, the plurality of physical blocks is at least grouped into a data field and an idle district, the plurality of physical blocks belonging to this data field and this idle district is grouped into multiple physical location, those physical locations in this idle district are in order to replace those physical locations of this data field to write data, multiple logical block is configured to those physical locations mapping this data field, and each those logical block has multiple logical page (LPAGE), this method for writing data comprises:

At least one physical location is extracted as a random district of the overall situation from those physical locations in this idle district, wherein the random district of this overall situation is in order to the temporary data belonging to multiple more new logical page, and those more new logical page to belong among those logical blocks multiple upgrades logical block;

Receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among those logical blocks;

Judge whether the random district of this overall situation stores the data belonging to this first logical block;

When the random district of this overall situation stores the data belonging to this first logical block, by this more new data write to this overall situation district at random;

When the random district of this overall situation does not store the data belonging to this first logical block, judge whether those numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of those logical blocks;

When the number that those have upgraded logical block is less than this preset number, by this more new data write in the random district of this overall situation; And

When those have upgraded that the number of logical block is non-is less than this preset number, extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block, wherein this muon physics unit is only in order to store this to should the data of the first logical block.

20. 1 kinds of memorizer memory devices, comprising:

A connector, in order to be electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, has multiple physical blocks and each the plurality of physical blocks has multiple physical page; And

One Memory Controller, is electrically connected to this connector and this reproducible nonvolatile memorizer module, and in order to the plurality of physical blocks to be at least grouped into a data field and an idle district,

Wherein the plurality of physical blocks belonging to this data field and this idle district is grouped into multiple physical location by this Memory Controller, and wherein those physical locations in this idle district are in order to replace those physical locations of this data field to write data,

Wherein this Memory Controller configures multiple logical block to map those physical locations of this data field, and wherein each the plurality of logical block has multiple logical page (LPAGE),

Wherein this Memory Controller extracts at least one physical location as a random district of the overall situation from those physical locations in this idle district, wherein the random district of this overall situation keeps in the data belonging to multiple more new logical page, and to belong among the plurality of logical block multiple upgrades logical block for the plurality of more new logical page

Wherein this Memory Controller receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among the plurality of logical block,

Wherein this Memory Controller judges whether the random district of this overall situation stores the data belonging to this first logical block,

Wherein when the random district of this overall situation does not store the data belonging to this first logical block, this Memory Controller judges whether those numbers having upgraded logical block are less than a preset number, and wherein this present count is less than the sum of the plurality of logical block,

Wherein when the plurality of number having upgraded logical block is less than this preset number, this Memory Controller by this more new data write in the random district of this overall situation,

Wherein when the random district of this overall situation stores the data belonging to this first logical block, this Memory Controller by this more new data write to this overall situation at random in district,

Wherein when those have upgraded that the number of logical block is non-is less than this preset number, this Memory Controller extract among those physical locations in this idle district one first physical location as to should the first logical block a muon physics unit and by this more new data write to should this muon physics unit of the first logical block, wherein this muon physics unit is only in order to store the data belonging to this first logical block.