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CN102956594A - 带有引线框连接的功率覆盖结构 - Google Patents

带有引线框连接的功率覆盖结构 Download PDF

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Publication number
CN102956594A
CN102956594A CN2012102918945A CN201210291894A CN102956594A CN 102956594 A CN102956594 A CN 102956594A CN 2012102918945 A CN2012102918945 A CN 2012102918945A CN 201210291894 A CN201210291894 A CN 201210291894A CN 102956594 A CN102956594 A CN 102956594A
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China
Prior art keywords
pol
submodule
lead frame
attached
base plate
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Granted
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CN2012102918945A
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CN102956594B (zh
Inventor
A.V.高达
P.A.麦康內李
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General Electric Co
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General Electric Co
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Abstract

本发明涉及带有引线框连接的功率覆盖结构。公开了一种合并引线框连接的功率覆盖(POL)封装结构。该POL结构(10)包括POL子模块(14)，其具有：介电层(30)；至少一个半导体装置(12)，其附连到介电层(30)上且其包括由半导体材料构成的基板和形成于基板上的多个连接垫；以及金属互连结构(38)，其电联接到至少一个半导体装置(12)的多个连接垫，其中金属互连结构(38)延伸通过介电层(30)中的通孔(36)以便连接到多个连接垫。该POL结构(10)还包括引线框(26)，其电联接到POL子模块(14)，其中引线框(26)包括引线(28)，引线(28)被配置成形成到外部电路结构(27)的互连。

Description

带有引线框连接的功率覆盖结构
技术领域
本发明的实施例大体而言涉及用于封装半导体装置的结构和方法，且更特定而言涉及在其中合并了引线框(leadframe)连接的功率覆盖(POL)封装结构。
背景技术
功率半导体装置为用作功率电子电路中的开关或整流器的半导体装置，诸如开关式电源。大部分功率半导体装置仅用于通信模式(即，它们或者导通或者截止)，且因此对此进行优化。许多功率半导体装置用于高电压功率应用中且被设计成输送大量电流且支持大电压。在使用中，高电压功率半导体装置经由功率覆盖(POL)封装和互连系统连接到外部电路，其中POL封装也提供移除由装置所生成的热且保护该装置免受外部环境影响的方式。
标准POL封装制造工艺通常始于经由粘合剂将一个或多个功率半导体装置放置于介电层上。金属互连(例如，铜互连)然后电镀到介电层上以形成到(多个)功率半导体装置的直接金属连接。金属互连可呈小轮廓(例如，小于200微米厚)、平坦互连结构的形式，其提供用于到和自(多个)功率半导体装置的输入/输出(I/O)系统的形成。
为了连接到外部电路，诸如通过形成到印刷电路板的二级互连，例如，当前的POL封装使用焊球栅阵列(BGA)或盘栅阵列(LGA)。虽然这些类型的互连的短间隔高度(~5至20 mil)提供小轮廓，但是这种连接易于在高应力条件下出现早期失效。即，很大的温度循环范围、冲击和振动可在这些焊点中引起失效。
因此，将期望提供一种POL封装，其具有耐受高应力条件下的失效的互连以便提高互连可靠性。还期望对于这种POL封装来提供这种可靠性同时最小化POL封装的成本。
发明内容
本发明的实施例通过提供一种半导体装置封装结构而克服了前述缺陷，这种半导体装置封装结构消除了焊球栅阵列(BGA)或盘栅阵列(LGA)的使用以将POL封装连接到外部电路。向POL封装提供引线框连接以提供可在多种高应力环境下可用的高度可靠的互连结构。
根据本发明的一方面，一种功率覆盖(POL)结构，包括：POL子模块，其中POL子模块还包括：介电层；附连到介电层上的至少一个半导体装置，其包括由半导体材料构成的基板和形成于基板上的多个连接垫(pad)；以及金属互连结构，其电联接到至少一个半导体装置的多个连接垫，其中金属互连结构延伸通过穿过介电层形成的通孔(via)以便连接到多个连接垫。该POL结构还包括引线框，其电联接到POL子模块，引线框包括引线，其配置成形成到外部电路结构的互连。
根据本发明的另一方面，一种功率覆盖(POL)封装结构，包括：POL子模块，其具有介电层；至少一个半导体装置，其附连到介电层上且包括由半导体材料构成的基板和形成于基板上的多个连接垫；以及一级互连结构，其电联接到至少一个半导体装置的多个连接垫，其中一级互连结构延伸通过穿过介电层形成的通孔以便连接到多个连接垫。该POL封装结构还包括二级互连结构，其将POL子模块电联接到外部电路结构，二级互连结构包括引线框，其被配置成形成到外部电路结构的互连。
根据本发明的又一方面，一种形成功率覆盖(POL)结构的方法，包括：提供POL子模块，其包括介电层；至少一个半导体装置，其附连到介电层上；以及金属互连结构，其延伸通过介电层中的通孔以电连接到至少一个半导体装置。该方法还包括：提供用于POL子模块的引线框，其被配置成在POL子模块与外部电路结构之间形成互连，其中，引线框基于引线框到POL子模块上的直接附连和引线框到位于POL子模块与引线框之间的直接覆铜(DBC)基板的附连中的一个电联接到POL子模块。该方法还包括：利用聚合材料来包封POL子模块和引线框的一部分以为POL结构提供结构刚度。
通过结合附图提供的本发明的优选实施例的下文的详细描述，这些和其它优点和特征将更易于理解。
附图说明
附图示出了目前设想到的用于执行本发明的实施例。
在附图中：
图1为根据本发明的实施例的功率覆盖(POL)结构的示意截面侧视图。
图2至图13为根据本发明的实施例在制造/组建工序的各个阶段期间的POL结构的示意截面侧视图。
图14为根据本发明的另一实施例的POL结构的示意截面侧视图。
具体实施方式
本发明的实施例提供了一种具有合并在其中的引线框连接的半导体装置封装，以及形成这种半导体装置封装的方法。制造该半导体装置封装使得引线框连接形成高度可靠的互连结构，可用于多种高应力环境中，用于将半导体装置封装附连到外部电路上。
参看图1，示出了根据本发明的实施例的功率覆盖(POL)封装和互连结构10。POL结构10包括在其中的一个或多个半导体装置12，其根据各种实施例可呈管芯、二极管或其它功率电子装置的形式。如图1所示，两个半导体装置12设于POL结构10中，但应认识到更多或更少量的半导体装置12可包括于POL结构10中。(多个)半导体装置12封装于POL子模块14内，如将在下文中更详细地解释地，POL子模块14形成到(多个)功率半导体装置12的直接金属连接，其中连接呈小轮廓、平坦互连结构的形式，例如，其提供用于到和自(多个)半导体功率装置12的输入/输出(I/O)系统的形成。根据本发明的一个实施例，诸如电阻器、电容器或感应器的无源装置/构件16也包括于POL结构10中。
如图1所示，POL结构10还包括直接覆铜(DBC)基板18或POL子模块14和无源装置16附连到其上的另一类似基板。DBC基板18包括瓷板(例如，氧化铝)20，其带有通过高温结合工艺而接合到其两侧的铜片22、24。根据本发明的实施例，可基于例如基板18由氧化铝还是氮化铝和氮化硅等形成来采用不同的硬焊和直接接合技术。通常在烧制后蚀刻DBC 18的两侧。在DBC基板18的后侧上的底部铜层24留置为完全或者部分地暴露以提供从POL结构10的高效地向外的传热。虽然在上文和下文中称作“DBC”基板，但是应认识到铝可代替铜用作金属层，且因此这种实施例也被认为在本发明的范围内。因此，在下文中使用术语“DBC基板”来意图涵盖包括瓷板(例如氧化铝)20的结构18，瓷板20带有接合到其两侧的由任何合适金属材料(诸如铜或铝)制成的片22、24。
如在图1中进一步示出地，DBC基板18包括附连于其上的引线框26。根据本发明的实施例，在将POL子模块14放置于DBC基板上之前将引线框26预先附连到DBC基板18上，诸如经由高温结合工艺，如焊接(solder)、硬焊、熔接或其它类似方法，但应认识到根据本发明的另一实施例，引线框26可备选地在后附连(取决于所用的焊接材料)。在附连到DBC基板18上之后，引线框26随后被切割且形成以允许将POL结构10表面安装到诸如印刷电路板(PCB)27的外部电路上。引线框26被形成为包括多根引线28，引线28被配置为附连/附接到PCB上以将POL结构10电联接到PCB。引线框26提供高度可靠的互连结构，其耐受在高应力条件下的失效，诸如经历温度循环范围、冲击和振动的汽车环境。聚合物底部填充件或包封或外模(overmold)29设于POL结构10上，其包封POL子模块14的顶部和连接到DBC基板18的引线框26的区域且填充在POL结构10中的间隙，以便向POL结构10提供额外的结构完整性。根据一个实施例，包封29还施加到DBC基板18的后表面的至少一部分上。
虽然POL结构10在图1中被示出为包括具有附连到其上的引线框26的DBC基板18，但应认识到还设想不包括DBC基板18的本发明的额外实施例。即，根据本发明的额外实施例，提供引线框26，其直接附连到POL子模块14上，其中POL子模块14在附连到引线框26上时被形成外模或包封。因此引线框26被合适地设计成允许路由和合并POL子模块14。
现参看图2至图12，根据本发明的实施例，提供用于制造图1的POL结构10的技术的工序步骤的详细视图。如首先在图2至图9中所示，提供了用于组建POL子模块14的工序步骤。参看图2，POL子模块14的组建工序始于将介电层30放置并附连到框架结构32上。介电层30呈叠层或膜的形式且放置于框架结构32上以在POL子模块14的组建工序期间提供稳定性。根据本发明的实施例，介电层30可由多种介电材料中的一种，诸如Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚砜材料(例如，Udel®、Radel®)或其它聚合物膜，诸如液晶聚合物(LCP)或聚酰亚胺材料来形成。
如图3所示，在将介电层30固定到框架结构32上后，粘合剂层34沉积到介电层30上。然后多个通孔36通过粘合剂层34和电介质叠层42形成，如图4所示。根据本发明的实施例，通孔36可经由激光消融或激光钻制工艺、等离子体蚀刻、光界定或机械钻制工艺。在下一技术步骤中，一个或多个半导体装置12经由粘合剂层34固定到介电层30上，如图5所示。为了将半导体装置12固定到电介质30上，半导体装置12放置于粘合剂层34上且然后使得粘合剂34固化以将半导体装置12固定到介电层30上。
虽然在图4中示出在将半导体装置12放置到粘合剂层34上之前执行通过粘合剂层34和电介质叠层30的通孔36的形成，但是应认识到可在通孔形成之前放置半导体装置12。即，取决于由通孔尺寸所施加的约束，半导体装置12可首先放置于粘合剂层34和介电层30上，其中通孔36随后在对应于在半导体装置12上所形成的多个金属电路和/或连接垫(未图示)的位置处形成。而且，可根据需要来采用预钻制通孔和在后钻制通孔的组合。
现参看图6和图7，在将半导体装置12固定于介电层30上且形成通孔36后，清洁通孔36(诸如通过反应式离子蚀刻(RIE)除尘工艺)且随后将通孔36金属化以形成互连38。金属互连38通常通过溅射和电镀应用的组合来形成，但应认识到也可使用金属沉积的其它无电方法。例如，钛粘附层和铜晶种层可首先经由溅射工艺来涂覆，继之以电镀工艺，其将铜的厚度增加到期望的水平。随后将所施加的金属材料模式化为具有所期望的形状的金属互连38(即，一级互连)且其充当通过介电层30和粘合剂层34形成的竖直馈通。如图6所示，根据一个实施例，金属互连38形成到在半导体装置12上的电路/连接垫的直接金属和电连接且其电连接两个半导体装置12。金属互连38从半导体装置12的电路和/或连接垫延伸出，通过通孔/开口36且出来横跨介电层30的顶部表面。如图8所示，焊接掩膜层40施加于模式化的金属互连38上以提供用于其铜垫片的保护涂层。但应认识到，根据本发明的其它实施例，无需施加焊接掩膜层40。即，仅在计划随后焊接POL子模块14或使POL子模块14的表面开放时需要焊接掩膜层40。此外，该层40可由并非焊接料的一些金属材料组成，诸如Ni或Ni/Au，或者随后可被包封的裸铜。
在完成了POL子模块14的组建时，POL子模块14被单个化且从框架结构32移除，如在图9中所示。因此提供完成的POL子模块14，其包括半导体装置12和金属互连38，金属互连38充当金属竖直馈通和顶侧互连。POL子模块14处置为构件或多芯片模块。根据一个实施例，铜垫片也可设于POL子模块14中且用作电短路件。铜垫片类似于半导体管芯12那样使用但由铜或类似材料制成。如氧化铝或氮化铝的陶瓷还可用于提供机械支承或充当热导管。
现参看图10，根据本发明的一个实施例，制造POL结构10的技术继续将POL子模块14和半导体装置12附连到直接覆铜(DBC)基板18上。如图10所示，POL子模块14经由焊接材料42附连到DBC基板18上，以便将POL子模块14和DBC基板18固定在一起。根据一个实施例，诸如电阻器、电容器或感应器的无源装置/构件16也焊接附连到DBC基板18上。
如在图10中进一步示出地，DBC基板18包括附连于其上的引线框26。引线框26可在附连POL子模块14(和无源装置16)之前预附连到DBC基板18上，或者在后附连，即在将POL子模块14附连到DBC基板18上之后附连。根据本发明的实施例，引线框26经由诸如焊接、硬焊、熔接的高温结合工艺或其它合适的方法而预先附连到DBC基板18上。聚合物底部填充件或包封44(例如，环氧化物)设于POL结构10上，其包封POL子模块14和连接到DBC基板18的引线框26的部分。聚合物底部填充件/包封44也填充在POL结构10中的间隙，如在图11中所示的那样，以便向POL结构10提供额外的结构完整性。根据一个实施例，包封44也施加到在瓷板20上DBC基板18的后表面的至少一部分上。
如图12所示，在利用环氧化物44包封POL子模块14时，引线框26随后切割且形成为允许POL结构10表面安装到外部电路，诸如PCB(未图示)。引线框26被切割/形成为包括多根引线28，引线28被配置为附连/附接到PCB上以将POL结构10电联接到PCB，使得引线框26形成用于POL结构10的二级互连。如在图12中可看出地，引线框26经由顶部铜层22而电联接到POL子模块14，使得能在POL子模块14与PCB之间形成互连。有益地，引线框26提供高度可靠的互连结构，其耐受在高应力条件下的失效。
现参看图13，根据本发明的一个实施例，制造POL结构10的工序继续将帽46绕POL结构10的POL子模块14定位和固定。具体而言，帽46绕DBC基板形成且固定到DBC基板上，且然后在密封之前可或可不填充聚合物。根据本发明的实施例，帽46可呈密闭帽或非密闭帽的形式。当帽46为密闭帽时，因为DBC基板18本身基于其中包括瓷板20而为密闭的结构，故密闭帽46与DBC基板18组合以密闭地密封POL子模块14与外部环境。这种密闭密封有益于高应力环境和条件，诸如经历温度循环范围、冲击和振动的汽车环境。在其它实施例中，帽46可为非密闭的塑料外壳，其附连到DBC基板18且填充有聚合物以避免使用模具，帽/盖46可拥有填充孔，聚合物可通过填充孔施加且然后密封。
有益地，根据图2至图13所示的工艺步骤形成的POL结构10被构造成使得使所有的连接到DBC基板平面(与现有技术中使连接到POL铜平面相比)且使得引线框26附连到DBC基板18，从而提高了POL结构10的可靠性。POL结构10还提供用于在POL子模块14外侧附连无源件14，从而允许使用标准的无源件和更小的POL子模块14。
现参看图14，示出根据本发明的另一实施例的POL结构50。如图13所示，提供引线框52，其直接附连到POL子模块54上，但在它们之间并不存在中间DBC基板。POL子模块54类似于图9所示的POL子模块14，例如，因为其包括介电层56，半导体装置58(和在要求时，用于竖直电或热互连的垫片58)经由粘合剂层60固定到介电层56上。通孔62向下通过介电层56形成到在半导体装置/垫片58上的连接垫(未图示)且随后金属化以形成具有期望形状的互连64和顶侧互连。
根据图14中所示的POL结构50的实施例，引线框52直接附连到半导体装置58的后表面上，诸如经由焊接材料66，其中引线框52被构造成允许在其上路由和合并POL子模块54。在将引线框52焊接附连到半导体装置58上之后，聚合物底部填充件、外模或包封68设于POL结构50上，其包封POL子模块54和引线框52的一部分。聚合物底部填充件/包封68还填充在POL结构50中的任何间隙，从而向POL结构50提供额外的结构完整性。备选地，填充POL结构50下方的间隙的材料68可不同于该结构周围的外模/包封68。
因此，根据本发明的一个实施例，一种功率覆盖(POL)结构，包括：POL子模块，其中POL子模块还包括：介电层；附连到介电层上的至少一个半导体装置，其包括由半导体材料构成的基板和形成于基板上的多个连接垫；以及金属互连结构，其电联接到至少一个半导体装置的多个连接垫，其中金属互连结构延伸通过穿过介电层形成的通孔以便连接到多个连接垫。该POL结构还包括引线框，其电联接到POL子模块，其中引线框包括引线，引线被配置成形成到外部电路结构的互连。
根据本发明的另一实施例，一种功率覆盖(POL)封装结构，包括：POL子模块，其具有介电层；至少一个半导体装置，其附连到介电层上且包括由半导体材料构成的基板和形成于基板上的多个连接垫；以及一级互连结构，其电联接到至少一个半导体装置的多个连接垫，其中一级互连结构延伸通过穿过介电层形成的通孔以便连接到多个连接垫。该POL封装结构还包括二级互连结构，其将POL子模块电联接到外部电路结构，二级互连结构包括引线框，引线框被配置成形成到外部电路结构的互连。
根据本发明的又一实施例，一种形成功率覆盖(POL)结构的方法，包括：提供POL子模块，其包括介电层；至少一个半导体装置，其附连到介电层上；以及金属互连结构，其延伸通过介电层中的通孔以电连接到至少一个半导体装置。该方法还包括：提供用于POL子模块的引线框，其被配置成在POL子模块与外部电路结构之间形成互连，其中引线框基于引线框到POL子模块上的直接附连和引线框到位于POL子模块与引线框之间的直接覆铜(DBC)基板的附连中的一个而电联接到POL子模块。该方法还包括：利用聚合材料来包封POL子模块和引线框的一部分来向POL结构提供结构刚度。
虽然仅关于有限数目的实施例描述了本发明，但应易于了解本发明并不限于这种公开的实施例。而是，可修改本发明以合并之前未描述但与本发明的精神和范围相符的任意数目的变型、更改、备选或等效布置。此外，虽然描述了本发明的各种实施例，但是应了解本发明的方面可仅包括所述实施例中的一些。因此，本发明不应视作受前文的描述限制，而是仅受所附权利要求的范围限制。

Claims (10)

1.一种功率覆盖(POL)结构(10)，包括：
POL子模块(14)，所述POL子模块(14)包括：
介电层(30)；
附连到所述介电层(30)上的至少一个半导体装置(12)，其中所述至少一个半导体装置(12)中的每一个包括由半导体材料构成的基板和形成于所述基板上的多个连接垫；以及
金属互连结构(38)，其电联接到所述至少一个半导体装置(12)的多个连接垫，所述金属互连结构(38)延伸通过穿过所述介电层(30)形成的通孔(36)以便连接到所述多个连接垫；以及
引线框(26)，其电联接到所述POL子模块(14)，所述引线框(26)包括引线(28)，所述引线(28)被配置成形成到外部电路结构(27)的互连。
2.根据权利要求1所述的POL结构(10)，其特征在于，还包括多层基板(18)，其具有第一表面和第二表面，其中，所述POL子模块(14)附连到所述多层基板(18)的第一表面上。
3.根据权利要求2所述的POL结构(10)，其特征在于，还包括位于所述多层基板(18)与所述POL结构(10)之间的焊接材料、导电粘合剂或烧结银中的一种，以将所述POL子模块(14)固定到所述多层基板(18)上。
4.根据权利要求3所述的POL结构(10)，其特征在于，还包括无源装置(16)，其经由所述焊接材料、所述导电粘合剂或所述烧结银而附连到所述多层基板(18)。
5.根据权利要求2所述的POL结构(10)，其特征在于，所述引线框(26)附连到所述多层基板(18)的第一表面上。
6.根据权利要求5所述的POL结构(10)，其特征在于，所述多层基板(18)包括直接覆铜(DBC)基板，并且其中，所述DBC基板的第一表面包括铜或铝板(22)，所述铜或铝板(22)被配置成将所述引线框(26)电联接到所述POL子模块(14)。
7.根据权利要求2所述的POL结构(10)，其特征在于，还包括包封(44)，其绕所述POL子模块(14)且在所述引线框(26)的一部分上、在所述多层基板(18)的第一表面上形成。
8.根据权利要求2所述的POL结构(10)，其特征在于，还包括帽(46)，其附连到所述多层基板(18)，其中，所述帽(46)包括密闭帽和非密闭帽中的一种；以及
其中，当所述帽(46)包括密闭帽时，所述密闭帽与所述多层基板(18)组合，密闭地密封所述POL子模块(14)与周围环境。
9.根据权利要求1所述的POL结构(10)，其特征在于，所述引线框(26)直接附连到所述POL子模块(14)的至少一个半导体装置(12)。
10.根据权利要求1所述的POL结构(10)，其特征在于，所述POL子模块(14)无需引线接合连接。
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US9165864B2 (en) 2015-10-20
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