CN102956455B - Manufacturing method of semiconductor devices - Google Patents
Manufacturing method of semiconductor devices Download PDFInfo
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- CN102956455B CN102956455B CN201110239276.1A CN201110239276A CN102956455B CN 102956455 B CN102956455 B CN 102956455B CN 201110239276 A CN201110239276 A CN 201110239276A CN 102956455 B CN102956455 B CN 102956455B
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Abstract
The invention provides a manufacturing method of semiconductor devices. The manufacturing method includes providing a semiconductor substrate, forming a virtual grid structure comprising a sacrificial grid electrode layer on the semiconductor substrate, and forming gap wall structures, close to the virtual grid structure, on the two sides of the virtual grid structure; removing the sacrificial grid electrode layer to form a grid trench in the middle of the gap wall structures, forming a first work function metal layer and a second work function metal layer in the grid trench sequentially; performing annealing treatment to form an alloy layer in the grid trench; and backfilling the metal grid. Since titanium aluminum alloy is selected as a material for work function metal layers in the high-k metal grid structure of an NMOS (N-channel metal oxide semiconductor FET), requirements of the NMOS to work functions can be met.
Description
Technical field
The present invention relates to semiconductor fabrication process, be used for the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS in particular to a kind of adjustment.
Background technology
Along with the continuous innovation of ic manufacturing technology, the size of the various elements in integrated circuit constantly reduces, and functionalization density constantly increases simultaneously.Under scaled principle, the ic manufacturing technology of development improves production efficiency, reduces manufacturing cost; Meanwhile, the problem of high power consumption is also brought.Had the semiconductor device of low-power consumption feature by application, such as complementary metal oxide semiconductors (CMOS) (CMOS), can solve the problem of above-mentioned high power consumption.
Typical CMOS comprises gate oxide and polysilicon gate.Due to the continuous reduction of feature sizes of semiconductor devices, substitute gate oxide in CMOS and polysilicon gate respectively with high k grid dielectric medium and metal gates, the performance of cmos device can be improved.But the work function for the workfunction layers in the high-k/metal gate structure of NMOS and PMOS is different, the scope for the work function of the described workfunction layers of PMOS is 4.9-5.2eV; Scope for the work function of the described workfunction layers of NMOS is 3.9-4.1eV.In traditional formation process of the workfunction layers for PMOS, usually select titanium-aluminium alloy (TiAl) as the material of described workfunction layers, when the material selecting titanium-aluminium alloy as the workfunction layers for NMOS, it is very challenging for adjusting its work function had to meet NMOS for the requirement of described work function.
Therefore, needing to propose a kind of method, when selecting titanium-aluminium alloy as material for the workfunction layers in the high-k/metal gate structure of NMOS, the requirement of NMOS for described work function can be met.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: Semiconductor substrate is provided, be formed with dummy gate structure on the semiconductor substrate, described dummy gate structure comprises sacrificial gate dielectric layer, and is formed with the clearance wall structure near described dummy gate structure in the both sides of described dummy gate structure; Remove described sacrificial gate dielectric layer, to form a gate groove in the middle of described clearance wall structure, and in described gate groove, form the first workfunction layers and the second workfunction layers successively; Perform an annealing in process, to form an alloy-layer in described gate groove; Implement the backfill of metal gate.
Further, described dummy gate structure comprises the boundary layer stacked gradually, high k dielectric layer, cover layer and sacrificial gate dielectric layer from bottom to top.
Further, etch described dummy gate structure, remove the described sacrificial gate dielectric layer of the described dummy gate structure the superiors, to form described gate groove.
Further, physical gas-phase deposition is adopted to form described first workfunction layers and the second workfunction layers.
Further, the material of described first workfunction layers is titanium.
Further, the material of described second workfunction layers is titanium-aluminium alloy.
Further, the thickness of described first workfunction layers is 10-40 dust.
Further, the thickness of described second workfunction layers is 20-50 dust.
Further, the temperature of described annealing in process is 400-500 DEG C.
Further, the time that described annealing in process continues is 120-300s.
Further, the formation of described alloy-layer is Ti
xal, x>1.
Further, before the backfill implementing metal gate, form barrier layer and soakage layer successively, cover described alloy-layer.
Further, atom layer deposition process or physical gas-phase deposition is adopted to form described barrier layer.
Further, the material on described barrier layer is tantalum nitride or titanium nitride.
Further, physical gas-phase deposition is adopted to form described soakage layer.
Further, the material of described soakage layer is titanium.
Further, the material of described metal gate is aluminium.
Further, chemical vapor deposition method or physical gas-phase deposition is adopted to carry out the backfill of described metal alum gate.
Further, after the backfill implementing metal alum gate, chemical mechanical milling tech is adopted to remove the described metal alum gate at described clearance wall structure top, soakage layer, barrier layer and alloy-layer.
Further, described semiconductor device is NMOS.
According to the present invention, when selecting titanium-aluminium alloy as material for the workfunction layers in the high-k/metal gate structure of NMOS, the requirement of NMOS for work function can be met.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 F is the schematic cross sectional view of the adjustment that proposes of the present invention for each step of the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS;
Fig. 2 is the flow chart of the adjustment that proposes of the present invention for the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the present invention how to adjust work function for the workfunction layers in the high-k/metal gate structure of NMOS.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step of adjustment for the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS of the present invention's proposition is described with reference to Figure 1A-Fig. 1 F and Fig. 2.
With reference to Figure 1A-Fig. 1 F, illustrated therein is the schematic cross sectional view of adjustment for each step of the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS of the present invention's proposition.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.In Semiconductor substrate 100, be formed with isolation channel, buried regions etc., in order to simplify, be omitted in diagram.
Described Semiconductor substrate 100 is formed with dummy gate structure 101, and as an example, described dummy gate structure 101 can comprise the boundary layer stacked gradually, high k dielectric layer, cover layer (capping layer) and sacrificial gate dielectric layer from bottom to top.The material of boundary layer can comprise oxide, as silicon dioxide (SiO
2).The material of high k dielectric layer can comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia and aluminium oxide.Tectal material can comprise titanium nitride and tantalum nitride.The material of sacrificial gate dielectric layer can comprise polysilicon.
In addition, exemplarily, described Semiconductor substrate 100 is also formed is positioned at described dummy gate structure 101 both sides and near the clearance wall structure 102 of described dummy gate structure.Wherein, described clearance wall structure 102 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
Then, as shown in Figure 1B, with described clearance wall structure 102 for mask, etch described dummy gate structure, remove the sacrificial gate dielectric layer of the described dummy gate structure the superiors, in the middle of described clearance wall structure 102, form a gate groove 103.Employing traditional handicraft completes the etching to described sacrificial gate dielectric layer, such as dry etching.
Next, in described gate groove 103, form the first workfunction layers 104 and the second workfunction layers 105 successively.Physical gas-phase deposition is adopted to form described first workfunction layers 104 and the second workfunction layers 105.The material of described first workfunction layers 104 is titanium (Ti), and the material of described second workfunction layers 105 is titanium-aluminium alloy (TiAl).
The thickness of described first workfunction layers 104 is 10-40 dust, and the thickness of described second workfunction layers 105 is 20-50 dust.
Form described first workfunction layers 104 and the second workfunction layers 105 in described gate groove 103 while, also can form described first workfunction layers 104 and the second workfunction layers 105 at the top of described clearance wall structure 102.
Then, as shown in Figure 1 C, perform an annealing in process, make the Al in described second workfunction layers be flowed in described first workfunction layers, to form Ti
xal(x>1) alloy-layer 106.By adjusting the ratio (i.e. the numerical value of x) of Ti and the Al in described alloy-layer 106, making the work function of described alloy-layer 106 be between 3.9-4.1eV, namely meeting the requirement of NMOS for the work function of workfunction layers.
The temperature of described annealing in process is 400-500 DEG C, and the duration is 120-300s.
Then, as shown in figure ip, in described gate groove 103, form barrier layer 107 and soakage layer 108 successively, cover described alloy-layer 106.
Atom layer deposition process or physical gas-phase deposition is adopted to form described barrier layer 107.The material on described barrier layer 107 comprises tantalum nitride and titanium nitride.Equally, form described barrier layer 107 in described gate groove 103 while, also can form described barrier layer 107 at the top of described clearance wall structure 102.
Physical gas-phase deposition is adopted to form described soakage layer 108.The material of described soakage layer 108 is titanium.Form described soakage layer 108 in described gate groove 103 while, also can form described soakage layer 108 at the top of described clearance wall structure 102.
Then, as referring to figure 1e, the backfill of metal gate 109 is implemented.In this example, the material of described metal gate 109 is aluminium.Chemical vapor deposition method (CVD) or physical gas-phase deposition (PVD) is adopted to carry out the backfill of described metal alum gate.
Then, chemical mechanical milling tech (CMP) is adopted to remove the described metal alum gate at described clearance wall structure 102 top, soakage layer, barrier layer and alloy-layer, as shown in fig. 1f, described metal alum gate, soakage layer, barrier layer are concordant with the top of described clearance wall structure 102 with the surface of alloy-layer for the semiconductor structure 110 obtained.
So far, complete whole processing steps that method is according to an exemplary embodiment of the present invention implemented, in the two-layer workfunction layers formed, the material of lower floor's workfunction layers is titanium, the material of upper strata workfunction layers is titanium-aluminium alloy (TiAl), by controlling the process conditions of annealing in process, the Al in the workfunction layers of upper strata can be made to be flowed in lower floor's workfunction layers, thus form alloy-layer Ti
xal(x>1), the work function with the alloy-layer of different titanium al proportion (i.e. different x value) formed can meet the requirement of different components for work function.
According to the present invention, when selecting titanium-aluminium alloy as material for the workfunction layers in the high-k/metal gate structure of NMOS, the requirement of NMOS for work function can be met.
With reference to Fig. 2, illustrated therein is the flow chart of adjustment for the method for the work function of the workfunction layers in the high-k/metal gate structure of NMOS of the present invention's proposition, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, be formed with dummy gate structure on the semiconductor substrate, described dummy gate structure comprises sacrificial gate dielectric layer, and is formed with the clearance wall structure near described dummy gate structure in the both sides of described dummy gate structure;
In step 202., remove described sacrificial gate dielectric layer, to form a gate groove in the middle of described clearance wall structure, and in described gate groove, form the first workfunction layers and the second workfunction layers successively;
In step 203, perform an annealing in process, to form an alloy-layer in described gate groove;
In step 204, the backfill of metal gate is implemented.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (17)
1. a manufacture method for semiconductor device, comprising:
There is provided Semiconductor substrate, be formed with dummy gate structure on the semiconductor substrate, described dummy gate structure comprises sacrificial gate dielectric layer, and is formed with the clearance wall structure near described dummy gate structure in the both sides of described dummy gate structure;
Remove described sacrificial gate dielectric layer, to form a gate groove in the middle of described clearance wall structure, and in described gate groove, form the first workfunction layers and the second workfunction layers successively, the material of described first workfunction layers is titanium, and the material of described second workfunction layers is titanium-aluminium alloy;
Perform an annealing in process, to form an alloy-layer in described gate groove, the formation of described alloy-layer is Ti
xal, x>1;
Implement the backfill of metal gate.
2. method according to claim 1, is characterized in that, described dummy gate structure comprises the boundary layer stacked gradually, high k dielectric layer, cover layer and sacrificial gate dielectric layer from bottom to top.
3. method according to claim 1 and 2, is characterized in that, etches described dummy gate structure, removes the described sacrificial gate dielectric layer of the described dummy gate structure the superiors, to form described gate groove.
4. method according to claim 1, is characterized in that, adopts physical gas-phase deposition to form described first workfunction layers and the second workfunction layers.
5. method according to claim 1, is characterized in that, the thickness of described first workfunction layers is 10-40 dust.
6. method according to claim 1, is characterized in that, the thickness of described second workfunction layers is 20-50 dust.
7. method according to claim 1, is characterized in that, the temperature of described annealing in process is 400-500 DEG C.
8. method according to claim 1, is characterized in that, the time that described annealing in process continues is 120-300s.
9. method according to claim 1, is characterized in that, also comprises: before the backfill implementing metal gate, form barrier layer and soakage layer successively, cover described alloy-layer.
10. method according to claim 9, is characterized in that, adopts atom layer deposition process or physical gas-phase deposition to form described barrier layer.
11. methods according to claim 9, is characterized in that, the material on described barrier layer is tantalum nitride or titanium nitride.
12. methods according to claim 9, is characterized in that, adopt physical gas-phase deposition to form described soakage layer.
13. methods according to claim 9, is characterized in that, the material of described soakage layer is titanium.
14. methods according to claim 1, is characterized in that, the material of described metal gate is aluminium.
15. methods according to claim 14, is characterized in that, adopt chemical vapor deposition method or physical gas-phase deposition to carry out the backfill of described metal alum gate.
16. methods according to claim 15, is characterized in that, comprise further: after the backfill implementing metal alum gate, adopt chemical mechanical milling tech to remove the described metal alum gate at described clearance wall structure top, soakage layer, barrier layer and alloy-layer.
17. methods according to claim 1, is characterized in that, described semiconductor device is NMOS.
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| CN201110239276.1A CN102956455B (en) | 2011-08-19 | 2011-08-19 | Manufacturing method of semiconductor devices |
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| CN201110239276.1A CN102956455B (en) | 2011-08-19 | 2011-08-19 | Manufacturing method of semiconductor devices |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103094114B (en) * | 2011-10-31 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of transistor |
| CN104124156B (en) * | 2013-04-27 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN104217951B (en) * | 2013-06-04 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method |
| CN104576337B (en) * | 2013-10-11 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN104752316B (en) * | 2013-12-25 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN104766822B (en) * | 2014-01-06 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN106340452A (en) * | 2016-11-30 | 2017-01-18 | 上海华力微电子有限公司 | Metal gate structure and manufacturing method thereof |
| CN108630608A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN111627817B (en) * | 2019-02-28 | 2023-10-13 | 中芯国际集成电路制造(上海)有限公司 | Transistor structures and methods of forming them |
| CN115863408A (en) * | 2021-08-20 | 2023-03-28 | 长鑫存储技术有限公司 | Transistor and method of making the same |
| CN118538603B (en) * | 2024-07-22 | 2024-11-12 | 合肥晶合集成电路股份有限公司 | High dielectric metal gate and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6727560B1 (en) * | 2003-02-10 | 2004-04-27 | Advanced Micro Devices, Inc. | Engineered metal gate electrode |
| CN1812054A (en) * | 2004-12-01 | 2006-08-02 | 三星电子株式会社 | Dual work function metal gate structure and related method of manufacture |
| CN101752317A (en) * | 2008-11-14 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN101877311A (en) * | 2010-06-30 | 2010-11-03 | 复旦大学 | A method to effectively adjust the work function of TiN metal gate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7528024B2 (en) * | 2004-05-24 | 2009-05-05 | Texas Instruments Incorporated | Dual work function metal gate integration in semiconductor devices |
| US20110042728A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | Semiconductor device with enhanced stress by gates stress liner |
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- 2011-08-19 CN CN201110239276.1A patent/CN102956455B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6727560B1 (en) * | 2003-02-10 | 2004-04-27 | Advanced Micro Devices, Inc. | Engineered metal gate electrode |
| US7033888B2 (en) * | 2003-02-10 | 2006-04-25 | Advanced Micro Devices, Inc. | Engineered metal gate electrode |
| CN1812054A (en) * | 2004-12-01 | 2006-08-02 | 三星电子株式会社 | Dual work function metal gate structure and related method of manufacture |
| CN101752317A (en) * | 2008-11-14 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN101877311A (en) * | 2010-06-30 | 2010-11-03 | 复旦大学 | A method to effectively adjust the work function of TiN metal gate |
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