CN102955713B - The disposal route that a kind of 802.11n wireless network card chip emulation firmware is optimized - Google Patents
The disposal route that a kind of 802.11n wireless network card chip emulation firmware is optimized Download PDFInfo
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- CN102955713B CN102955713B CN201110255501.0A CN201110255501A CN102955713B CN 102955713 B CN102955713 B CN 102955713B CN 201110255501 A CN201110255501 A CN 201110255501A CN 102955713 B CN102955713 B CN 102955713B
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Abstract
The invention discloses the disposal route that a kind of wireless network card chip emulation firmware is optimized, the method for the front-end simulation of chip and rear end emulation demand customized firmware, and provides support.Method comprise interruption compilation process, improve cpu bus efficiency and the optimization of firmware volume.The correctness of aforesaid operations can be judged by the self-check module in simulating, verifying environment and simulation waveform and optimize the integrality of rear data.
Description
Technical field
The present invention relates to a kind of disposal route optimized based on SoC framework 802.11n wireless network card chip emulation firmware.
Background technology
Due to the increase of SOC communication chip complexity, more and more stricter to the requirement of power consumption and efficiency, this also just has higher requirement to traditional verification mode.Use firmware and RTL to carry out emulation in the front and back end stage can solve and use CPU model not accurate enough and emulate and cannot measure the problems such as chip power-consumption in the past.
, simulation time long characteristic large based on 802.11n wireless network card chip complexity, considers to improve simulation efficiency by optimizing firmware to reduce the post-simulation time.This kind of optimization method, by the amendment to compilation and C language way of realization, realizes the raising of firmware operation performance, the reduction of firmware volume in the impregnable situation of original function.Add in initialization assembly code simultaneously and also can reduce C size of code to the process of vector interrupt, non vector interrupt, and the amendment to this function after common part integration is together facilitated.
Owing to needing to carry out the work such as time stimulatiom and waveform interception analysis power consumption at post-simulation, emulation uses the operating efficiency of firmware just to seem especially important, and the firmware after optimization can save simulation time in the post-simulation stage, and post-simulation work can be restrained as early as possible.
Summary of the invention
Method of the present invention utilizes assembly language and C language to realize one to cooperatively interact the fixer system carrying out emulating with verification environment, and this system comprises initialization and interrupt response.
Initialization comprises boots, interface and IO initialization, internal register initialization, key list initialization, and wherein interface and IO initialization can be distinguished by macro definition according to the different scenes of firmware application.
Interrupt response comprises downlink command response, upstream data response, downlink data response, UART interrupt response, TIMER interrupt response, WatchDog interrupt response, PMU interrupt response, SPIRF interrupt response etc., wherein achieves in the mode of list structure service data in upstream data response, downlink data response.
The present invention utilizes the collaborative simulation of firmware realization and verification environment and RTL, emulation and post-simulation work before realizing; CPU starts to call firmware program after completing electrification reset, and firmware is according to the data structure response instruction consulted with verification environment and data, and the self-verifying module finally provided by verification environment completes result and judges and terminate emulation; Firmware is as follows with the flow process in verification environment and RTL collaborative simulation process:
(1) first CPU calls in firmware the boots program collecting and write after electrification reset, completes the configuration to interrupt control register, utilize boots program realize interrupt function link and vector interrupt, non vector interrupt initialization operation; By realizing the operation of removing vector interrupt to the indirect assignment of interrupt control register in vector interrupt operation;
(2) association's data structure is used to complete the assignment operation of the related registers such as interface register, internal register, key list, key information district, MAC Address, BD, by association's data structure, scattered data structure is integrated together and carries out whole word assignment;
(3) carrying out in assignment operating process to BD register, using loop statement to replace the code presented in expanded form, realize the optimization of code under identical function;
(4) carry out the operation response of interrupt function, realize downlink command, up-downgoing data manipulation;
(5) the operation response backed off after random interrupt function completing this interrupt function carries out waiting for the process of next interrupt function;
(6), complete the inspection of each transmitting and receiving data frame at verification environment after, emulation is stopped.
Accompanying drawing explanation
Fig. 1 is a kind of process flow figure optimized based on SoC framework 802.11n wireless network card chip emulation firmware;
Fig. 2 uses association's process schematic diagram data;
Fig. 3 uses for loop statement initialization BD schematic diagram;
Fig. 4 is verification environment and firmware structure schematic diagram.
Embodiment
The present invention uses EDA emulation tool to combine checking and firmware collaborative simulation, under the prerequisite of function realizing original firmware, by the optimization to firmware code, realizes the raising of performance and the reduction of firmware area.The automatic comparison module improved by verification environment and the method for checking waveform carry out the judgement of simulation result, according to the validity that its result verification firmware is optimized.
Below in conjunction with drawings and Examples, present invention is described.
Fig. 1 is firmware operation flow chart illustration, describe firmware with the related procedure in verification environment collaborative simulation process.CPU starts to call firmware program after completing electrification reset, and firmware is according to the data structure response instruction consulted with verification environment and data, and the self-verifying module finally provided by verification environment completes result and judges and terminate emulation.
First 101:CPU can call in firmware the boots program collecting and write after electrification reset, completes the configuration to interrupt control register.
102: the initialization operation completing the related registers such as interface register, internal register, key list, key information district, MAC Address, BD.
103: carry out the operation response interrupting irq function, realize downlink command, up-downgoing data manipulation, release the process that irq function carries out waiting for next irq function after completing this operation.If CPU does not temporarily process this irq, do not remove interruption, wait for that next cpu cycle scans in this to have no progeny and process again.
104: after the operation completing an interruption irq service routine, wait for the generation of next irq program.
105: complete the inspection of each transmitting and receiving data frame at verification environment after, stop emulation.
Power on after CPU completes reset at chip, first call the boots program that assembly language is write, the initial configuration of interrupting is operated in and carries out here.Use and " ldrr0 ,=Addr are operated to the assignment of register; Ldrr1 ,=Data; Strr1, [r0] " realize the configuration of interruption control module, if use vector interrupt, by " ldrr9 ,=ICVectAddr; Ldrr9, [r9] " obtain Current interrupt number and indicate PC pointer to jump to response address, realize calling irq interrupt function.Non vector interrupt is then that the mode by reading " IRQStatusReg " register completes redirect.Irq function in C firmware is the entity function of interrupt processing, and this function does not have difference when processing above-mentioned two interruptions.
As shown in Figure 2, after completing operation such as boots interruption initialization and interface initialization etc., association's data structure just can be used to carry out assignment operation to free time such as key list, key information district, MAC Address districts.The feature of this operation is originally scattered data structure to be integrated together to carry out whole word assignment.In the past in firmware use pointer assignment method, being made in firmware like this, to write meeting more convenient, but can cause the wasting of resources in bus more.As used pointer assignment 4bit " f ", bus can show as " 32 ' hxxxxxxxf ", and remaining idle will be wasted, and will stop above-mentioned waste with whole word output after data preparation, decrease bus operation number of times.
201: the data structure before integration can be position, byte, half-word, and can be discontinuous.
202: the data after integration can output in bus with the form of a whole word.
As shown in Figure 3, realize using for circulation to replace the operation of Switch statement, thus reduce C code cubage.Switch statements all in theory can carry out this and optimize, and the Switch statement line number just had is little, or too complex need not realize or badly realize this optimization.Initialization BD chained list spatial operation carries out the Optimum Operation of for loop statement conversion after debugging is stablized with regard to can be implemented in very much.In practical operation, find that the line number of C code is fewer, compiling " * .hex " file is out also less, and the load time being reacted to firmware in simulation process is also fewer, directly can improve simulation efficiency.
Above-mentioned firmware Optimum Operation is suitable for too in FPGA emulation and actual plate level firmware, and just because FGPA emulation or plate level operate insensitive to the time of firmware operation, it is not very urgent for result in the demand of firmware Optimum Operation.
Claims (3)
1. based on the disposal route that the 802.11n wireless network card chip emulation firmware of SoC framework is optimized, it is characterized in that: the collaborative simulation utilizing firmware realization and verification environment and RTL, emulation and post-simulation work before realizing; CPU starts to call firmware program after completing electrification reset, and firmware is according to the data structure response instruction consulted with verification environment and data, and the self-verifying module finally provided by verification environment completes result and judges and terminate emulation; Firmware is as follows with the flow process in verification environment and RTL collaborative simulation process:
(1) first CPU calls in firmware the boots program collecting and write after electrification reset, completes the configuration to interrupt control register, utilize boots program realize interrupt function link and vector interrupt, non vector interrupt initialization operation; By realizing the operation of removing vector interrupt to the indirect assignment of interrupt control register in vector interrupt operation;
(2) association's data structure is used to complete the assignment operation of interface register, internal register, key list, key information district, MAC Address, BD register, by association's data structure, scattered data structure be integrated together and carry out whole word assignment, the data after integration can output in bus with the form of a whole word;
(3) carrying out in assignment operating process to BD register, using loop statement to replace the code presented in expanded form, using for circulation to replace Switch statement, realize the optimization of code under identical function;
(4) carry out the operation response of interrupt function, realize downlink command, up-downgoing data manipulation;
(5) the operation response backed off after random interrupt function completing this interrupt function carries out waiting for the process of next interrupt function;
(6), complete the inspection of each transmitting and receiving data frame at verification environment after, emulation is stopped.
2. method according to claim 1, it is characterized in that: utilize association's data structure to improve bus data transfer efficiency, reach the object reducing power consumption, when bus carries out data transmission, the data structure that needs operate is integrated, the unified of data is completed to respective stored address and exports.
3. method according to claim 1, it is characterized in that: by association's data structure, scattered data structure is integrated together and carries out whole word assignment, data structure before integration is position or byte or half-word, and be discontinuous or continuous print, the data structure after integration outputs in bus with the form of a whole word.
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| US6848084B1 (en) * | 2002-07-02 | 2005-01-25 | Cadence Design Systems, Inc. | Method and apparatus for verification of memories at multiple abstraction levels |
| CN1818790A (en) * | 2005-02-07 | 2006-08-16 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction for mask pattern during photoetching process |
| CN101344899A (en) * | 2008-08-15 | 2009-01-14 | 炬力集成电路设计有限公司 | Simulation test method and system of on-chip system |
| CN101720466A (en) * | 2007-05-09 | 2010-06-02 | 新思公司 | Techniques for use with automated circuit design and simulations |
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| EP2797239B1 (en) * | 2005-10-28 | 2018-09-05 | Nokia Solutions and Networks Oy | A method and a telecommunication device for selecting a number of code channels and an associated spreading factor for a CDMA transmission |
| CN101047927B (en) * | 2007-04-23 | 2011-11-30 | 北京中星微电子有限公司 | System and method for implementing mobile terminal baseband SOC |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6848084B1 (en) * | 2002-07-02 | 2005-01-25 | Cadence Design Systems, Inc. | Method and apparatus for verification of memories at multiple abstraction levels |
| CN1818790A (en) * | 2005-02-07 | 2006-08-16 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction for mask pattern during photoetching process |
| CN101720466A (en) * | 2007-05-09 | 2010-06-02 | 新思公司 | Techniques for use with automated circuit design and simulations |
| CN101344899A (en) * | 2008-08-15 | 2009-01-14 | 炬力集成电路设计有限公司 | Simulation test method and system of on-chip system |
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