CN102932581B - Image processing circuit and image processing method - Google Patents

Abstract

An image processing circuit and an image processing method. The image processing circuit includes a block matching unit, a multiplexer, an arbitrator and a motion compensation circuit. The block matching unit calculates a high-frequency absolute error sum and a low-frequency absolute error sum according to a current block of a current picture and a reference block of a reference picture. The arbitrator controls the multiplexer to selectively output a high-frequency absolute error sum or a low-frequency absolute error sum according to an arbitration rule, and the arbitration rule is related to the scene characteristics of the current picture. The motion compensation circuit performs motion compensation according to the high-frequency absolute error sum or the low-frequency absolute error sum output by the multiplexer.

Description

Image processing circuit and image processing method

technical field

The invention relates to an image processing circuit and an image processing method, and in particular to an image processing circuit and an image processing method capable of performing motion compensation according to the sum of high-frequency absolute errors or the sum of low-frequency absolute errors.

Background technique

Please refer to FIG. 1 , which is a schematic diagram of a motion estimation and motion compensation device. A motion estimation and motion compensation (MotionEstimateandMotionCompensation, MEMC) device 1 includes a motion estimation engine 11 and a motion compensation circuit 12 . The motion estimation engine 11 performs motion estimation according to the current frame and the reference frame, so that the motion compensation circuit interpolates the compensated frame according to the motion estimation result.

The motion estimation engine 11 includes a block matching unit (BlockMatchingUnit) 111 . The block matching unit (BlockMatchingUnit) 111 will divide the current picture into blocks of equal size, and each block has a corresponding search area in the reference picture. The block matching unit 111 calculates the sum of low-frequency absolute errors between the current block and the reference block to find the block most similar to itself in the search area.

Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 at the same time. FIG. 2 is a schematic diagram of a reference screen, FIG. 3 is a schematic diagram of a current screen, and FIG. 4 is a schematic diagram of an interpolation screen. However, when a flickering scene appears on the playing screen, the block matching unit 111 cannot find out the block most similar to itself according to the low-frequency absolute error sum. For example, the partial area 21 in FIG. 2 and the partial area 31 in FIG. 3 are vehicle lights. Partial area 21 is totally dark, while partial area 31 is fully bright. Since the pixel difference between the local area 31 and the local area 21 is too large, the block matching unit 111 cannot find the block most similar to itself according to the low-frequency absolute error sum. In this way, the motion compensation circuit 12 will interpolate the interpolated frame as shown in FIG. 4 due to the incorrect block comparison of the block matching unit 111 . The local area 41 corresponds to the local area 31 and the local area 21 . However, the shape of the local area 41 is distorted due to incorrect block comparison.

Contents of the invention

The invention relates to an image processing circuit and an image processing method, which can correctly find out the block most similar to itself according to whether the local area is flickering or the object moves, so as to correctly perform motion compensation.

According to the invention, an image processing circuit is proposed. The image processing circuit includes a block matching unit (BlockMatchingUnit), a multiplexer, an arbiter and a motion compensation circuit. The block matching unit calculates a high frequency sum of absolute difference (Sum of Absolute Difference, SAD) and a low frequency sum of absolute difference according to the current block of the current frame and the reference block of the reference frame. The arbiter controls the multiplexer to selectively output the high-frequency absolute error sum or the low-frequency absolute error sum according to an arbitration rule, and the arbitration rule is related to the scene characteristics of the current picture. The movement compensation circuit performs movement compensation according to the high-frequency absolute error sum or the low-frequency absolute error sum output by the multiplexer.

According to the present invention, an image processing method is proposed. The image processing method includes: calculating a high-frequency absolute error sum (Sum of Absolute Difference, SAD) and a low-frequency absolute error sum according to the current block of the current picture and the reference block of the reference picture; selectively outputting the high-frequency absolute error sum or the low-frequency absolute error sum according to arbitration rules The absolute error sum and the arbitration rule are related to the scene characteristics of the current picture; and motion compensation is performed according to the high-frequency absolute error sum or the low-frequency absolute error sum.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of a motion estimation and motion compensation device.

FIG. 2 is a schematic diagram of a reference frame.

FIG. 3 is a schematic diagram of the current screen.

FIG. 4 is a schematic diagram of an interpolation screen.

FIG. 5 is a schematic diagram of an image processing circuit according to the first embodiment.

FIG. 6 is a flow chart of the image processing method according to the first embodiment.

[Description of main component symbols]

10:

1: Motion Estimation and Motion Compensation Device

5: Image processing circuit

11, 51: Motion Estimation Engine

12, 52: Motion Compensation Circuit

21, 31, 41: local area

53: multiplexer

54: Arbiter

61~63: Steps

511, 111: block matching unit

20:

detailed description

first embodiment

Please refer to FIG. 5 and FIG. 6 at the same time. FIG. 5 is a schematic diagram of an image processing circuit according to the first embodiment, and FIG. 6 is a flowchart of an image processing method according to the first embodiment. The image processing circuit 5 includes a motion estimation engine 51 , a motion compensation circuit 52 , a multiplexer 53 and an arbiter 54 , and the motion estimation engine 51 further includes a block matching unit (BlockMatchingUnit) 511 . The image processing method can be applied to the image processing circuit 5 and includes the following steps:

First, as shown in step 61, the block matching unit 511 outputs a high-frequency sum of absolute difference (Sum of Absolute Difference, SAD) AC_SAD and a low-frequency sum of absolute difference DC_SAD according to the current block of the current frame and the reference block of the reference frame. Block matching unit 511 according to the pixel value of the current block and the pixel value of the reference block Compute the low frequency absolute error and DC_SAD. The low frequency absolute error sum (x, y) is the displacement between the current block and the reference block, and a block has N×N pixels.

The sum of high-frequency absolute errors can be calculated in two ways. In the first calculation method, the block matching unit 511 calculates the high-frequency absolute error sum AC_SAD according to the low-frequency absolute error sum DC_SAD and the DC difference value DC _diff . High frequency absolute error sum AC_SAD=|DC_SAD-DC _diff |. The second calculation method is based on the pixel value of the current block by the block matching unit 511 The average pixel value DC _avg1 of the current block, the pixel value of the reference block and the average pixel value DC _avg2 of the reference block to calculate the high-frequency absolute error sum AC_SAD. High frequency absolute error and $\mathrm{AC}\_\mathrm{SAD}=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}\underset{j=0}{\overset{N-1}{\mathrm{\Σ}}}\left|\right|f_{i,j}^t-\mathrm{D.}{C}_{\mathrm{avg}1}|-|f_{i+x,j+\mathrm{the\; y}}^{t-1}-\mathrm{D.}{C}_{\mathrm{avg}2}\left|\right|.$

Next, as shown in step 62, the arbiter 54 controls the multiplexer 53 to selectively output the high-frequency absolute error sum AC_SAD or the low-frequency absolute error sum DC_SAD according to the arbitration rule, which is related to the scene characteristics of the current picture. Then, as shown in step 63 , the motion compensation circuit 52 performs motion compensation according to the high-frequency absolute error sum AC_SAD or the low-frequency absolute error sum DC_SAD output by the multiplexer 53 .

When the local area is flashing, the motion compensation circuit 52 can correctly perform motion compensation according to the high-frequency absolute error and AC_SAD. On the contrary, when the object moves in the local area, the motion compensation circuit 52 can correctly perform motion compensation according to the low-frequency absolute error and DC_SAD. In this way, the moving image processing circuit 5 can correctly perform motion compensation regardless of whether the local area is flickering or the object is moving.

The aforementioned current frame further includes several adjacent blocks adjacent to the current block, and the aforementioned arbitration rules include, for example, an adjacent block arbitration rule. Adjacent block arbitration rule is that if the multiplexer 53 outputs the high-frequency absolute error and AC_SAD corresponding to the adjacent block, then the multiplexer 53 outputs the high-frequency absolute error and AC_SAD corresponding to the current block; if the multiplexer 53 corresponds to the adjacent block The block outputs the low-frequency absolute error and DC_SAD, and the multiplexer 53 outputs the low-frequency absolute error and DC_SAD corresponding to the current block.

second embodiment

The main difference between the second embodiment and the first embodiment is that the arbitration rule of the second embodiment includes a difference arbitration rule. The difference arbitration rule is that if the difference between the high frequency absolute error sum AC_SAD and the low frequency absolute error sum DC_SAD is greater than the difference threshold, the multiplexer 53 outputs the high frequency absolute error sum AC_SAD corresponding to the current block. This is because when the local area flickers, the high-frequency absolute error and AC_SAD are small, while the low-frequency absolute error and DC_SAD are large, so the motion compensation circuit 52 can correctly perform motion compensation according to the high-frequency absolute error and AC_SAD.

On the contrary, the difference arbitration rule is that if the difference between the high-frequency absolute error sum AC_SAD and the low-frequency absolute error sum DC_SAD is not greater than the difference threshold, the multiplexer 53 outputs the low-frequency absolute error sum DC_SAD corresponding to the current block.

This is because when the object moves in the local area, the high-frequency absolute error and AC_SAD are small, and the low-frequency absolute error and DC_SAD are also small, so the motion compensation circuit 52 can correctly perform motion compensation according to the low-frequency absolute error and DC_SAD.

third embodiment

The main difference between the third embodiment and the first embodiment is that the arbitration rule of the third embodiment further includes a difference arbitration rule. The arbiter 51 controls the multiplexer 53 to selectively output the high frequency absolute error sum AC_SAD or the low frequency absolute error sum DC_SAD according to the adjacent block arbitration rule, the adjacent block weight value, the difference arbitration rule and the difference weight value. In other words, the arbiter 51 can control and control the multiplexer 53 to selectively output the high-frequency absolute error and AC_SAD or the low-frequency absolute error and DC_SAD according to a combination of multiple arbitration rules, so that the motion compensation circuit 52 can correctly perform motion compensation .

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. An image processing circuit, comprising: A block matching unit (BlockMatchingUnit), calculating a high-frequency absolute error sum (SumofAbsoluteDifference, SAD) and a low-frequency absolute error sum according to a current block of a current frame and a reference block of a reference frame; a multiplexer; an arbiter, controlling the multiplexer to selectively output the high-frequency absolute error sum or the low-frequency absolute error sum according to an arbitration rule, the arbitration rule being related to the scene characteristics of the current picture; and A motion compensation circuit, performing a motion compensation according to the high-frequency absolute error sum or the low-frequency absolute error sum output by the multiplexer, wherein The arbitration rules include a difference arbitration rule, and the difference arbitration rule is that if the difference between the high-frequency absolute error sum and the low-frequency absolute error sum is greater than a difference threshold, the multiplexer Outputting the high-frequency absolute error sum corresponding to the current block, if the difference between the high-frequency absolute error sum and the low-frequency absolute error sum is not greater than the difference threshold, the multiplexer outputs the current block corresponding to the Low frequency sum of absolute errors. 2. The image processing circuit according to claim 1, wherein the current frame further includes a plurality of adjacent blocks adjacent to the current block, and the arbitration rule further includes an adjacent block arbitration rule, the adjacent blocks The block arbitration rule is that if the multiplexer outputs the high-frequency absolute error sum corresponding to these adjacent blocks, then the multiplexer outputs the high-frequency absolute error sum corresponding to the current block, and if the multiplexer corresponds to these phases The adjacent block outputs the low-frequency absolute error sum, and the multiplexer outputs the low-frequency absolute error sum corresponding to the current block, where The arbiter controls the multiplexer to selectively output the high frequency absolute error and/or the low frequency absolute error according to the adjacent block arbitration rule, a neighboring block weight value, the difference arbitration rule and a difference weight value error sum. 3. The image processing circuit as claimed in claim 1, wherein the block matching unit calculates the low frequency sum of absolute errors according to the pixel values of the current block and the pixel values of the reference block. 4. The image processing circuit as claimed in claim 1, wherein the block matching unit calculates the high-frequency absolute error sum according to the low-frequency absolute error sum and a DC difference value. 5. The image processing circuit according to claim 1, wherein the block matching unit is based on the pixel value of the current block, the average pixel value of the current block, the pixel value of the reference block and the pixel value of the reference block The average pixel value computes the high frequency sum of absolute errors. 6. An image processing method, comprising: calculating a high frequency sum of absolute difference (Sum of Absolute Difference, SAD) and a low frequency sum of absolute difference according to a current block of a current picture and a reference block of a reference picture; selectively outputting the high-frequency absolute error sum or the low-frequency absolute error sum according to an arbitration rule, the arbitration rule being related to the scene characteristics of the current picture; and A motion compensation is performed according to the high-frequency absolute error sum or the low-frequency absolute error sum, wherein The arbitration rules include a difference arbitration rule. If the difference between the high frequency absolute error sum and the low frequency absolute error sum is greater than a difference threshold, the difference arbitration rule corresponding to the current area The block outputs the high-frequency absolute error sum, and if the difference between the high-frequency absolute error sum and the low-frequency absolute error sum is not greater than the difference threshold, then outputs the low-frequency absolute error sum corresponding to the current block. 7. The image processing method according to claim 6, wherein the current frame further includes a plurality of adjacent blocks adjacent to the current block, and the arbitration rule further includes an arbitration rule for adjacent blocks, the adjacent blocks The block arbitration rule is that if the high-frequency absolute error sum is output corresponding to these adjacent blocks, then the high-frequency absolute error sum is output corresponding to the current block; if the low-frequency absolute error sum is output corresponding to these adjacent blocks, then the The current block should output the low-frequency absolute error sum, where The step of selectively outputting the high frequency absolute error sum or the low frequency absolute error sum according to the arbitration rule is based on the adjacent block arbitration rule, a neighboring block weight value, the difference arbitration rule and a difference weight The value selectively outputs the high-frequency absolute error sum or the low-frequency absolute error sum. 8. The image processing method as claimed in claim 6, wherein the calculating step calculates the low-frequency sum of absolute errors according to the pixel values of the current block and the pixel values of the reference block. 9. The image processing method as claimed in claim 6, wherein the calculating step calculates the high frequency absolute error sum according to the low frequency absolute error sum and a DC difference value. 10. The image processing method as claimed in claim 6, wherein the calculation step is based on the pixel value of the current block, the average pixel value of the current block, the pixel value of the reference block and the average pixel value of the reference block The value computes the high frequency sum of absolute errors.