CN102931237B - Structure of perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method thereof - Google Patents

Abstract

The invention provides a structure of a vertical asymmetric ring gate MOSFET device and a manufacturing method thereof. Including the underlying n-type silicon wafer substrate 101, the drain region 111 is located at the lowest end of the device; the drain extension region 106, the channel region 107, and the source region 108 are epitaxially grown on the substrate 101, and the gate oxide layer 109 surrounds the entire channel A polysilicon gate 110 is deposited on the gate oxide layer 109 in the region 107 . The present invention provides a vertical asymmetric gate-around MOSFET structure that can effectively suppress the effect of the short channel effect, and also provides a vertical asymmetric gate-around MOSFET that can simplify the process flow and flexibly control the gate length and the thickness of the silicon body region method.

Description

Structure and Fabrication Method of Vertical Asymmetric Gate-Round MOSFET Device

technical field

The invention relates to a semiconductor device, and the invention also relates to a method for forming the semiconductor device. Specifically, it is a structure of a vertical asymmetric ring gate MOSFET device and a manufacturing method thereof.

Background technique

In recent years, with the rapid development of the semiconductor industry, integrated circuits have developed into very large scale integrated circuits (ULSI) stage. The size of the device is also reduced to the nanometer level, which poses a great challenge for the development of new device structures and fabrication processes. Over the past few decades, the size of MOSFET devices has been continuously reduced, and today the effective channel length of MOSFET devices is less than 10 nanometers. In order to continuously improve the current driving ability and better suppress the short channel effect, MOSFET devices have developed from traditional single-gate planar devices to multi-gate three-dimensional devices. Among all multi-gate devices, the gate-all-around (Gate-All-Around, GAA) device has the best suppression effect on the short channel effect compared with other multi-gate devices. The performance is superior.

The development of nanoscale electronic devices has brought high complexity to the design of integrated circuits, as well as complex photolithography systems and expensive costs. As the feature size of the device continues to decrease, the manufacturing process of the traditional MOSFET device is also limited, so a vertical MOSFET device is developed to replace the traditional device. In this device the current direction flows vertically from the drain to the source. It not only simplifies the lithographic technique for defining the channel region, but also maintains compatibility with standard processes. More importantly, since the active region is located on the side of the silicon body, it is easier to form double-gate or gate-around structures than planar devices. Therefore, the short channel effect can be suppressed and the current driving force can be enhanced.

However, when the channel length is reduced below 50 nanometers, vertical MOSFET devices will face a serious problem: in order to suppress the short channel effect, the channel doping concentration must be very high (up to 7.0×10 ¹⁸ cm ^-3 ), which will lead to a large junction leakage current and reduce the channel carrier mobility. After adopting the traditional symmetric LDD (Lightly Doped Drain) structure, although the channel doping concentration can be reduced to 3.5×10 ¹⁸ cm ^-3 , this is still unacceptable in devices with a channel length less than 50 nanometers. In order to solve these problems, MOSFET devices with asymmetric LDD vertical structure are proposed. Compared with the symmetrical LDD structure, the asymmetric LDD structure has the advantages of reducing the off-leakage current, reducing the electric field near the drain junction, suppressing the short channel effect and reducing the source terminal series resistance. Compatible with the planar CMOS process in the manufacturing process, it is easy to implement.

In order to solve the problems caused by the reduction of device size, MOSFET devices with graded channel doping have been studied. Through the gradual change of the doping concentration of the channel region, the tangential electric field intensity at the source end is increased, so a high carrier velocity is obtained and the short channel effect is suppressed. But in traditional planar MOSFET devices, in order to obtain asymmetric channel doping, large-angle-tilt implants and complex photolithography processes must be used. Therefore, a MOSFET device with a vertical structure with gradient channel doping has been studied, which is not only compatible with the traditional CMOS manufacturing process in terms of manufacturing process, but also has a good ability to suppress short channel effects. There are many nanoscale device structures that have been proposed now, and devices similar to the present invention include vertical asymmetric double-gate MOSFET devices and vertical ring-gate MOSFET devices. Compared with the device structure proposed by the present invention, the above two devices respectively have the disadvantages of insufficient gate control capability and excessive leakage current.

Contents of the invention

The object of the present invention is to provide a vertical asymmetric ring-gate MOSFET structure that effectively suppresses the effect of the short channel effect. The object of the present invention is also to provide a method for manufacturing a vertical asymmetric ring gate MOSFET which can simplify the process flow and flexibly control the gate length and the thickness of the silicon body region.

The purpose of the present invention is achieved like this:

The structure of the vertical asymmetric gate-around MOSFET device is as follows: it includes the underlying n-type silicon wafer substrate 101, the drain region 111 is located at the lowest end of the device; the drain extension region 106 is epitaxially grown on the n-type silicon wafer substrate 101, and the channel region 107, and source region 108, a gate oxide layer 109 surrounds the entire channel region 107, and a polysilicon gate 110 is deposited on the gate oxide layer 109.

The drain extension region 106 is n-doped; the channel region 107 is p-type doped; the source region 108 and the drain region 111 are n+ doped, and the doping concentration is 1×10 ¹⁸ to 1×10 ¹⁹ cm ^-3 .

The channel length of the channel region 107 is 10-20 nm.

The channel region 107 is in the shape of a cylinder, and the polysilicon gate 110 and the gate oxide layer 109 are in the shape of a ring.

The fabrication method of the vertical asymmetric ring gate MOSFET device comprises the following steps:

Step 1. Prepare an n-type silicon wafer substrate 101 with crystal orientation <100>;

Step 2, depositing a layer of SiO ₂ layer 102, SiGe layer 103, and SiO ₂ layer 104 sequentially on the n-type silicon wafer substrate 101;

Step 3, the _SiO2 layer 102, the SiGe layer 103, and the _SiO2 layer 104 grown by photolithography deposition, so that the _SiO2 layer 102 in the middle part, the SiGe layer 103 and the _SiO2 layer 104 are all etched away to form a window, Using the photoresist as a mask layer, ion implantation is performed on the device to form the drain region 111, and the impurity is activated by rapid thermal annealing after the ion implantation;

Step 4, epitaxially growing the epitaxial silicon layer 105 on the n-type silicon wafer substrate 101, and performing n-diffusion doping during the epitaxial growth;

Step 5, using the SiO ₂ layer 104 as a stop layer, performing chemical mechanical polishing on the epitaxial silicon layer 105;

Step 6. First perform low-energy ion implantation on the device to form a p-type body region; then perform high-energy ion implantation to form an n+-type source region, and perform rapid thermal annealing to activate impurities after ion implantation;

Step 7, after the ion implantation, form the source region 108, the channel region 107 and the drain extension region 106 sequentially from top to bottom in the silicon epitaxial layer region, and use SiGe and _SiO2 in the different selectivity ratios in the etchant to perform selective etching, and then growing a layer of SiO ₂ by thermal oxidation on the corroded area as gate oxide layer 109;

Step 8: Etching the unetched SiO ₂ layer, depositing a layer of polysilicon gate 110 outside the gate oxide layer, performing n+ type doping implantation on the polysilicon gate 110, and rapidly annealing to activate impurities.

The main features of the method of the present invention are as follows:

1) A ring gate structure is adopted, and the gate surrounds the entire channel region; 2) A vertical channel structure is adopted, and the gate length can be flexibly controlled by changing the thickness of the SiGe layer; 3) An asymmetric LDD structure is adopted to reduce the electric field near the drain junction; 4) Using the gate-last process, self-aligned doping is first performed to form the source region, channel region and drain region, and then the gate electrode is fabricated. Since the formation of the source region, channel region and drain region requires a series of high-temperature treatment steps, such as ion implantation and annealing, the gate oxide in the gate-last process avoids the influence of external factors such as temperature, making the device performance better; 5) Through an easy-to-control etching process, the thickness of the silicon body region can be flexibly controlled to make it easy to achieve full depletion and enhance gate control capabilities.

Description of drawings

Fig. 1 is a schematic cross-sectional view of a vertical asymmetric gate-around MOSFET device disclosed by the present invention;

Fig. 2 prepares the schematic diagram of silicon wafer;

Fig. 3 is a cross-sectional view of the structure in Fig. 2 after depositing a layer of SiO ₂ , SiGe, and SiO ₂ in sequence;

Fig. 4 is a schematic diagram of etching and ion implantation of the structure of Fig. 3;

Fig. 5 is a cross-sectional view of the structure of Fig. 4 after epitaxial silicon material and n-doping;

Fig. 6 is a cross-sectional view of the structure of Fig. 5 after chemical mechanical polishing;

Fig. 7 is a schematic diagram of high and low energy ion implantation in the structure of Fig. 6;

Figure 8 is a cross-sectional view of _SiO2 and SiGe layers in the structure of Figure 7 after selective etching and thermal growth of _SiO2 ;

FIG. 9 is a cross-sectional view of the structure of FIG. 8 after etching unetched SiO ₂ and polysilicon deposition thermally grown SiO ₂ .

Detailed ways

The present invention is described in detail below in conjunction with accompanying drawing example:

Specific embodiment one:

Combined with Figure 2. As shown, an n-type silicon wafer substrate 101 with crystal orientation <100> is prepared with a thickness of 100 nm.

Combined with Figure 3. On an n-type silicon wafer 101, a SiO ₂ layer 102, a SiGe layer 103 and a SiO ₂ layer 104 are sequentially deposited. The thicknesses of the SiO ₂ layer 102, the SiGe layer 103 and the SiO ₂ layer 104 are all 20-50 nm.

Combined with Figure 4. Photolithography is performed on the structure in FIG. 3, so that the SiO ₂ layer 102, SiGe layer 103 and SiO ₂ layer 104 in the middle part are all etched away to form windows. Then, the photoresist is used as a doping mask layer to perform n-type doping implantation on the silicon material, and rapid thermal annealing (RTA) activates the impurities to form the drain region 111 .

Combined with Figure 5. The epitaxial silicon layer 105 is epitaxial on the silicon material, and the thickness of the epitaxial silicon layer 105 is 200-300nm. At the same time, n-diffusion doping is performed during the epitaxial growth to form a drain extension region LDD.

Combined with Figure 6. With the SiO ₂ layer 104 as a stop layer, chemical mechanical polishing (CMP) is performed on the epitaxial silicon layer 105 .

Combined with Figure 7. Using the SiO ₂ layer 104 as a mask layer, low-energy boron ion implantation is first performed to form a p-type channel region; then high-energy arsenic ion implantation is performed to form an n+ source region. Rapid thermal annealing is then performed to activate the impurities.

Combined with Figure 8. After the ion implantation, a source region 108 , a channel region 107 and a drain extension region 106 are sequentially formed in the silicon epitaxial layer region from top to bottom. Among them, the doping type and concentration of the source region 108 and the drain region 111 are the same, both are n+ doped, and the concentration is 1×10 ¹⁸ ~ 1×10 ¹⁹ cm ^-3 ; the drain extension region 106 is n- doped; the channel Region 107 is doped p-type. Since in a certain etchant, the corrosion rate of SiGe is much higher than that of _SiO2 , so the selection ratio of _SiO2 and SiGe in this etchant is different, for _SiO2 layer 102, SiGe layer 103 and _SiO2 layer 104 Selective etching is performed, and a thin SiO ₂ layer 109 is grown by thermal oxidation at the etched SiGe layer 103 as a gate oxide layer.

Combined with Figure 9. The SiO ₂ layer 102 and the SiO ₂ layer 104 are etched away, and a layer of polysilicon material 110 is deposited outside the gate oxide layer 109 as a gate material. The polysilicon material is implanted with n+ type doping, and the impurity is activated by rapid annealing.

The advantages of Embodiment 1 are: 1) the gate-around structure is adopted, and the effective number of gates is the largest, so the gate has the strongest electrical control over the channel, which can minimize the short channel effect; 2) the vertical channel is adopted structure, without resorting to complex lithography means to define the channel length, not limited by lithography accuracy, and the working principle and characteristics are almost the same as those of planar devices; 3) Adopting an asymmetric LDD structure, which can It has the advantages of reducing the cut-off leakage current, reducing the electric field near the drain junction, suppressing the short channel effect and reducing the series resistance of the source terminal. The manufacturing process is compatible with the planar CMOS process and is easy to implement; 4) Using the gate-last process, first perform self-aligned doping to form the source region, channel region and drain region, and then make the gate electrode. Since the formation of the source region, channel region and drain region requires a series of high-temperature treatment steps, such as ion implantation and annealing, the gate oxide in the gate-last process avoids the influence of external factors such as temperature, making the device performance better; 5) Through an easy-to-control etching process, the thickness of the silicon body region can be flexibly controlled. In the actual production process, the sacrificial oxide layer should be over-etched as much as possible, so that the channel region can be easily fully depleted and the gate control capability can be enhanced.

Specific embodiment two:

Other described steps are the same as the specific embodiment one.

Combined with Figure 7. Using the SiO ₂ layer 104 as a mask layer, first perform low-energy ion implantation with an implantation energy of 20keV and a dose of boron ions at a dose of 5×10 ¹³ cm ^-2 to form a graded channel; then perform high-energy ion implantation with an implantation energy of 20keV, Arsenic ions with a dose of 2×10 ¹⁵ cm ^-2 to form the source region. Rapid thermal annealing is then performed to activate the impurities. The doping concentration of the graded channel region 107 gradually decreases from the source end to the drain end, and is 2×10 ¹⁸ -8×10 ¹⁷ cm ⁻³ .

The second embodiment has all the advantages of the first embodiment, and the doping concentration of the channel region is gradually changed, which increases the tangential electric field intensity at the source end, thereby obtaining a high carrier velocity and suppressing the short channel effect.

The two specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be noted that the above descriptions are only specific embodiments of the present invention and do not limit the present invention. , all adjustments and optimizations made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (1)

1. the manufacture method of vertical asymmetric surrounding-gate MOSFET device, is characterized in that comprising the following steps:

Step 1, preparation crystal orientation are the N-shaped silicon wafer substrate (101) of <100>;

Step 2, in N-shaped silicon wafer substrate (101) deposit one deck SiO successively ₂layer (102), SiGe layer (103), and SiO ₂layer (104);

The SiO of step 3, photoetching deposit growth ₂layer (102), SiGe layer (103), and SiO ₂layer (104), makes the SiO of mid portion ₂layer (102), SiGe layer (103) and SiO ₂layer (104) is all etched away, and forming window, take photoresist as masking layer, carries out ion implantation form drain region (111), rapid thermal annealing activator impurity after ion implantation to device;

Step 4, at N-shaped silicon wafer substrate (101) Epitaxial growth silicon epitaxial layers (105), simultaneously in epitaxial growth, carry out n-diffusing, doping;

Step 5, with SiO ₂layer (104) is stop-layer, carries out chemico-mechanical polishing to silicon epitaxial layers (105);

Step 6, first low energy ion beam implantation is carried out to device, form p-type body district; Then carry out energetic ion injection, form n+ type source region, after ion implantation, carry out rapid thermal annealing activator impurity;

Form source region (108) from top to bottom successively in silicon epitaxy layer region after step 7, ion implantation, channel region (107) and leakage expansion area (106), utilize SiGe and SiO ₂selection radio in corrosive agent is different, carries out selective corrosion, then thermal oxide growth one deck SiO on the region be corroded ₂, as gate oxide (109);

Step 8, to the SiO be not corroded ₂layer etches, then at gate oxide (109) outside deposit one deck polysilicon gate (110), and n+ type doping injection is carried out to polysilicon gate (110), short annealing activator impurity, finally obtains vertical asymmetric surrounding-gate MOSFET device.