CN102929194B - Asynchronous multi-core programmable automation controller (PAC) - Google Patents

Abstract

The invention discloses an asynchronous multi-core programmable automation controller, which includes an analog main board, an I/O main board, a motion control main board, a diagnose module, a synchronous debugger, a self-defined enhanced SPI bus, and a power supply communication device and a synchronous debugging bus. Bottom board; three main boards are installed on the bottom board with power supply communication device and synchronous debugging bus through pins; three main boards are respectively connected through self-defined enhanced SPI bus; three main boards are respectively connected to the diagnostic module, and the diagnostic module is connected to the PC connected; the five sub-boards are installed on their corresponding main boards; the synchronous debugger is connected to the PC and the three main boards respectively. The automation controller works asynchronously through multi-core, which effectively solves the problems of difficulty in increasing the clock frequency of single-core processors and high power consumption of microprocessors. off to a good start.

Description

Asynchronous multi-core programmable automation controller

technical field

The invention belongs to the field of industrial automation control, in particular to a programmable automation controller (PAC), in particular to an asynchronous multi-core programmable automation controller. the

Background technique

With the increasing demand for industrial control equipment, it is increasingly difficult for the current control system to meet the more functional requirements of modern industrial applications. In order to meet the requirements of modern industrial control system applications, people have proposed programmable automation Controller (PAC), Programmable Automation Controller (PAC) is gradually replacing Programmable Logic Controller (PLC), becoming an ideal choice for industrial control systems. However, at present, most PACs still use the single microprocessor (MCU) mode used by PLC, which makes the load on the control system very high, which easily leads to real-time problems in multi-tasking systems. Therefore, in order to meet the performance requirements, through Integrating more cores to improve performance is an inevitable choice, but the core structure must also be considered, because if the core structure is too complex, as the number of cores increases, not only will the performance not be improved, but the line delay will increase and power consumption will increase. Therefore, heterogeneous multi-core is an important direction, integrating multiple cores with different structures, power consumption, functions, and computing performance on the chip, and assigning different tasks to different cores through task division and division , so that each core handles the tasks that it is good at. This heterogeneous organization is more efficient than homogeneous multi-core processors to perform tasks, realizes the optimal allocation of resources, and reduces the overall power consumption. The heterogeneous multi-core programmable automation controller will replace the single-core processor and solve the development bottleneck of the microprocessor. It is an inevitable development trend of the industrial control system in the future. Therefore, it is of great practical significance to study a heterogeneous multi-core programmable automation controller for industrial control systems. However, the current common multi-core controller integrates multiple cores in an integrated chip (IC). In addition, in a heterogeneous multi-core system, the OS is still used for task scheduling, so that the stability and security of the entire system are built on the OS, and a single hardware MCU also causes the lack of redundancy of the entire system. the

Contents of the invention

In view of the defects or deficiencies in the above-mentioned programmable logic controller, the purpose of the present invention is to propose an asynchronous multi-core programmable automation controller, which effectively solves the difficulty of increasing the clock frequency of a single-core processor through multi-core asynchronous work. , The problem of high power consumption of the microprocessor. And it provides a good start for solving the security, stability of the control system, reducing the difficulty of software development and so on. the

In order to achieve the above object, the present invention adopts the following technical solutions:

An asynchronous multi-core programmable automation controller, including an analog main board, an I/O main board, a motion control main board, a diagnose module, a synchronous debugger, a custom enhanced SPI bus, a base board with a power supply communication device and a synchronous debugging bus; an analog main board The three main boards, the I/O main board and the motion control main board, are installed on the base plate with a power supply communication device and a synchronous debugging bus through pins; the three main boards are connected to each other through a self-defined enhanced SPI bus; the three Main board is connected with diagnose module respectively, and described diagnose module is logic analyzer level signal acquisition circuit, in order to realize the level signal acquisition on three main boards, and described diagnose module is connected with PC, in order to realize three Mainboard level signal display; the synchronous debugger is connected to the PC and the three mainboards respectively to realize the synchronous debugging of the three mainboards.

The present invention also includes following other technical features:

The controller also includes five sub-boards (7), and the five sub-boards (7) are installed on their corresponding main boards to expand the functions of the three main boards respectively; the five sub-boards include DAC interface expansion circuit, ADC interface expansion circuit, I/O interface expansion circuit, stepper motor control interface expansion circuit and encoder interface expansion circuit, wherein, the DAC interface expansion circuit and ADC interface expansion circuit are connected with the analog motherboard; The O interface expansion circuit is connected with the I/O main board; the stepper motor control interface expansion circuit and the encoder interface expansion circuit are connected with the motion control main board.

The self-defined enhanced SPI bus includes 12 signal lines, which are: data lines and clock lines: including SPI_SCK, SPI_MISO, SPI_MOSI; chip select signal lines: including NSS0, NSS1, NSS2, NSS3, SPI_NSS; interrupt signal lines: Including IT0, IT1, IT2, IT3. the

The synchronous debugger includes a USB interface, an STM32 chip and an STM8SL05 chip. Among them, the USB interface, the STM32 chip and the STM8SL05 chip are connected in turn; the UART1 on the STM32 chip and the 5 GPIO lines on the STM8SL05 chip and the GND line together form a synchronous debugger interface Debugger1; the UART2 on the STM32 chip and the STM8SL05 chip The 5 GPIO lines and the GND line together form the synchronous debugger interface Debugger2; the UART3 on the STM32 chip and the 5 GPIO lines on the STM8SL05 chip and the GND line together form the synchronous debugger interface Debugger3; the 5 GPIO lines on the STM8SL05 chip Line, GND line and UART together form the debugger interface Debugger4; Debugger1, Debugger2, Debugger3 are respectively connected to the download debugging interface JTAG on the three motherboards; the PC is connected to the synchronous debugger through the USB interface, and the PC is The synchronous debugger interfaces Debugger1, Debugger2, and Debugger3 are respectively connected to the downloading and debugging interfaces JTAG on the three main boards. the

The advantage of asynchronous multi-core programmable automation controller of the present invention is as follows:

1. Each main board has a microcontroller MCU with different operating frequency or the same frequency, which is a concrete embodiment of the multi-core structure and asynchronous work of the present invention. The same interface communication modules as the field bus supporting distributed control or real-time control, RS485 interface, USB serial communication, download debugging interface JTAG, universal serial data bus UART and SPI bus interface for asynchronous communication, and their own functions module. In this way, each motherboard can work independently and asynchronously. For example, if only the analog motherboard is used in the work process, it is only necessary to use the Diagnose module to collect and analyze the signals in the analog motherboard. Therefore, only the analog motherboard can be selected to work through software programming to meet the needs of the control work, without the need for all three motherboards to be invested. Work, reduce power consumption, improve the execution efficiency and system security of the automation controller. The above are the advantages of asynchronous multi-core.

2. Three main boards and a synchronous debugger constitute a self-organizing reconfiguration system, which makes the asynchronous multi-core programmable automation controller of the present invention have reconfigurability and programmability, greatly improves multi-core versatility and computing performance, and enables The processor not only has the versatility of a general-purpose microprocessor, but also has the high performance of a single multi-core chip system, and has the advantages of flexibility, high performance, high reliability, and low energy consumption. The above are the advantages of the self-organizing reconstruction system. the

3. The self-defined enhanced SPI bus overcomes the shortcomings of the existing SPI bus that can only communicate in one direction. The three main boards form a whole through the enhanced SPI bus to realize mutual communication with each other. During the working process, the slave can interrupt the signal of the master by interrupting the signal line, and set itself as the master, so that the three main boards can be the master or the slave of each other, and at any time only one main board is the master, and the other main boards only It can be used as a slave, and the responsive communication connection between the master and the slave is realized through the interrupt signal line. the

4. The backplane with the power supply communication device and the synchronous debugging bus is an indispensable part of the present invention, mainly composed of the power supply device and the synchronous debugging bus. The five sub-boards are installed on the three main boards through the pins according to their corresponding expansion interfaces, and the three main boards are installed on the bottom board with the power supply communication device and the synchronous debugging bus through the pins; when necessary, the synchronous debugger and the three main boards connected, the synchronous debugger exists independently when not needed. Power is supplied to the three main boards through the power supply device on the bottom board, so as to realize the mutual connection and communication among the three main boards, five sub-boards and the synchronous debugger. the

Description of drawings

Fig. 1 is a schematic structural diagram of an asynchronous multi-core programmable automation controller of the present invention. The labels in the figure: 1. Analog main board; 2. I/O main board; 3. Motion control main board; 4. Diagnose module; 5. Synchronous debugger; 6. Custom enhanced SPI bus; 7. Five sub-boards. the

FIG. 2 is a schematic diagram of the structure of the analog motherboard. Each label in the figure: 8, field bus CAN; 9, RS485 interface; 10, USB serial port; 11, download debugging interface JTAG; 12, universal serial data bus UART; 13, ADC analog acquisition front-end conditioning circuit; 14, D/ A circuit; 15. Analog motherboard MCU; 16. A/D circuit; 17. DAC digital back-end conditioning circuit; 18. 24 rows of terminals; 19. 2803 chip; 20. Relay output circuit; 22. Isolated digital input and output circuits; 23. Custom enhanced SPI terminals; 24. Communication terminals during configuration. the

FIG. 3 is a schematic structural diagram of an I/O main board. Each label in the figure: 25, field bus (CAN); 26, RS485 interface; 27, USB serial port; 28, download debugging interface JTAG; 29, universal serial data bus UART; 30, configuration communication terminal interface; 31, external Expand 24 pins; 32. I/O motherboard MCU; 33. 4245 chip; 34. Input optocoupler signal isolation circuit; 35. Input terminal; 36. 4245 chip; 37. Output optocoupler signal isolation circuit; 38. Output terminal ; 39, 24 terminal blocks; 40, custom enhanced SPI terminals; 41, power terminals. the

FIG. 4 is a schematic structural diagram of the motion control main board. Each label in the figure: 42, field bus (CAN); 43, RS485 interface; 44, USB serial port; 45, download debugging interface JTAG; 46, universal serial data bus UART; 47, configuration communication terminal interface; 48, external Expand 24 pins; 49, motion control mainboard MCU; 50, 4245 chip; 51, optocoupler signal isolation circuit; 52, single-ended to differential; 53, 4245 chip; 54, optocoupler signal isolation circuit; ; 56, custom enhanced SPI terminals. the

FIG. 5 is a schematic diagram of connections between three main boards and five sub-boards. Each label in the figure: 2. I/O main board; 1. Analog main board; 6. Custom enhanced SPI bus; 3. Motion control main board; 57. DAC interface expansion circuit; 58. ADC interface expansion circuit; 59. I/O O main board interface expansion circuit; 60, stepping motor control interface expansion circuit; 61, encoder interface expansion circuit. the

Fig. 6 is a schematic diagram of connection between three motherboards through a custom enhanced SPI bus. Each label in the figure is: 6, enhanced SPI bus, 23, enhanced SPI connection terminal of analog main board 1; 40, enhanced SPI connection terminal of I/O main board 2; 56, enhanced SPI connection of motion control main board 3 terminals. the

FIG. 7 is a schematic structural diagram of a synchronous debugger. Each label in the figure: 62, USB interface; 63, STM32; 64, STM32L05. the

The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments. the

Detailed ways

Referring to Fig. 1, the present invention is an asynchronous multi-core programmable automation controller, comprising an analog main board 1, an I/O main board 2, a motion control main board 3, a Diagnose module 4, a synchronous debugger 5, a self-defined enhanced SPI bus 6, and five Sub-board 7 and the bottom board with power supply communication device and synchronous debugging bus;

The analog main board 1, the I/O main board 2 and the motion control main board 3 are installed on the bottom board with the power supply communication device and the synchronous debugging bus through pins, and the three main boards are connected through the power supply device on the bottom board with the power supply communication device and the synchronous debugging bus. powered by.

The analog main board 1, the I/O main board 2 and the motion control main board 3 are connected through a custom enhanced SPI bus 6, and the three main boards are of the same level, and the mutual interrupt response between the master and the slave is realized through the custom enhanced SPI bus 6 communication connection, but at any time during the operation, only one main board acts as the master, and the other main boards act as slaves. The analog main board 1 is used to convert the collected digital signal into an analog voltage signal through DAC, and convert the output voltage from 0 to 2.5V to plus or minus 10V through the back channel circuit, which is used for servo motor analog control. The I/O main board 2 is used for input and output of various switch values of the controller. The motion control main board 3 is used to realize the control of the stepping motor and the input of special signals (origin signal, input of exclusive signals such as positive limit and negative limit). the

These three main boards of described analog main board 1, I/O main board 2 and motion control main board 3 are connected with diagnose module 4 respectively; Level signal acquisition. The diagnose module 4 can be connected with a PC, and the collected level signal can be displayed on the PC. the

The three main boards and the synchronous debugger 5 constitute a self-organizing reconfiguration system, so that the controller of the present invention has reconfigurability and programmability, and improves multi-core versatility and computing performance. Self-organizing reconstruction system is the core component of the present invention; Diagnose module 4, self-defined enhanced SPI bus 6 and five sub-boards 7 are auxiliary modules, which are used to meet the requirements of connection, communication, interface expansion and level signal collection. the

Referring to Fig. 2, the analog motherboard 1 includes a field bus 8, an RS485 interface 9, a USB serial port 10, a download debugging interface JTAG 11, a universal serial data bus UART 12, an ADC analog acquisition front-end conditioning circuit 13, a D/A circuit 14, Analog motherboard MCU 15, A/D circuit 16, DAC digital back-end conditioning circuit 17, 24 rows of terminals 18, 2803 chip 19, relay output circuit 20, external expansion 24 pins 21, isolated digital input and output circuit 22, custom enhancement Type SPI connection terminal 23 and communication terminal 24 during configuration (the three main boards are put together, the overall work is configuration, and the overall work is communicated through the configuration communication terminal 24; each individual main board is in an independent state when working, When it works independently, it communicates through an independent communication terminal); wherein, the field bus 8, RS485 interface 9, USB serial port 10, download debugging interface JTAG 11, universal serial data bus UART 12, D/A circuit 14, A/D circuit 16, 2803 chip 19, external expansion 24 pins 21, isolated digital input and output circuit 22, self-defined enhanced SPI connection terminal 23 and communication terminal 24 are connected with analog motherboard MCU 15 respectively during configuration; A/D circuit 16, DAC digital rear-end conditioning circuit 17, 24 rows of terminals 18, ADC analog acquisition front-end conditioning circuit 13 and D/A circuit 14 are connected in sequence; the 2803 chip 19 is connected with the relay output circuit 20. the

Referring to Fig. 3, described I/O main board 2 comprises field bus 25, RS485 interface 26, USB serial port 27, download debugging interface JTAG28, universal serial data bus UART29, configuration communication terminal interface 30, external expansion 24 pins 31, I/O motherboard MCU 32, 4245 chip 33, input optocoupler signal isolation circuit 34, input terminal 35, 4245 chip 36, output optocoupler signal isolation circuit 37, output terminal 38, 24 terminal row 39, custom enhanced SPI wiring Terminal 40 and power supply terminal 41; Wherein, described field bus 25, RS485 interface 26, USB serial port 27, download debugging interface JTAG28, universal serial data bus UART29, configuration communication terminal interface 30, external expansion 24 pins 31,4245 Chip 33, 4245 chip 36, 24 terminal row 39, self-defined enhanced SPI connection terminal 40, power supply terminal 41 are connected with I/O motherboard MCU 32 respectively; Described input terminal 35, input optocoupler signal isolation circuit 34 and 4245 The chips 33 are connected in sequence; the 4245 chip 36, the output optocoupler signal isolation circuit 37, and the output terminal 38 are connected in sequence. the

Referring to Fig. 4, described motion control main board 3 comprises field bus 42, RS485 interface 43, USB serial port 44, download debugging interface JTAG 45, universal serial data bus UART 46, configuration communication terminal interface 47, external expansion 24 pins 48 , motion control mainboard MCU 49, 4245 chip 50, optocoupler signal isolation circuit 51, single-ended to differential conversion 52, 4245 chip 53, optocoupler signal isolation circuit 54, 24 terminal row 55 and custom enhanced SPI terminal 56; , the field bus 42, RS485 interface 43, USB serial port 44, download debugging interface JTAG 45, universal serial data bus UART 46, configuration communication terminal interface 47, external expansion 24 pins 48, 4245 chip 50, 4245 chip 53 , 24 terminal blocks 55 and self-defined enhanced SPI connection terminals 56 are connected to the motion control main board MCU 49 respectively; the 4245 chip 50, the optocoupler signal isolation circuit 51 and the single-ended to differential circuit 52 are connected successively; the 4245 chip 53 is connected to the optocoupler signal isolation circuit 54; the single-ended to differential circuit 52 and the optocoupler signal isolation circuit 54 are respectively connected to the 24 terminal block 55. the

Referring to FIG. 5 , the five sub-boards 7 include a DAC interface expansion circuit 57 , an ADC interface expansion circuit 58 , an I/O interface expansion circuit 59 , a stepper motor control interface expansion circuit 60 and an encoder interface expansion circuit 61 . The five sub-boards are respectively the interface expansion circuits of the three main boards, which realize the interface expansion of the three main boards and are used to connect and control more external devices. Wherein, the DAC interface expansion circuit 57 and the ADC interface expansion circuit 58 are installed on the analog main board 1 through pins, as the expansion interface of the analog main board 1;

I/O interface expansion circuit 59 is installed on the I/O main board 2 by pin, as the expansion interface of I/O main board 2; Stepper motor control interface expansion circuit 60 and encoder interface expansion circuit 61 are installed on motion by pin On the control board 3, it serves as an expansion interface of the motion control board 3.

Referring to Fig. 6, the self-defined enhanced SPI bus 6 includes 12 signal lines, which are data lines and clock lines (including SPI_SCK, SPI_MISO, SPI_MOSI), chip select signal lines (including NSS0, NSS1, NSS2, NSS3, SPI_NSS ) and interrupt signal lines (including IT0, IT1, IT2, IT3), among which, the data line and clock line are used for signal communication between the slave and the host, and the chip select signal line is used for the host to select the slave through this signal line, The interrupt signal line is used for the slave to send an interrupt signal to the host, thereby interrupting the signal of the host, and setting itself as the host, and the others as slaves, so as to realize the responsive communication connection between the host and the slave interrupting each other, which is also compatible with the existing SPI The difference between the bus. The custom enhanced SPI bus 6 has 4 more interrupt signal lines and 4 chip select signal lines than the traditional SPI bus. the

The self-defined enhanced SPI connection terminal 23 of the analog main board 1, the self-defined enhanced SPI connection terminal 40 of the I/O main board 2, the self-defined enhanced SPI connection terminal 56 of the motion control main board 3 through the self-defined enhanced SPI bus The 12 signal lines of 6 are connected. The custom enhanced SPI terminal blocks meet the installation requirements of the custom enhanced SPI bus 6. the

Referring to FIG. 7 , the synchronous debugger 5 mainly includes a USB interface 62 , an STM32 chip 63 and an STM8SL05 chip 64 . Among them, the USB interface 62, the STM32 chip 63 and the STM8SL05 chip 64 are connected in turn; the UART1 on the STM32 chip 63 and the five GPIO lines on the STM8SL05 chip 64 and the GND line together form a synchronous debugger interface Debugger1; The UART2 on the STM8SL05 chip 64 and the five GPIO lines on the STM8SL05 chip 64 and the GND line together form the synchronous debugger interface Debugger2; the UART3 on the STM32 chip 63 and the five GPIO lines on the STM8SL05 chip 64 and the GND line together form the synchronous debugger interface Debugger3 ; 5 GPIO lines, GND lines and UART on the STM8SL05 chip 64 form a synchronous debugger interface Debugger4. the

The synchronous debugger interfaces Debugger1, Debugger2, and Debugger3 are respectively connected to the download debugging interface JIAG on the three motherboards, and the PC is connected to the USB interface 62 of the synchronous debugger 5, and transmits data to the STM32 chip 63 and the STM8SL05 chip 64 through the USB interface 78 . Therefore, the PC is respectively connected to the download and debugging interface JIAG on the three main boards through the Debugger1, Debugger2 and Debugger3 on the synchronous debugger 5 to realize the synchronous debugging of the three main boards. When downloading and debugging is required, the synchronous debugger (5) is connected to the three main boards, and when not needed, the synchronous debugger (5) can exist independently. the

Synchronous debugger interface Debugger4 is an additional synchronous debugging interface, which is used for the expansion of the mainboard. the

Claims (4)

1. an asynchronous multinuclear automation controller able to programme, it is characterized in that, comprise the base plate of simulating mainboard (1), I/O mainboard (2), motion control mainboard (3), diagnose module (4), synchronous debugging device (5), self-defined Enhanced SPI bus (6), thering is power supply communication device and synchronous debugging bus; Simulation mainboard (1), I/O mainboard (2) and these three mainboards of motion control mainboard (3) are arranged on the base plate with power supply communication device and synchronous debugging bus by contact pin; Described three mainboards interconnect by self-defined Enhanced SPI bus (6) respectively; Described three mainboards are connected with diagnose module (4) respectively, described diagnose module (4) is logic analyser level signal Acquisition Circuit, in order to realize three level signal collections on mainboard, described diagnose module (4) is connected with PC, in order to realize the demonstration to three mainboard level signals; Synchronous debugging device (5) is connected respectively with PC, three mainboards, in order to realize the synchronous debugging of three mainboards.

2. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, also includes five daughter boards (7), and described five daughter boards (7) are arranged on its corresponding mainboard, in order to three mainboards are carried out respectively to Function Extension; Described five daughter boards (7) comprise DAC Interface Expanding circuit (57), ADC Interface Expanding circuit (58), I/O Interface Expanding circuit (59), step motor control Interface Expanding circuit (60) and encoder interfaces expanded circuit (61), wherein, DAC Interface Expanding circuit (57) is connected with simulation mainboard (1) with ADC Interface Expanding circuit (58); I/O Interface Expanding circuit (59) is connected with I/O mainboard (2); Step motor control Interface Expanding circuit (60) is connected with motion control mainboard (3) with encoder interfaces expanded circuit (61).

3. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, described self-defined Enhanced SPI bus (6) comprises 12 signal line, respectively: data line and clock line: comprise SPI_SCK, SPI_MISO, SPI_MOSI; Chip selection signal line: comprise NSS0, NSS1, NSS2, NSS3, SPI_NSS; Look-at-me line: comprise IT0, IT1, IT2, IT3.

4. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, described synchronous debugging device (5) comprises USB interface (62), STM32 chip (63) and STM8SL05 chip (64); Wherein, USB interface (62), STM32 chip (63) and STM8SL05 chip (64) are connected successively; By 5 GPIO lines on the UART1 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger1; By 5 GPIO lines on the UART2 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger2; By 5 GPIO lines on the UART3 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger3; By 5 GPIO lines, GND line and UART on STM8SL05 chip (64), jointly form synchronous debugging device interface Debugger4; Debugger1, Debugger2, Debugger3 are connected with the download debugging interface JTAG on three mainboards respectively; PC connects synchronous debugging device (5) by USB interface (62), and PC is connected respectively with the download debugging interface JTAG on three mainboards by synchronous debugging device interface Debugger1, Debugger2, the Debugger3 on synchronous debugging device (5).