CN102891185B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite the first conductivity type. The second doped region is separated from the third doped region by the first doped region. The third doped region has a first portion and a second portion adjacent to each other, and the first portion and the second portion are close to and far from the second doped region respectively. The doping concentration of the first portion is greater than the doping concentration of the second portion. The diode in the semiconductor structure has high switching speed and low turn-on resistance. In addition, the diode of the invention can be self-isolated from other elements, and has small design area and low manufacturing cost.

Description

Semiconductor structure and manufacturing method thereof

technical field

The present invention relates to semiconductor structures and methods of fabrication thereof, and more particularly to diodes and methods of fabrication thereof.

Background technique

Diodes in semiconductor structures have a wide range of applications in electronic circuits. Diodes can be used to stabilize voltage and provide a stable voltage to the circuit. In addition, diodes can also be used to protect circuit elements of integrated circuit devices from extremely powerful voltages. However, general diodes still have problems that need to be improved. For example, the switching speed is low, which cannot meet the requirements of integrated circuit devices, and is likely to cause circuit failure. Therefore, the current circuit trend is to develop towards high-speed switching. However, general diodes require a large design area, which prevents breakthrough development in the miniaturization of unit devices.

Contents of the invention

The present invention relates to semiconductor structures and methods of fabrication thereof. The diodes in the semiconductor structure of the present invention have high switching speed and low on-resistance. In addition, the diode of the present invention can be self-isolated from other components, requiring a small design area and low manufacturing cost.

The present invention provides a semiconductor structure. The semiconductor structure includes a diode. The diode includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region is separated from the third doped region by the first doped region. The third doping region has a first portion and a second portion which are adjacent to and are respectively close to and far from the second doping region. The doping concentration of the first portion is greater than that of the second portion.

The invention also provides a manufacturing method of the semiconductor structure. A method of fabricating a semiconductor structure includes forming a diode. A method of forming a diode includes the following steps. A second doped region is formed on the first doped region. A third doped region is formed on the first doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region is separated from the third doped region by the first doped region. The third doping region has a first portion and a second portion which are adjacent to and are respectively close to and far from the second doping region. The doping concentration of the first portion is greater than that of the second portion.

The invention also provides a semiconductor structure. The semiconductor structure includes a diode. The diode includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region is separated from the third doped region only by the first doped region.

The invention also provides a method for manufacturing the semiconductor structure. A method of fabricating a semiconductor structure includes forming a diode. A method of forming a diode includes the following steps. A second doped region is formed on the first doped region. A third doped region is formed on the first doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region is separated from the third doped region only by the first doped region.

The preferred embodiments are specifically cited below, and in conjunction with the attached drawings, the detailed description is as follows:

Description of drawings

FIG. 1 shows a cross-sectional view of a semiconductor structure in one embodiment.

FIG. 2 illustrates a top view of a semiconductor structure in one embodiment.

FIG. 3 shows I-V curves of the diode of the embodiment and the diode of the comparative example.

4 to 8 illustrate the process of the semiconductor structure in an embodiment.

FIG. 9 illustrates a semiconductor structure and its method of operation in one embodiment.

FIG. 10 is a cross-sectional view of a semiconductor structure in an embodiment.

FIG. 11 is a cross-sectional view of a semiconductor structure in an embodiment.

FIG. 12 is a cross-sectional view of a semiconductor structure in an embodiment.

FIG. 13 is a cross-sectional view of a semiconductor structure in an embodiment.

FIG. 14 is a cross-sectional view of a semiconductor structure in an embodiment.

FIG. 15 is a cross-sectional view of a semiconductor structure in an embodiment.

[Description of main component symbols]

2: the first doped region;

4, 104, 204, 704: the second doped region;

6, 106, 206, 706: the third doped region;

8, 36, 108, 136, 436, 508, 536, 608, 636, 846, 850, 860: well area;

10, 110, 710: top floor;

12, 112, 712: the first layer;

14, 114, 714: the second layer;

16, 18, 20: edge;

22: first part;

24: first part;

26, 126, 326: dielectric isolation structure;

28, 128: Substrate;

30, 130: epitaxial layer;

32, 432: doped isolation structure;

34, 134, 434, 848: buried layers;

138: interlayer dielectric layer;

140: conductive layer;

142: conductive plug;

744: Dielectric isolation structure;

852, 854, 856: heavily doped regions;

858: grid structure;

D: component area;

HA: high side area;

L1: side length.

Detailed ways

1 and 2 respectively illustrate a cross-sectional view and a top view of a semiconductor structure in an embodiment. FIG. 2 does not show the dielectric isolation structure 26 in FIG. 1 . Referring to FIG. 1 , the semiconductor structure includes a diode. The diode includes a first doped region 2 , a second doped region 4 and a third doped region 6 . The first doped region 2 includes a well region 8 and a top layer 10 . Top layer 10 is located on well region 8 . Edge 20 of top layer 10 may be located between opposite edge 16 and edge 18 of third doped region 6 . The top layer 10 includes a first layer 12 and a second layer 14 . The first sub-layer 12 is located on the second sub-layer 14 . The doping concentration of the first sub-layer 12 may be greater than the doping concentration of the second sub-layer 14 . The third doped region 6 has a first portion 22 and a second portion 24 adjacent to each other, which are respectively close to and far from the second doped region 4 . The doping concentration of the first portion 22 may be greater than the doping concentration of the second portion 24 . In one embodiment, the third doped region 6 and the well region 8 of the first doped region 2 , the first layer 12 and the second layer 14 have a first conductivity type such as P conductivity type. The second doped region 4 has a second conductivity type opposite to the first conductivity type, eg N conductivity type. The second doped region 4 and the third doped region 6 may be heavily doped. In an embodiment, the diode may be used as a Zener diode.

Referring to FIG. 1 , the semiconductor structure may include a substrate 28 , an epitaxial layer 30 and a doped isolation structure 32 . Epitaxial layer 30 is formed on substrate 28 . The substrate 28 and the epitaxial layer 30 may have a first conductivity type such as P conductivity type. The doped isolation structure 32 may include a buried layer 34 and a well region 36 . The buried layer 34 and the well region 36 may have a second conductivity type such as N conductivity type. The doped isolation structure 32 provides diode self-isolation so that the diode can be isolated from other components.

Referring to FIG. 1 , in one embodiment, the second doped region 4 and the third doped region 6 are only separated by the top layer 10 of the first doped region 2 . In other words, there is no dielectric isolation structure between the second doped region 4 and the third doped region 6 . Therefore, the area occupied by the diode is small. In an embodiment, compared with the second doped region (such as the second doped region 704 in FIG. 14 ) and the third doped region (such as the third doped region 706 in FIG. 14 ) through the dielectric isolation structure For separated diodes (for example, the dielectric isolation structure 744 in FIG. 14 ), the area occupied by the diode without the dielectric isolation structure between the second doped region 4 and the third doped region 6 is smaller. For example, for a diode without a dielectric isolation structure between the second doped region 4 and the third doped region 6, the active region (OD) of the diode is defined by the interval of the dielectric isolation structure 26 such as a field oxide. region) side length L1 (Figure 2) can be as small as 12.6 μm. However, for a diode with a dielectric isolation structure (such as the dielectric isolation structure 744 in FIG. 14 ), the side length of the active region is 16.4 μm.

The top layer 10 as shown in FIG. 1 enables the diode to have a low on-resistance. In addition, using the top layer 10 and omitting the dielectric isolation structure (such as the dielectric isolation structure 744 in FIG. 14 ) between the second doped region 4 and the third doped region 6 can improve the switching speed of the diode. For example, FIG. 3 shows the current-voltage (I-V) curves of the diode of the embodiment and the diode of the comparative example, wherein the switching speed of the diode of the embodiment is significantly higher than that of the diode of the comparative example.

The semiconductor structure in the embodiment can be applied to mix-mode or analog circuit design, such as a start-up circuit or a charge pump circuit.

4 to 8 illustrate the process of the semiconductor structure in an embodiment. Referring to FIG. 4 , a buried layer 134 is formed on the substrate 128 . The buried layer 134 can be formed by a doping process in conjunction with the mask layer. For example, the method for forming the buried layer 134 may include forming a patterned mask layer (not shown) on the substrate 128 , and then doping the substrate 128 exposed by the mask layer to form the buried layer 134 . After the buried layer 134 is formed, the mask layer is removed. In one embodiment, an annealing step may also be performed to drive in impurities to form the buried layer 134 .

Referring to FIG. 5 , an epitaxial layer 130 is formed on the substrate 128 . In addition, for example, a well region 136 is formed on the substrate 128 , the epitaxial layer 130 and the buried layer 134 . The well region 108 can be formed on the buried layer 134 and the well region 136 . The well region 136 and the well region 108 can be respectively formed by a doping process with a mask layer. In some embodiments, an annealing step may be performed to implant impurities to form the well region 136 and the well region 108 .

Referring to FIG. 6 , a second sublayer 114 is formed on the well region 108 . The second sub-layer 114 can be formed by a doping process with a mask layer. For example, the second sub-layer 114 is formed by doping the top portion of the well region 108 . In some embodiments, an annealing step may be performed to implant impurities to form the second sub-layer 114 as shown in FIG. 7 . Referring to FIG. 7 , for example, a dielectric isolation structure 126 is formed on the well region 108 , the epitaxial layer 130 and the well region 136 . The first sub-layer 112 is formed on the second sub-layer 114 . A second doped region 104 is formed on the first layer 112 . A third doped region 106 is formed on the well region 108 and the top layer 110 including the first sub-layer 112 and the second sub-layer 114 . The first layer 112 , the second doped region 104 and the third doped region 106 can be respectively formed by a doping process with a mask layer. The method for forming the third doped region 106 includes doping the top portion of the top layer 110 and the top portion of the well region 108 adjacent to each other.

Referring to FIG. 8 , an interlayer dielectric layer 138 is formed and a conductive layer 140 and a conductive plug 142 electrically connected to the second doped region 104 and the third doped region 106 are formed. The forming method of the conductive layer 140 may include depositing a conductive material such as metal on the interlayer dielectric layer 138 and patterning the conductive material. The forming method of the conductive plug 142 may include forming a hole in the interlayer dielectric layer 138 and filling the hole with a conductive material such as metal.

The manufacturing method of the semiconductor structure in the embodiment can be applied to mix-mode or analog circuit design, such as a start up circuit or a charge pump circuit.

In one embodiment, a method for operating a diode of a semiconductor structure includes electrically connecting a cathode to the second doped region 204 and electrically connecting an anode to the third doped region 206 , as shown in FIG. 9 .

FIG. 10 is a cross-sectional view of a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 10 and the semiconductor structure shown in FIG. 1 is that the dielectric isolation structure 326 is shallow trench isolation.

FIG. 11 is a cross-sectional view of a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 11 and the semiconductor structure shown in FIG. 1 is that the dielectric isolation structure 26 shown in FIG. 1 is omitted. In this example, the diode does not form any dielectric isolation structure, thus reducing the manufacturing cost. In this example, the active region of the diode is defined by the doped isolation structure 432 including the buried layer 434 and the well region 436 . In addition, the diode is isolated from other components by doping the isolation structure 432 and the buried layer 434 .

FIG. 12 is a cross-sectional view of a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 12 and the semiconductor structure shown in FIG. 1 is that the buried layer 34 shown in FIG. 1 is omitted. In addition, well region 508 having a shallower depth than well region 536 is used. In this example, the diode is isolated from other components by well region 536 .

FIG. 13 is a cross-sectional view of a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 13 and the semiconductor structure shown in FIG. 1 is that the buried layer 34 and the epitaxial layer 30 shown in FIG. 1 are omitted. In addition, well region 608 having a shallower depth than well region 636 is used. In this example, the diode is isolated from other components by well region 636 .

FIG. 14 is a cross-sectional view of a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 14 and the semiconductor structure shown in FIG. 1 is that the second doped region 704 and the third doped region 706 are separated by a dielectric isolation structure 744 such as a field oxide. In other embodiments, the dielectric isolation structure 744 is shallow trench isolation. In one embodiment, the dielectric isolation structure 744 is formed after the top layer 710 including the first sub-layer 712 and the second sub-layer 714 . In another embodiment, the dielectric isolation structure 744 is formed after the second sub-layer 714 . The first layer 712 is formed after the dielectric isolation structure 744 , so the doping path used to form the first layer 712 is through the dielectric isolation structure 744 . In this case, the turn-on resistance (Ron) of the diode is thus reduced. In yet another embodiment, both the first sub-layer 712 and the second sub-layer 714 are formed after the dielectric isolation structure 744 . In this case, the turn-on resistance of the diode is thus reduced.

The diode of the semiconductor structure in the embodiment can be configured in a high side area of a high voltage integrated circuit (HVIC). For example, FIG. 15 shows a cross-sectional view of a semiconductor structure in an embodiment, wherein the diode is disposed in the high-side region HA adjacent to the device region D. Referring to FIG. There is a well region 860 between the device region D and the high-side region HA, which may have a first conductivity type such as a P conductivity type. The elements arranged in the element region D may include transistors (MOS). The transistor may include a well region 846 such as a high voltage well region, a buried layer 848 , a well region 850 , a heavily doped region 852 , a heavily doped region 854 such as a source, and a heavily doped region 856 such as a drain and gate structure 858 . The transistors can be NMOS. In one embodiment, the well region 850 and the heavily doped region 852 have a first conductivity type such as P conductivity type. The well region 846 , the buried layer 848 , the heavily doped region 854 and the heavily doped region 856 have a second conductivity type such as N conductivity type. The heavily doped region 856 such as the drain is required to withstand high voltage such as ultra-high voltage greater than 600V.

In an embodiment of the present invention, forming the first layer or the second layer of the top layer after the dielectric isolation structure can reduce the turn-on resistance of the diode. The doping range of the top layer is properly adjusted to improve the switching speed of the diode. Omitting the dielectric isolation structure between the second doped region and the third doped region can also improve the switching speed of the diode. In addition, the required design area of the unit element can be reduced and the manufacturing cost can be reduced. The diode can be self-isolated from other components by doping the isolation structure.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make minor changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (9)

1. a semiconductor structure, is characterized in that, comprises a diode, and wherein this diode comprises:

One first doped region, has one first conductivity type;

One second doped region, has one second conductivity type in contrast to this first conductivity type; And

One the 3rd doped region, has this first conductivity type;

Wherein, this second doped region is separated by this first doped region with the 3rd doped region, 3rd doped region has an adjoining Part I and a Part II, this Part I and this Part II respectively near with away from this second doped region, the doping content of this Part I is greater than the doping content of this Part II, this first doped region comprises a top layer, and an edge of this top layer is between the relative edge of the 3rd doped region.

2. semiconductor structure according to claim 1, is characterized in that, this second doped region and the 3rd doped region are only separated by this first doped region.

3. semiconductor structure according to claim 1, it is characterized in that, this first doped region comprises a top layer, and this top layer comprises one first sublevel and one second sublevel, this first sublevel is positioned on this second sublevel, and the doping content of this first sublevel is greater than the doping content of this second sublevel.

4. a manufacture method for semiconductor structure, is characterized in that, comprise formation one diode, the method forming this diode comprises:

One first doped region forms one second doped region; And

On this first doped region formed one the 3rd doped region, this first doped region comprises a top layer, an edge of this top layer between the relative edge of the 3rd doped region,

Wherein, this first doped region and the 3rd doped region have one first conductivity type, this second doped region has one second conductivity type in contrast to this first conductivity type, this second doped region is separated by this first doped region with the 3rd doped region, 3rd doped region has an adjoining Part I and a Part II, this Part I and this Part II respectively near with away from this second doped region, the doping content of this Part I is greater than the doping content of this Part II.

5. the manufacture method of semiconductor structure according to claim 4, is characterized in that, this first doped region comprises a well region, and the formation method of this top layer comprises a top portion of this well region of doping.

6. the manufacture method of semiconductor structure according to claim 5, is characterized in that, the formation method of the 3rd doped region comprises a doping top portion of this top layer adjacent to each other and a top portion of this well region.

7. the manufacture method of semiconductor structure according to claim 5, it is characterized in that, the method forming this diode comprises formation one dielectric isolation structure on this well region, wherein this second doped region is separated by this dielectric isolation structure with the 3rd doped region, and this top layer is formed after this dielectric isolation structure.

8. a semiconductor structure, is characterized in that, comprises a diode, and this diode comprises:

One first doped region, has one first conductivity type;

One second doped region, has one second conductivity type in contrast to this first conductivity type; And

One the 3rd doped region, has this first conductivity type;

Wherein, this second doped region and the 3rd doped region are only separated by this first doped region, and this first doped region comprises a top layer, and an edge of this top layer is between the relative edge of the 3rd doped region.

9. a manufacture method for semiconductor structure, is characterized in that, comprise formation one diode, the method forming this diode comprises:

One first doped region forms one second doped region; And

This first doped region forms one the 3rd doped region, and this first doped region comprises a top layer, and an edge of this top layer is between the relative edge of the 3rd doped region;

Wherein this first doped region and the 3rd doped region have one first conductivity type, and this second doped region has one second conductivity type in contrast to this first conductivity type, and this second doped region and the 3rd doped region are only separated by this first doped region.