CN102890663A - Data transmitting method and time delay module - Google Patents

Abstract

The present invention provides a data transmission method and a time delay module, wherein the data transmission method includes: setting the initial value of the transmission delay time of the delay transmission module between the first data terminal and the second data terminal; Multiple adjustments are made to perform multiple detections of the transmitted data, and the detection results corresponding to each transmission delay time are obtained; among the detection results corresponding to each transmission delay time, the optimal detection result is selected; the transmission delay corresponding to the optimal detection result is The time is set as the optimal transmission delay time of the delay transmission module, so that the data transmission between the first data terminal and the second data terminal is delayed by the optimal transmission delay time. Through the above data transmission method and time delay module, the data transmission delay time can be automatically adjusted to ensure the integrity and accuracy of data transmission.

Description

A data transmission method and a time delay module

technical field

The invention relates to the field of data communication, in particular to a data transmission method and a time delay module.

Background technique

Generally speaking, a processor on an application board of a base station or a core network (such as a CPU or a DSP, etc.) is integrated with a memory controller, and the memory controller usually has an external memory chip for storing data. Data is transferred between the memory controller and the memory chip. When the memory controller issues a write command, data is transferred from the memory controller to the memory chip. When the memory controller issues a read command, data is transferred from the memory chip to the memory controller and processed by the processor.

Memory chips usually use synchronous dynamic random access memory (SDRAM), which means that the work of the memory requires a synchronous clock. The double data stream SDRAM (DDR SDRAM) can transmit data on the rising edge (rising edge) and the falling edge (falling edge) of the clock, which is widely used by memory chips, so the following will be described using DDR chips as an example.

When the memory controller issues a read command, the external DDR chip selected by the processor will start to drive the data signal (DQ signal) and the data strobe (Data Strobe) signal (DQS signal for short), and the DDR chip is regarded as the sending end. When the memory controller issues a write command, the memory controller drives the DQ signal and the DQS signal, and the memory controller is regarded as the sending end. The DQS signal is bidirectional. It is a synchronous clock signal for data. Every 8 DQ signals that transmit a byte (Byte) correspond to a DQS signal. It is used to accurately distinguish each transmission cycle and facilitate the receiver to receive data accurately.

Figure 1 is a timing diagram of the DQ signal and the DQS signal at the receiving end in an ideal state. In an ideal situation, the center of the DQ signal (DQ0~DQ7 is a Byte) at the receiving end must be aligned with the rising or falling edge of the DQS signal (DQS0) to ensure the largest timing margin, thereby ensuring the integrity of the sampled data sex and accuracy. However, since the layout of memory controllers of various processors manufactured by each manufacturer is different, and in the actual application process of the board, it is affected by many factors such as ambient temperature, changes in transmission line resistance, chip power supply voltage, etc. Affected by various factors, the propagation delay of the DQ signal and the DQS signal is also different, so that the data cannot be correctly written into the DDR chip or cannot be correctly read by the DDR chip.

FIG. 2 shows a timing diagram of a DQ signal and a DQS signal actually received by a receiving end. When the DQ signal and the DQS signal are transmitted to the receiving end, the center of the DQ signal is usually out of alignment with the DQS signal. When the DQS signal transmission delay is very serious, it may cause correct data transmission, that is, the correct reading and writing of the DDR chip cannot be performed.

In order to allow the DDR chips from different manufacturers plugged into different processors to be able to read and write smoothly, board designers must first purchase DDR chips from different manufacturers and solder them to the board during the development of the board, and then Connect all the signal lines of the DDR interface between these DDR chips and the processor chip to the oscilloscope, and then test the signal quality of these DDR chips under working conditions. Due to different wiring of different processors and DDR chips, differences in DDR chip speed levels, ambient temperature, chip power supply voltage and other factors, some DDR chips cannot be read or written smoothly, and testers make judgments based on the quality of test signals. And replace these DDR chips that cannot be read and written smoothly.

When there are many types of processor memory controllers and DDR chips, it will be inefficient to manually test signals and eliminate problems, and when the actual working environment of the board changes (for example, the test environment is very different), pass the test. The external DDR chip on the single board may not be able to read and write correctly.

Contents of the invention

In order to realize automatic adjustment of transmission delay time, an embodiment of the present invention provides a data transmission method and a time delay module.

In order to solve the problems of the technologies described above, the present invention provides the following solutions:

A data transmission method, comprising:

The delay transmission module between the first data terminal and the second data terminal obtains an initial value of a transmission delay time, and the transmission delay time is applied between the first data terminal and the second data terminal by the delay transmission module Delay in transmitting data;

The delay transmission module performs multiple detections of the transmission data by adjusting the transmission delay time multiple times, and obtains a detection result corresponding to each transmission delay time;

The delayed transmission module selects the optimal detection result among the detection results corresponding to each transmission delay time;

The delay transmission module sets the transmission delay time corresponding to the optimal detection result as the optimal transmission delay time of the delay transmission module, so that the data transmission between the first data terminal and the second data terminal passes through The delay of the optimal transmission delay time.

Preferably, in the above-mentioned data transmission method,

Before multiple times of adjusting the transmission delay time to perform multiple detections of transmission data, the method further includes:

The delay transmission module detects the frequency of the data strobe signal of the transmission data;

The delay transmission module divides the frequency to determine the step unit time;

The multiple adjustments of the transmission delay time include:

performing multiple adjustments to the step value;

On the basis of the initial value, increase or decrease the product of the step unit time and the step value to obtain the adjusted transmission delay time.

Preferably, in the above-mentioned data transmission method, the frequency division coefficient for dividing the frequency is N, and N is a natural number greater than 1;

The multiple detections of the transmitted data by the delayed transmission module through multiple adjustments to the transmission delay time specifically include:

Each time the delay transmission module obtains a detection result, it judges whether the step value is less than N, if the step value is less than N, gradually increases the step value, and continues to detect the received data; if If the step value is equal to N, the step of selecting the optimal detection result among the detection results corresponding to each transmission delay time is continued.

Preferably, in the above data transmission method, the transmission delay time includes:

The receiving delay time for the first data terminal to receive the data sent by the second data terminal and the transmission delay time for the data sent from the first data terminal to the second data terminal;

The delayed transmission module performs multiple detections of the transmitted data through multiple adjustments to the transmission delay time, and obtains a detection result corresponding to each transmission delay time, which specifically includes:

Adjusting the receiving delay time and sending delay time to perform multiple detections of transmission data, and obtain the detection result of each detection, wherein, any connection between the first data terminal and the second data terminal or between the second data terminal and the first data terminal When data transmission fails in one direction, the detection result is transmission failure; when data transmission succeeds in both directions from the first data terminal to the second data terminal and from the second data terminal to the first data terminal, the detection result is The result is the transmission is successful;

A detection result matrix including the detection results obtained by the multiple detections is generated by using the receiving delay time as a row coordinate and the sending delay time as a column coordinate.

Preferably, in the above data transmission method, the delayed transmission module selects the optimal detection result among the detection results corresponding to each transmission delay time, specifically:

In the detection result matrix, the delayed transmission module selects the matrix with the largest number of detection results indicating successful transmission;

Selecting the detection result located in the central part of the matrix as the optimal detection result.

Preferably, the above data transmission method further includes: when the preset condition for optimizing the transmission delay time is reached, starting the delay transmission module between the first data terminal and the second data terminal to set the initial value of the transmission delay time A step of.

Preferably, in the above data transmission method, the delay transmission module makes the data strobe signal of the data sending end pass through the transmission delay time, and then uses it as the clock signal of the trigger to control the conduction of the data terminal of the trigger, thereby controlling the The transmission delay time of the transmission data described above.

The present invention also provides a time delay module, located between the first data terminal and the second data terminal, the time delay module includes:

A transmission delay time adjustment module, configured to receive the set initial value of the transmission delay time, and adjust the transmission delay time multiple times on the basis of the initial value of the transmission delay time;

A transmission data detection module, configured to detect the transmission data under the transmission delay time sent by the transmission delay time adjustment module, and obtain corresponding detection results;

An optimal detection result acquisition module, configured to obtain an optimal detection result from the plurality of detection results; and an optimal transmission delay time configuration module, configured to configure the transmission delay time corresponding to the optimal detection result as an optimal transmission delay Time, so that the data transmission between the first data terminal and the second data terminal passes through the delay of the optimal transmission delay time.

Preferably, the above-mentioned time delay module further includes:

a frequency detection module, configured to detect the frequency of the data strobe signal of the transmission data; and

A frequency division module, configured to divide the frequency to determine the step unit time;

The transmission delay time is the product of the step unit time and a step value; the step value is a natural number greater than or equal to 1;

The transmission delay time adjustment module is specifically configured to receive the set initial value of the transmission delay time, adjust the step value multiple times on the basis of the transmission delay time initial value, and notify the transmission delay time to the Transmission data detection module.

Preferably, in the above-mentioned time delay module, the frequency division module is specifically used to divide the frequency according to a frequency division coefficient N to determine the step unit time, where N is a natural number greater than 1;

The transmission delay time adjustment module is further used to judge whether the step value is less than N, if the step value is less than N, gradually increase the step value, and notify the transmission data detection of the transmission delay time module; if the step value is equal to N, notify the optimal detection result acquisition module.

Preferably, in the above-mentioned time delay module, the transmission delay time includes: the reception delay time for the first data terminal to receive the data sent by the second data terminal and the delay time for the first data terminal to send the data to the second data terminal The delay time of sending data at the data end;

The transmission delay time adjustment module is specifically configured to receive the set initial value of the reception delay time and the initial value of the transmission delay time, and adjust the reception delay time multiple times on the basis of the initial value of the reception delay time, and performing multiple adjustments to the sending delay time on the basis of the initial value of the sending delay time;

The transmission data detection module is specifically used to perform multiple detections on the transmission data under the reception delay time and transmission delay time of multiple transmissions sent by the transmission delay time adjustment module, obtain the detection result of each detection, and use the received The delay time is a row coordinate, and the transmission delay time is a column coordinate, and a detection result matrix including the detection results obtained by the multiple detections is generated; wherein, from the first data end to the second data end or from the second data end to the second data end When a data transmission failure occurs in any direction of a data terminal, the detection result is a transmission failure, and when data transmission succeeds in both directions from the first data terminal to the second data terminal and from the second data terminal to the first data terminal , the detection result is that the transmission is successful.

Preferably, in the above-mentioned time delay module, the optimal detection result acquisition module is specifically configured to, in the detection result matrix, select the matrix with the largest number of successfully transmitted detection results, and select the matrix located in the center of the matrix The detection result of is taken as the optimal detection result.

Preferably, the above-mentioned time delay module further includes: an optimized transmission time start module, configured to send the initial value of the transmission delay time to the transmission delay time adjustment module when the preset condition for optimizing the transmission delay time is reached, and start the transmission Adjustment of delay time.

The data transmission method and the time delay module provided by the embodiment of the present invention enable the data transmission delay time to be automatically adjusted and optimized without soldering the memory chip to the single board and performing manual detection by an oscilloscope, and can ensure the integrity and integrity of the data transmission accuracy.

Description of drawings

Figure 1 is a timing diagram of the ideal DQ signal and DQS signal at the receiving end;

Figure 2 is a timing diagram of DQ signals and DQS signals at the receiving end in actual use;

Fig. 3 is a method flowchart of an embodiment of the present invention;

Fig. 4 is an equivalent diagram of a circuit connection structure of an embodiment of the present invention;

Fig. 5 is a method flowchart of an embodiment of the present invention;

6 is a schematic diagram of a detection result matrix according to an embodiment of the present invention;

7 is a schematic diagram of a detection result matrix according to an embodiment of the present invention;

Fig. 8 is a structural block diagram of a time delay module according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

The present invention provides an embodiment of a data transmission method. Transmission data is detected by adjusting the transmission delay time, and then an optimal transmission delay time is obtained, and the data transmission is performed using the delay time. Referring to Figure 3, an embodiment of the method includes:

Setting the initial value of the transmission delay time for the delay transmission module between the first data terminal and the second data terminal;

Perform multiple detections of the transmission data by adjusting the transmission delay time multiple times, and obtain a detection result corresponding to each transmission delay time;

Selecting an optimal detection result among the detection results corresponding to each transmission delay time;

Setting the transmission delay time corresponding to the optimal detection result as the optimal transmission delay time of the delay transmission module, so that the data transmission between the first data terminal and the second data terminal passes through the optimal transmission delay time Delay time delay.

Assume that the first data terminal and the second data terminal in the above embodiment are respectively the memory controller and its external memory chip. According to the instructions issued by the memory controller, the memory controller sends data to the memory chip or receives data from the memory chip. chip data. Between the memory controller and the memory chip, there is a delay transmission module, which causes the DQS signal to be delayed for a certain period of time (this delay can be advanced or backward, collectively referred to as delay), so that the DOS signal is located as far as possible Center of the DQ signal.

Figure 4 shows the process of reading data from the memory chip to the memory controller. The delay transmission module can be realized by a delay phase-locked loop (Delay Lock Loop, DLL) and a D flip-flop. The DLL is used to make the clock signal generate a certain amount of delay. The data strobe signal DQS of the memory chip is input to the clock terminal (CLK terminal) of the D flip-flop after being delayed by the DLL, and the DQ signal of the memory chip is connected to the data terminal (D terminal) of the D flip-flop. In this way, after the DQS signal is delayed in the DLL such as T' shown in Figure 2, the D flip-flop is triggered to be turned on, so that the "shifted" DQS signal is just aligned with the center of the DQ signal. In this way, the delay transmission module obtains multiple test results corresponding to each transmission delay time by automatically adjusting the transmission delay time, and selects the optimal value from the test results, so that the delay transmission module obtains the optimal transmission delay time and automatically realizes the transmission delay time The optimization avoids the cumbersome adjustment of transmission delay time by manual test method, and the inconvenience caused by manual test when the transmission delay time needs to be adjusted due to changes in environmental temperature, chip power supply voltage and other factors during use.

In a specific embodiment, after the single board is powered on, the initial value of the transmission delay time is first set, generally zero can be selected, and then the transmission delay time is gradually increased or decreased on the basis of the initial value each time. Of course, it can also be set to a value other than zero. The range of the initial value is related to the frequency of the DQS signal. If it is a DDR chip, the range of the initial value is the duration between the rising and falling edges of two adjacent DQS pulses. The following The DDR chip is taken as an example for description.

After the initial value of the transmission delay time is set, the transmission data is tested. In this example, the reading test of the DDR chip is performed, so for the memory controller, the receiving time of the DQ signal is delayed, that is, the transmission delay time is the receiving delay time. The memory controller compares the DQ signal output on the DDR chip side with the DQ signal received by the memory controller to obtain a test result. If the value of the DQ signal output from the DDR chip side is the same as the DQ signal received at the memory controller side, it means that the reading is successful; otherwise, the reading fails. Constantly adjust the receiving delay time within a certain range to obtain multiple test results. The range of adjustment is the same as the range of setting the initial value.

Then, the optimal result is selected from the multiple test results, and the receiving delay time corresponding to the optimal result is found. Multiple test results will include multiple successful reading records. For example, if the rising edge of the first pulse in Figure 2 is very close to the midpoint of D0, it means that the reception delay makes the data reception more stable (if the data is received as shown in Figure 2 Indicates that although the rising edge of the first pulse is within the range of D0, it does not mean that the reading is successful). Among the test records that have been successfully read for several times, only one time makes the rising edge (or falling edge) of the pulse closest to the center of D0, and the receiving delay time corresponding to this time is the optimal receiving delay time. Assign this optimal receiving delay time to the DLL, so that the data reading of the DDR chip is at the maximum timing margin.

Similarly, the above read test can also be a write test from the memory controller to the DDR chip, and the steps are similar. Of course, since the data transmission between the memory controller and the memory chip is bidirectional, that is, both reading and writing of memory chip data need to adjust the delay transmission time, a better test plan should be to perform both reading and writing. Test, and comprehensively optimize the receiving delay time and sending delay time, so as to obtain the optimal transmission delay time for reading and writing.

A better test scheme is provided below. Complete the output and writing test process between the memory controller and the DDR chip, that is, write the DQ signal to the DDR chip on the content controller side, then receive the DQ signal from the DDR chip side, and compare the two signals . First, the DQ signals written by the memory controller to the DDR chip are 55AA55AA, AA55AA55, 0, FFFFFFFF (the order is not limited), and the above values are measured four times in a row (for example, the first DQ signal is 55AA55AA, the second DQ The signal is AA55AA55), if each byte received by the memory controller end is the same as the above data, the read and write test is successful. The considerations for selecting the above values are that in binary, 5 is 0101, A is 1010, and F is 1111. After four tests, each bit appears 0, 1, 0, 1 (testing twice means that 1 and 0 appear once It is also feasible), and it can more accurately determine whether the occasions of 0 and 1 are received normally. It can be seen from this that similar combinations of the above-mentioned measurement signals such as A5A5A5A5, 5A5A5A5A, FFFFFFFF, and 0 can also achieve the same effect.

In a preferred embodiment, a step-by-step detection method is used to realize multiple detections. Before making multiple adjustments to the transmission delay time, the frequency of the DQS signal is detected first, and then the frequency is divided to obtain the step unit time. Assuming that the frequency division clock of the internal phase-locked loop PLL of the processor is used, the frequency of the DQS signal at the DDR terminal is detected to be 500M Hz. When the frequency division coefficient is 10, the frequency after frequency division is 5000M Hz, that is, the step unit time is 2*10 ^-10 s. For the adjustment of transmission delay time, fine-tune in units of 2*10 ^-10 . When the step value is 1, the transmission delay time is increased or decreased by 2*10 ^-10 s from the initial value; when the step value is 2, the transmission delay time is increased or decreased by 4*10 ^-10 s from the initial value, and so on.

In theory, the frequency division coefficient can be infinitely large, that is, the step unit time can be infinitely short. The frequency division coefficient and the total number of steps are the same in value, that is, how many times the total number of steps can be divided into as many step units of time. Of course, the step value does not have to be increased one by one. When the frequency division coefficient is large enough, the step value can be increased by 2, 3 or a larger value each time, but when the above step value increases to the total number of steps, one The test cycle ends. Still take reading the DDR chip as an example, from the test results obtained in this cycle, first select the test result that was successfully received, and then find one or two in the middle (when the number of successful reception is even, the optimal value is two ) to get the corresponding optimal delayed receiving time. When there are two optimal values, just choose one of them at random.

The methods of the above-mentioned embodiments can be applied to writing to the memory chip and reading from the memory chip by the memory controller, that is, adjustment of delayed receiving time and delayed sending time. For example, when writing to a memory chip, the delayed transmission time is the delayed sending time. The DQS signal sent by the memory controller passes through the delayed sending time, and then triggers the D flip-flop to turn on the transmission of the DQ signal to the memory chip.

In the following embodiments, the present invention provides a method of data transmission, in the process of data transmission between the memory controller and the memory chip (taking the DDR chip as an example), using delayed sending time and delayed receiving time (such as using DLL function) to adjust the timing relationship between the DQ signal and the DQS signal at the receiving end. As shown in Figure 5, after the single board is powered on, the processor completes the initialization operation of the memory controller and the DDR chip, and after obtaining the step unit time according to the method of the above-mentioned embodiment, the method for optimizing the transmission delay time includes the following steps:

Step 1. Configure the initial value of the delayed receiving time (initial receiving DLL configuration value);

Step 2. Configure the initial value of the delayed sending time (initial sending DLL configuration value), and the time sequence of step 2 and step 1 is not limited;

Step 3. Configure the delayed sending time in a step-by-step manner, that is, adjust the delayed sending time by adjusting the step value, and the delayed sending time = sending step value × step unit time;

Step 4. Carry out writing test to DDR chip and record test result;

Step 5. Determine whether the sending step value has reached the total number of steps N, that is, whether the accumulated number of sending DLL steps has reached the total number of steps available; if not, return to step 3 for execution; if reached, then Execute step 6;

Step 6. Configure the delayed receiving time by stepping, that is, adjust the delayed receiving time by adjusting the step value (receiving step value × step unit time);

Step 7. Carry out a reading test on the DDR chip and record the test result;

Step 8. Determine whether the received step value reaches the total number of steps N, that is, whether the accumulated number of received DLL steps has reached the total number of steps available; if not, return to step 3 for execution; if reached, then Execute step 9;

Step 9. Obtain the test result matrix, calculate the optimal test result from the test result matrix, and obtain the corresponding optimal transmission delay time.

Finally, the DLL function module is configured with the optimal transmission delay time, and the data transmission uses the DLL function module to realize the delay.

In the above loop nesting method, the order of configuring the delayed sending time by stepping through the above step 3 and configuring the delayed receiving time by stepping in step 6 can be interchanged, and the delayed sending time can also be realized The data transmission corresponding to the two-dimensional value of the delayed receiving time is detected, and the test results arranged in a matrix are obtained in step 9.

In the above step 9, the test results are arranged in a matrix, and the matrix with the largest number of successful read and write tests is found from the matrix table, and the matrix in which all the read and write test results are successful in the total matrix table is found. Select the largest number of test results in these matrices, which is reflected in the test result matrix table (part) in Figure 6, which is the rectangle with the largest area of "√", and obtain the two-dimensional value closest to the middle value in the rectangle. Taking the test result matrix shown in FIG. 6 as an example, the abscissa of the matrix represents the sending DLL configuration value (delayed sending time), and the ordinate of the matrix represents the receiving DLL configuration value (delayed receiving time). The interval between adjacent step values is the same size. The mark "×" in the matrix indicates that after using the corresponding (abscissa value, ordinate value) two-dimensional DLL configuration value for transmission delay, the read and write test of the DDR chip fails (failure to read or write or both read and write) Write failed); the mark "√" in the matrix indicates that after using the corresponding (abscissa value, ordinate value) two-dimensional DLL configuration value for transmission delay, the read and write test of DDR is successful (both read and write are successful) . How to find the most suitable transmission delay time (that is, the comprehensive optimization of data delay sending time and delay receiving time) among the transmission delay times corresponding to the test results of these successful read and write tests, that is, to make the memory controller end receive the DQS signal The rising and falling edges are as close to the center of the received DQ signal as possible, and the rising and falling edges of the DQS signal received by the DDR chip are as close as possible to the center of the received DQ signal. Pick from the area matrix.

In Figure 6, the rectangle with the largest area marked "√" is a 3×3 square, and the ordinate and abscissa of the "√" in the middle ("√" surrounded by a circle) are the optimal transmission delay time. In FIG. 7 , the rectangle with the largest area marked "√" is a 2×4 rectangle, and there are four combinations ("√" surrounded by four circles respectively) for the optimal transmission delay time. After obtaining the optimal combination of these four sets of delayed sending time and delayed receiving time, one of them can be randomly selected and set in the DLL module.

In the above detection, the selection of the transmitted DQ signal can use the aforementioned recommended values, such as 55AA55AA, AA55AA55, 0, FFFFFFFF (the sequence is not limited) to measure four times continuously, if the values of these DQ signals received by the memory controller side If they are all the same as the value of the DQ signal written to the DDR chip, then the read and write test is successful, and the reason will not be repeated here.

In a preferred embodiment, the trigger conditions for re-optimizing parameters are set, such as changes in ambient temperature, chip power supply voltage, etc., so that the transmission delay time needs to be optimized and adjusted, so the delayed sending time and delayed receiving time are configured in the delayed transmission module The initial value of the initial value, the delayed transmission module that has obtained the initial value will start the above test, through multiple tests and find the delayed sending time and delayed receiving time corresponding to the optimal test result in the test results, for the memory controller and the memory chip. data transfer between. This can avoid the inconvenience caused by manual testing when the transmission delay time needs to be adjusted due to the influence of various factors during use.

The present invention also provides an embodiment of a time delay module, for example, the function of the time delay module is realized by a delay-locked loop (DLL) and a D flip-flop in FIG. 4 . Figure 8 shows a block diagram of the internal structure of the DLL between the first data terminal and the second data terminal, including:

The transmission delay time adjustment module is used to receive the set initial value of the transmission delay time, and adjust the transmission delay time multiple times on the basis of the initial value of the transmission delay time;

The transmission data detection module is used to detect the transmission data under the transmission delay time sent by the transmission delay time adjustment module, and obtain corresponding detection results;

An optimal detection result acquisition module, configured to obtain an optimal detection result from a plurality of detection results; and

The optimal transmission delay time configuration module is used to configure the transmission delay time corresponding to the optimal detection result as the optimal transmission delay time, so that the data transmission between the first data terminal and the second data terminal passes through the optimal transmission delay time. Delay.

Preferably, the time delay module further includes:

Frequency detection module, for detecting the frequency of the data strobe signal of transmission data;

The frequency division module is used to divide the frequency detected above to determine the step unit time.

The above transmission delay time is the product of the step unit time and the step value; the step value is a natural number greater than or equal to 1;

The transmission delay time adjustment module is specifically used to receive the set initial value of the transmission delay time, adjust the step value multiple times on the basis of the initial value of the transmission delay time, and notify the transmission data detection module of the transmission delay time.

In a preferred embodiment, the above-mentioned frequency division module is specifically used to divide the detected frequency by a frequency division coefficient N to determine the step unit time, where N is a natural number greater than 1;

The above transmission delay time adjustment module is further used to judge whether the step value is less than N, if the step value is less than N, gradually increase the step value, so that the transmission delay time is adjusted, and notify the transmission delay time after the adjustment Data detection module; if the step value is equal to N, indicating that the step value has reached the total number available for stepping, then notify the optimal detection result acquisition module.

In the scenario where two-way data transmission is possible between the first data terminal and the second data terminal, either terminal may be a data sending terminal or a data receiving terminal, and the transmission delay time includes: receiving delay time and sending delay time.

The transmission delay time adjustment module is specifically used to receive the set initial value of the receiving delay time and the initial value of the sending delay time, and adjust the receiving delay time multiple times on the basis of the initial value of the receiving delay time. The sending delay time is adjusted multiple times on the basis of the initial value of the sending delay time;

The transmission data detection module is specifically used to detect the transmission data under the receiving delay time and sending delay time sent by the transmission delay time adjustment module, obtain corresponding detection results, and form a detection result matrix.

Further, the optimal detection result acquisition module is specifically used to, in the detection result matrix, select the matrix (the rectangle with the largest area) that contains the most test results among the successfully transmitted detection results, and select the detection result located in the center of the rectangle , as the optimal detection result.

Further, the time delay module further includes: an optimized transmission time start module, which is used to send the initial value of the transmission delay time to the transmission delay time adjustment module when the preset condition for optimizing the transmission delay time is reached, and start the adjustment of the transmission delay time.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (13)

1. A data transmission method, characterized in that, comprising: The delay transmission module between the first data terminal and the second data terminal obtains an initial value of a transmission delay time, and the transmission delay time is applied between the first data terminal and the second data terminal by the delay transmission module Delay in transmitting data; The delay transmission module performs multiple detections of the transmission data by adjusting the transmission delay time multiple times, and obtains a detection result corresponding to each transmission delay time; The delayed transmission module selects the optimal detection result among the detection results corresponding to each transmission delay time; The delay transmission module sets the transmission delay time corresponding to the optimal detection result as the optimal transmission delay time of the delay transmission module, so that the data transmission between the first data terminal and the second data terminal passes through The delay of the optimal transmission delay time. 2. The data transmission method according to claim 1, wherein: Before multiple times of adjusting the transmission delay time to perform multiple detections of transmission data, the method further includes: The delay transmission module detects the frequency of the data strobe signal of the transmission data; The delay transmission module divides the frequency to determine the step unit time; The multiple adjustments of the transmission delay time include: performing multiple adjustments to the step value; On the basis of the initial value, increase or decrease the product of the step unit time and the step value to obtain the adjusted transmission delay time. 3. the data transmission method according to claim 2, is characterized in that, the frequency division coefficient that the frequency division is carried out to described frequency is N, and N is the natural number greater than 1; The multiple detections of the transmitted data by the delayed transmission module through multiple adjustments to the transmission delay time specifically include: Each time the delay transmission module obtains a detection result, it judges whether the step value is less than N, if the step value is less than N, gradually increases the step value, and continues to detect the received data; if If the step value is equal to N, the step of selecting the optimal detection result among the detection results corresponding to each transmission delay time is continued. 4. The data transmission method according to any one of claims 1 to 3, wherein the transmission delay time includes: The receiving delay time for the first data terminal to receive the data sent by the second data terminal and the transmission delay time for the data sent from the first data terminal to the second data terminal; The delayed transmission module performs multiple detections of the transmitted data through multiple adjustments to the transmission delay time, and obtains a detection result corresponding to each transmission delay time, which specifically includes: Adjusting the receiving delay time and sending delay time to perform multiple detections of transmission data, and obtain the detection result of each detection, wherein, any connection between the first data terminal and the second data terminal or between the second data terminal and the first data terminal When data transmission fails in one direction, the detection result is transmission failure; when data transmission succeeds in both directions from the first data terminal to the second data terminal and from the second data terminal to the first data terminal, the detection result is The result is the transmission is successful; A detection result matrix including the detection results obtained by the multiple detections is generated by using the receiving delay time as a row coordinate and the sending delay time as a column coordinate. 5. The data transmission method according to claim 4, characterized in that, The delayed transmission module selects the optimal detection result among the detection results corresponding to each transmission delay time, specifically: In the detection result matrix, the delayed transmission module selects the matrix with the largest number of detection results indicating successful transmission; Selecting the detection result located in the central part of the matrix as the optimal detection result. 6. The data transmission method according to claim 1, characterized in that, the method further comprises: when the preset condition for optimizing the transmission delay time is reached, starting the communication between the first data terminal and the second data terminal Steps for the delayed transmission module to set the initial value of the transmission delay time. 7. The data transmission method according to claim 1, wherein the delay transmission module makes the data strobe signal of the data sending end pass through the transmission delay time, and then controls the trigger data as a clock signal of the trigger. The conduction of the end, thereby controlling the transmission delay time of the transmission data. 8. A time delay module, located between the first data terminal and the second data terminal, is characterized in that, the time delay module comprises: A transmission delay time adjustment module, configured to receive the set initial value of the transmission delay time, and adjust the transmission delay time multiple times on the basis of the initial value of the transmission delay time; A transmission data detection module, configured to detect the transmission data under the transmission delay time sent by the transmission delay time adjustment module, and obtain corresponding detection results; An optimal detection result acquisition module, configured to obtain an optimal detection result from the plurality of detection results; and an optimal transmission delay time configuration module, configured to configure the transmission delay time corresponding to the optimal detection result as an optimal transmission delay Time, so that the data transmission between the first data terminal and the second data terminal passes through the delay of the optimal transmission delay time. 9. time delay module according to claim 8, is characterized in that, also comprises: a frequency detection module, configured to detect the frequency of the data strobe signal of the transmission data; and A frequency division module, configured to divide the frequency to determine the step unit time; The transmission delay time is the product of the step unit time and a step value; the step value is a natural number greater than or equal to 1; The transmission delay time adjustment module is specifically configured to receive the set initial value of the transmission delay time, adjust the step value multiple times on the basis of the transmission delay time initial value, and notify the transmission delay time to the Transmission data detection module. 10. The time delay module according to claim 9, wherein the frequency division module is specifically used to divide the frequency by a frequency division coefficient N to determine the step unit time, where N is greater than 1 Natural number; The transmission delay time adjustment module is further used to judge whether the step value is less than N, if the step value is less than N, gradually increase the step value, and notify the transmission data detection of the transmission delay time module; if the step value is equal to N, notify the optimal detection result acquisition module. 11. The time delay module according to any one of claims 8 to 10, wherein the transmission delay time includes: the reception delay time for the first data terminal to receive the data sent by the second data terminal and The transmission delay time of the data sent from the first data terminal to the second data terminal; The transmission delay time adjustment module is specifically configured to receive the set initial value of the reception delay time and the initial value of the transmission delay time, and adjust the reception delay time multiple times on the basis of the initial value of the reception delay time, and performing multiple adjustments to the sending delay time on the basis of the initial value of the sending delay time; The transmission data detection module is specifically used to perform multiple detections on the transmission data under the reception delay time and transmission delay time of multiple transmissions sent by the transmission delay time adjustment module, obtain the detection result of each detection, and use the received The delay time is a row coordinate, and the transmission delay time is a column coordinate, and a detection result matrix including the detection results obtained by the multiple detections is generated; wherein, from the first data end to the second data end or from the second data end to the second data end When a data transmission failure occurs in any direction of a data terminal, the detection result is a transmission failure, and when data transmission succeeds in both directions from the first data terminal to the second data terminal and from the second data terminal to the first data terminal , the detection result is that the transmission is successful. 12. The time delay module according to claim 11, wherein the optimal detection result acquisition module is specifically used to, in the detection result matrix, select the matrix with the largest number of successful detection results, and Selecting the detection result located in the central part of the matrix as the optimal detection result. 13. The time delay module according to claim 8, further comprising: The optimized transmission time starting module is configured to send the initial value of the transmission delay time to the transmission delay time adjustment module when the preset condition of optimizing the transmission delay time is reached, and start the adjustment of the transmission delay time.

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