CN102882514B - AND logic circuit and chip - Google Patents

Abstract

The embodiment of the present invention discloses a logic circuit and a chip. The circuit includes: an array of resistive memristors and a comparator; The positive-phase input terminal of the same column of resistive memristor is used as the signal input terminal or auxiliary signal input terminal of the logic circuit, and the auxiliary signal input terminal is connected to the low level when working; the same row of resistive memristor array The inverting input terminal of the resistor is connected to the input terminal of a comparator, so that the output terminal of the comparator is used as the signal output terminal of the logic circuit; when the voltage received by the input terminal of the comparator is greater than the threshold voltage, the comparator's The output terminal outputs a high level, and when the voltage received by the input terminal of the comparator is lower than the threshold voltage, the output terminal of the comparator outputs a low level. In the embodiment of the present invention, while saving the area occupied by the logic circuit, the programmable performance of the logic circuit is realized.

Description

with logic circuits and chips

technical field

The invention relates to the field of electronic technology, in particular to logic circuits and chips.

Background technique

And logic circuits are usually based on metal-oxide-semiconductor (MOS, Metal-Oxide-Semiconductor) tube storage devices. As the requirements for chip integration become higher and higher, the size of and logic circuits is also decreasing, but due to MOS Due to the limitation of the size of the tube storage device itself, the AND logic circuit in the prior art has a minimum size technology node.

Contents of the invention

The embodiment of the present invention provides an AND logic circuit and a chip, which are used to solve the problem in the prior art that the AND logic circuit has a minimum size technology node.

In order to solve the above problems, the embodiment of the present invention discloses the following technical solutions:

On the one hand, there is provided an AND logic circuit, comprising: an array of resistive memristors and a comparator; the positive phase input terminals of the same row of resistive memristors in the array of resistive memristors are connected, so that all The positive-phase input terminal of the same column resistance variable memristor is used as the signal input terminal or the auxiliary signal input terminal of the logic circuit, and the auxiliary signal input terminal is connected to a low level during operation; the resistance variable memristor The inverting input terminal of the resistance variable memristor of the same row in the array is connected with the input terminal of one described comparator, so that the output terminal of the described comparator is used as the signal output terminal of the described AND logic circuit; the comparator When the voltage received by the input terminal of the comparator is greater than the threshold voltage, the output terminal of the comparator outputs a high level, and when the voltage received by the input terminal of the comparator is less than the threshold voltage, the output terminal of the comparator outputs a low level flat.

Preferably, two of the signal input terminals and one of the auxiliary signal input terminals are used as a group, so that the two signal input terminals of the same group are used to receive the same bit of two digital input signals.

Preferably, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state;

There are three resistive memristors in a low-resistance resistance state in the resistive memristors in the same row in the resistive memristor array; and, the resistive memristors in the same column in the resistive memristor array The resistor includes a resistive memristor in a low resistance state.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor.

Preferably, the resistive memristor includes: resistive memory (RRAM, Resistive Random Access Memory) or phase-change memory (PRAM, Phase-Change Random Access Memory) or ferroelectric memory (FRAM, ferroelectric Random Access Memory) or magnetic Memory (MRAM, Magnetic Random Access Memory).

In one aspect, a chip is provided, including: a top electrode metal strip, a bottom electrode metal strip and an AND logic circuit; the AND logic circuit includes: a resistive memristor array and a comparator; the resistive memristor array The positive phase input terminals of the resistance variable memristors in the same column are connected through the top electrode metal strip, so that the positive phase input terminals of the same column resistance variable memristors are used as the signal input terminals of the AND logic circuit or Auxiliary signal input terminal, the auxiliary signal input terminal is connected to a low level when working; the inverting input terminal of the same row of resistance change memristors in the resistance change memristor array is connected with one of the bottom electrode metal strips The input terminal of the comparator is connected, so that the output terminal of the comparator is used as the signal output terminal of the AND logic circuit; when the voltage received by the input terminal of the comparator is greater than the threshold voltage, the comparator's The output terminal outputs a high level, and when the voltage received by the input terminal of the comparator is lower than the threshold voltage, the output terminal of the comparator outputs a low level.

Preferably, two of the signal input terminals and one of the auxiliary signal input terminals are used as a group, so that the two signal input terminals of the same group are used to receive the same bit of two digital input signals.

Preferably, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state;

There are three resistive memristors in a low-resistance resistance state in the resistive memristors in the same row in the resistive memristor array; and, the resistive memristors in the same column in the resistive memristor array The resistor includes a resistive memristor in a low resistance state.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor.

Preferably, the resistive memristor includes: RRAM or PRAM or FRAM or MRAM.

The AND logic circuit provided by the embodiment of the present invention does not completely use the traditional MOS transistor storage device in its circuit composition, but partly uses a new type of storage device with a two-terminal structure, a resistive memristor. Memristor has the characteristics of good scalability, high storage density, low power consumption, fast reading and writing speed, strong resistance to repeated operations, and long data retention time. Therefore, while effectively saving the area occupied by the logic circuit, it realizes Programmable performance with logic circuits.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is a schematic diagram of an AND logic circuit in one embodiment of the present invention;

Fig. 2 is a schematic diagram of the resistive state setting of the resistive memristor array in one embodiment of the present invention;

Figure 3a is a graph showing the conductivity of a unipolar resistive memristor increasing with voltage;

Fig. 3b is a graph showing that the conductivity of a unipolar resistive memristor decreases with voltage;

Fig. 4 is a graph showing the conductivity of a bipolar resistive memristor as a function of voltage.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in FIG. 1 , it is a schematic diagram of an AND logic circuit in an embodiment of the present invention.

The AND logic circuit may include a resistive memristor array 10 and a comparator 11 . In the resistive memristor array 10, the positive phase input terminals of the same column resistance variable memristor 101 are connected, so that the positive phase input terminal of the same column resistance variable memristor 101 is used as the signal input terminal of the logic circuit or the auxiliary signal Input terminal, the auxiliary signal input terminal is connected to low level when working, the signal input terminal is used to receive low level or high level signal, specifically can be used to receive one of a predetermined number of N-bit digital input signals (Din) , N is a positive integer, the above-mentioned predetermined number can be set according to the specific situation, in the embodiment of the present invention, only an AND logic circuit for realizing two N-bit digital input signals to perform phase-by-phase AND operation is taken as an example for illustration, the resistance variable In the memristor array 10, the inverting input terminal of the resistive memristor 101 of the same row is connected with the input terminal of a comparator 11, so that the output terminal of the comparator 11 is used as the signal output terminal of the AND logic circuit, and the signal output The terminal is used to output a low-level or high-level signal, specifically, it can be used to output one of the N-bit digital output signals (Dout).

Wherein, the resistive memristor 101 is a two-terminal device. Referring to FIG. 1 , the upper end of the resistive memristor 101 is a non-inverting input end, and the lower end of the resistive memristor 101 is an inverting input end.

In the embodiment of the present invention, when the voltage received by the input terminal of the comparator 11 is greater than the threshold voltage, the output terminal of the comparator 11 outputs a high level, and correspondingly, the signal output terminal of the logic circuit outputs a high level, that is, a digital signal "1"; when the voltage received by the input terminal of the comparator 11 is less than the threshold voltage, the output terminal of the comparator 11 outputs a low level, correspondingly, the signal output terminal of the logic circuit outputs a low level, that is, the digital signal "0" ". Wherein, the comparator 11 can be implemented in various ways, which are not specifically limited in the present invention.

When the AND logic circuit is used to implement two N-bit digital input signals for phase-wise AND operation, the resistive memristor array 10 can form an array with N rows and 3N columns, and each column resistive memristor 101 As an input port, there are 3N input ports in total. Among them, there are 2N signal input ports of the AND logic circuit, and N auxiliary signal input ports of the AND logic circuit. The two signal input ports and one The auxiliary signal input terminals are divided into one group, and the two signal input terminals of the same group are used to receive the same bit of the two digital input signals, and the AND logic circuit in the embodiment of the present invention is used to realize the bitwise AND of the two digital input signals Functions, for example, the two digital input signals of the logic circuit are Din1 and Din2, and the digital output signal is Dout. The corresponding relationship between each bit of the digital input signal and the digital output signal can be shown in Table 1.

Table I:

Din1 A1 A2 … AN Din2 B1 B2 … BN Dout A1 and B1 A2 and B2 … AN and BN

Referring to Fig. 1, in the embodiment of the present invention, every three input ports can be divided into one group, thus each input port can be divided into N groups sequentially, and one input port in each group is used as an auxiliary signal input terminal, for example , the first input port in each group is used as the auxiliary signal input port, when working with the logic circuit, the auxiliary signal input port is connected to a low level, which can be a digital signal "0", and the remaining two input ports in each group are used as The signal input terminal is used for receiving the same bit of two digital input signals, for example, for receiving the first bit A1 of the digital input signal Din1 and the first bit B1 of the digital input signal Din2.

The resistive memristor 101 used in the embodiment of the present invention may have two resistance states: a high resistance state and a low resistance state. There are three resistive memristors in the low resistance resistance state in the same row of resistive memristors 101 in the resistive memristor array 10, and the resistive memristors in the same column in the resistive memristor array 10 There is a resistive memristor in a low-resistance resistance state in the device 101 . Specifically, the resistive memristors located in row n+1, columns 3n+1, 3n+2, and 3n+3 in the resistive memristor array 10 are in a low-resistance resistance state, where n starts from 0 value, for example, when n=0, it can be seen that the three resistive memristors located in the first row, the first column, the first row, the second column, and the first row, the third column are in a low-resistance resistance state, which can be specifically Referring to the schematic diagram of the resistance state setting of the AND logic circuit shown in FIG. 2 to set the resistance state of each resistance variable memristor, wherein the resistance change memristor whose resistance state is in a low resistance value resistance state is represented by an internal blank rectangular box, To distinguish it from the resistive memristor whose resistance state is in a high resistance state.

Before working with the logic circuit, each resistance change memristor 101 in the resistance change memristor array 10 can be programmed according to the grouping of the input ports, the above programming is about to set each resistance change memristor 101 to a low resistance value resistance state or high resistance resistance state, because the AND logic circuit of the present invention can be programmed to set the resistance variable memristor 101 to a low resistance resistance state or a high resistance resistance state, the AND logic circuit of the present invention can be called It is a programmable AND logic circuit.

The resistive memristor 101 has a resistive state memory function. When the voltage applied across the resistive memristor 101 is lower than the threshold voltage, the resistive state of the resistive memristor 101 remains unchanged. When the resistive memristor 101 When the voltage applied to both ends is higher than the threshold voltage, the resistance state of the resistive memristor 101 may change. It can be seen from the above that the working voltage of the resistive memristor 101 should be less than the threshold voltage; The voltage applied across the resistive memristor 101 during programming.

The usage modes of the AND logic circuit of the present invention may include: programming mode and working mode. When the AND logic circuit is in the programming mode, the magnitude of the programming voltage applied across the resistive memristor 101 should exceed the threshold voltage of the resistive memristor 101, because the resistive variable included in the resistive memristor array 10 The number of memristors 101 may be many, for example, when the AND logic circuit is used to realize the function of phase-wise AND of two 8-bit digital input signals, the resistive memristor array 10 has 8 auxiliary signal input terminals, 16 Signal input terminals and 8 signal output terminals, the resistance change memristor array 10 may contain 112 resistance change memristors 101, and each resistance change memristor 101 in the resistance change memristor array 10 is programmed separately The time efficiency is low, and most of the resistive memristors 101 in the resistive memristor array 10 should be set to a high-resistance resistance state, so all the resistive memristors in the resistive memristor array 10 can be set to Resistors 101 are programmed uniformly, that is, all resistive memristors 101 are in a high-resistance resistance state through unified programming, and then a small number of resistive memristors 101 that should be set to a low-resistance resistance state are individually programmed , that is to make part of the resistive memristors 101 that have been uniformly programmed be in a low-resistance resistance state through separate programming.

When performing unified programming on the above-mentioned resistive memristors 101, the input port of the logic circuit can be used as the non-inverting input terminal of the programming voltage, and the inverting input terminal of each resistive memristor 101 can be used as the inverting input terminal of the programming voltage terminal, for example, the row of reserved ports on the left side in Figure 1 can be used as the inverting input terminal of the programming voltage.

When the above-mentioned resistive memristor 101 is individually programmed, the input port of the column where the resistive memristor 101 is located can be used as the non-inverting input terminal of the programming voltage, and the inverting input terminal of the resistive memristor 101 can be used as The inverting input terminal of the programming voltage can also be used as the inverting input terminal of each resistive memristor 101 in the same row as the resistive memristor 101 in the resistive memristor array 10 as the inverting input terminal of the programming voltage For example, the reserved port in the row where the resistive memristor 101 is located in FIG. 1 can be used as the inverting input port of the programming voltage.

In the embodiment of the present invention, the resistive memristor 101 may be a unipolar resistive memristor, or a bipolar resistive memristor. When programming the resistive memristor 101, the programming voltage The size can be selected according to the unipolar or bipolar characteristics of the resistive memristor 101 .

Referring to the graphs of the conductivity of the unipolar resistive memristor as a function of voltage in FIG. 3a and FIG. and high-resistance resistance-state threshold voltage Vreset are both positive voltages. When performing unified programming on the resistance-variable memristors 101, since all resistance-variable memristors 101 are to be set to high resistance-value resistance states, the first programming The voltage V1 should satisfy: Vset>V1>Vreset, so that all the resistive memristors 101 in the resistive memristor array 10 are set to a high-resistance resistance state; When each resistive memristor 101 in a low resistance state is individually programmed, the second programming voltage V2 should satisfy: V2>Vset.

Referring to the graph of the conductivity of the bipolar memristor as a function of voltage in FIG. , the threshold voltage Vreset of the high-resistance resistance state is a negative voltage. When performing unified programming on the resistance-variable memristors 101, since all the resistance-variable memristors 101 must be set to high-resistance resistance states, the programming voltage can be set to The non-inverting input terminal of the programming voltage is grounded, and the inverting input terminal of the programming voltage is connected to the third programming voltage V3, and V3 should satisfy: V3>|Vreset|, so that all the resistive memristors 101 in the resistive memristor array 10 are is set to a high-resistance resistance state; then when each resistance-variable memristor 101 that should be set to a low-resistance resistance state in the resistance-variable memristor array 10 is individually programmed, the inverting input terminal of the programming voltage can be grounded, and the noninverting input terminal of the programming voltage is connected to the fourth programming voltage V4, and V4>Vset.

The AND logic circuit can select the corresponding function according to the needs. In addition to being used to realize the bit-wise AND of two digital input signals, it can also be used to realize the bit-wise AND of more digital input signals. Since the specific implementation methods are similar, the implementation of the present invention No more details in the example.

The resistive memristor 101 has two resistance states of high resistance and low resistance. When the resistance values in the two resistance states differ greatly, it can be regarded as that the resistive memristor 101 has two states of on and off. When the same magnitude of voltage is applied to both ends of the two resistive memristors 101 in different resistance states, there is a large current in the resistive memristor in the low resistance state, and the resistor in the high resistance state There is almost no current in the memristor, so the memristor 101 has the characteristic of selective conduction; the memristor 101 also has another important characteristic, the memristor 101 has Very good resistance consistency, that is, the resistance values of the two resistive memristors in the low resistance state are approximately equal, for example, Ron1 represents the resistance value of a low resistance resistance state resistive memristor 101, Ron2 is used to represent the resistance value of another low-resistance resistive memristor 101 , then Ron1≈Ron2. In the embodiment of the present invention, the above two characteristics of the resistive memristor 101 are utilized, and the comparator 11 is combined to realize the bitwise AND of two digital input signals.

For the convenience of description, in the embodiment of the present invention, the voltage received by the input terminal of the comparator is called the input voltage, represented by Vin, and the threshold voltage of the comparator is represented by Vref. If Vin>Vref, the output terminal of the comparator Output high level, that is, digital signal "1", if Vin<Vref, the output terminal of the comparator outputs low level, that is, digital signal "0", where Vref can be set to 1/2 of the working voltage VDD.

Below in conjunction with Fig. 2, the working principle of the present invention and the logic circuit is analyzed: when the logic circuit is in the working state, there are only three resistance memristors in each row of the resistance change memristor array in the low-resistance value resistance state (that is, the open state ), for example, in the first row of the resistive memristor array in FIG. The device is in the high-resistance resistance state (that is, the off state), so only the signal on the input port connected to the three resistive memristors in the low-resistance resistance state has an input voltage Vin of the comparator connected to the row. contribute. In the first row of the resistive memristor array, the resistive memristor 201 is connected to the auxiliary signal input terminal. When working with the logic circuit, the auxiliary signal input terminal is connected to the digital signal "0", that is, the low level VL, and the resistance variable memristor 201 is connected to the auxiliary signal input terminal. The variable memristor 202 and the resistance variable memristor 203 are connected to the signal input end, and the signal input end is used to receive the same bit of the two digital input signals that need to be ANDed. For the convenience of description, the resistive memristor 201, the resistive memristor 202 and the resistive memristor 203 and their resistance values are represented by Ron1, Ron2 and Ron3 respectively, assuming that the operating voltage of the AND logic circuit is VDD, namely High level VH=VDD, the input voltage of the comparator is represented by Vin. When the two-digit digital input signals A1 and B1 received by the signal input end are both "1", that is, high level VH, it is equivalent to connecting Ron2 and Ron3 in parallel and then connecting Ron1 in series, and Vin is the divided voltage value of Ron2//Ron3 and Ron1 , where the symbol "Ron2//Ron3" indicates the resistance of Ron2 and Ron3 in parallel, from Ron1≈Ron2≈Ron3, Ron2//Ron3≈1/2Ron1, Vin≈2/3VDD>Vref=1/2VDD, so The comparator outputs a high level, that is, a digital signal "1"; when the two input signals A1 and B1 received by the signal input end are both "0", that is, a low level VL, it is equivalent to three resistive memristors Ron1, Ron2 and Ron3 are connected in parallel, Vin≈VL≈0<Vref=1/2VDD, the comparator outputs low level, that is, digital signal "0"; When one is "1", that is, high level VH, and the other is "0", that is, low level VL, for example, the signal B1 on Ron3 is high level, and the signal A1 on Ron2 is low level, which is equivalent to Ron2 and Ron1 are connected in parallel and connected in series with Ron3. Vin is the divided voltage value of Ron1//Ron2 and Ron3. From Ron1≈Ron2≈Ron3, Ron1//Ron2≈1/2Ron1, Vin≈1/3VDD<Vref=1/2VDD, Therefore, the output of the comparator is low level, that is, the digital signal "0". It can be seen from the above that only when A1 and B1 are both at high level, the corresponding signal output terminal will output high level, so as to realize the function of bitwise ANDing the two input signals with the logic circuit. The working principle of the other rows in the logic circuit is the same as that of the first row, which will not be analyzed in this embodiment of the present invention.

In addition, the above-mentioned resistive memristor may be any one of RRAM, PRAM, FRAM and MRAM.

The AND logic circuit provided by the embodiment of the present invention does not completely use the traditional MOS transistor storage device in its circuit composition, but uses a new type of storage device with a two-terminal structure, such as a resistive memristor. Resistors have the characteristics of good scalability, high storage density, low power consumption, fast read and write speed, strong resistance to repeated operations, and long data retention time. Therefore, while effectively saving the area occupied by the logic circuit, it realizes Programmable performance with logic circuits.

The embodiment of the present invention also provides a chip, including: a top electrode metal strip, a bottom electrode metal strip and an AND logic circuit. The AND logic circuit includes: a resistive memristor array and a comparator, wherein the positive phase input terminals of the same column of resistive memristors in the resistive memristor array are connected through top electrode metal strips, so that the same column of resistive memristors The non-inverting input terminal of the memristor is used as the signal input terminal or auxiliary signal input terminal of the logic circuit, and the auxiliary signal input terminal is connected to a low level when it is working. The phase input terminal is connected to the input terminal of a comparator through the bottom electrode metal strip, so that the output terminal of the comparator is used as the signal output terminal of the AND logic circuit.

Wherein, when the voltage received by the input terminal of the comparator is greater than the threshold voltage, the output terminal of the comparator outputs a high level, and when the voltage received by the input terminal of the comparator is lower than the threshold voltage, the output terminal of the comparator outputs a low level.

Preferably, the two signal input terminals and one auxiliary signal input terminal are used as a group, so that the two signal input terminals of the same group are used to receive the same bit of the two digital input signals.

Preferably, the resistance state of the resistance variable memristor includes: a high resistance value resistance state and a low resistance value resistance state; three of the resistance change memristors in the same row in the resistance change memristor array are at low resistance A resistance variable memristor in a value resistance state; and, one of the resistance variable memristors in the same column in the resistance variable memristor array is a resistance variable memristor in a low resistance value resistance state.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor; and, the resistive memristor includes: RRAM or PRAM or FRAM or MRAM.

In the embodiment of the present invention, in order to reduce the size of the chip as much as possible, the metal strips of the top electrode and the metal strips of the bottom electrode can be vertically intersected to form a resistive memristor at each intersection point, for example, the resistive memristor is It is formed by filling the intersection of the top electrode metal strip and the bottom electrode metal strip with a resistive variable medium.

In addition, the top electrode metal strips and the bottom electrode metal strips may be respectively disposed on different metal layers in the chip, for example, two adjacent metal layers.

In the embodiment of the present invention, since the resistive memristor is compatible with the Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) process, the manufacturing process of the chip is simple.

The chip provided by the embodiment of the present invention includes a top electrode metal strip, a bottom electrode metal strip and an AND logic circuit. In its circuit configuration, traditional MOS tube storage devices are not completely used, but resistive memristors are partially used. This new type of storage device with two-terminal structure, because the resistive memristor has the characteristics of good scalability, high storage density, low power consumption, fast read and write speed, strong tolerance to repeated operations, and long data retention time, etc., Therefore, while the area occupied by the logic circuit is effectively saved, the programmable performance of the logic circuit is realized, the size of the chip is correspondingly reduced, and the performance of the chip is improved.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments of the invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present invention . Therefore, the embodiments of the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

The above descriptions are only preferred embodiments of the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. within the spirit and principles of the embodiments of the present invention are It should be included in the protection scope of the embodiments of the present invention.

Claims (8)

1. and a logical circuit, it is characterized in that, comprising: resistive memristor array and comparator;

In described resistive memristor array, the normal phase input end of same row resistive memristor is connected, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level;

Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator, to make the output of described comparator as the described signal output part with logical circuit;

When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator;

Wherein, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.

2. as claimed in claim 1 and logical circuit, it is characterized in that, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;

With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.

3. as claimed in claim 1 and logical circuit, it is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.

4. as claimed in claim 1 and logical circuit, it is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.

5. a chip, is characterized in that, comprising: top electrode bonding jumper, hearth electrode bonding jumper and and logical circuit;

Describedly to comprise with logical circuit: resistive memristor array and comparator;

In described resistive memristor array, the normal phase input end of same row resistive memristor is connected by described top electrode bonding jumper, to make the normal phase input end of described same row resistive memristor as described signal input part with logical circuit or auxiliary signal input, during described auxiliary signal input work, be connected to low level;

Inverting input with a line resistive memristor in described resistive memristor array is connected with the input of a described comparator by described hearth electrode bonding jumper, to make the output of described comparator as the described signal output part with logical circuit;

When the voltage that the input of described comparator receives is greater than threshold voltage, the output of described comparator exports high level, when the voltage that the input of described comparator receives is less than threshold voltage, and the output output low level of described comparator;

Wherein, two described signal input parts and a described auxiliary signal input as one group, to make same group two described signal input parts for receiving the same position of two digital input signals.

6. chip as claimed in claim 5, it is characterized in that, the resistance state of described resistive memristor comprises: high value resistance state and low resistance resistance state;

With there being three resistive memristors being in low resistance resistance state in the resistive memristor of a line in described resistive memristor array; And, in described resistive memristor array same row resistive memristor in have a resistive memristor being in low resistance resistance state.

7. chip as claimed in claim 5, it is characterized in that, described resistive memristor comprises: monopole type resistive memristor or ambipolar resistive memristor.

8. chip as claimed in claim 5, it is characterized in that, described resistive memristor comprises: resistance-variable storing device RRAM or phase transition storage PRAM or ferroelectric memory FRAM or magnetic memory MRAM.