CN102880467B - Cache coherence protocol verification method and multi-core processor system - Google Patents
Cache coherence protocol verification method and multi-core processor system Download PDFInfo
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- CN102880467B CN102880467B CN201210325660.8A CN201210325660A CN102880467B CN 102880467 B CN102880467 B CN 102880467B CN 201210325660 A CN201210325660 A CN 201210325660A CN 102880467 B CN102880467 B CN 102880467B
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Abstract
The present invention provides a kind of Cache coherence protocol verification method and multi-core processor system. Cache coherence protocol verification method according to the present invention comprises: arrange multiple queue in watch-dog, and each queue comprises multiple unit, not yet processes complete once asking for recording; The request that all addresses are relevant is kept in the unit of same queue according to its order entering consistency treatment parts successively; Utilize the behavior state of each unit independently tracked institute record request. The request that memory access address is relevant can be ensured the characteristic processed according to the order of sequence by the Cache coherence protocol verification method based on watch-dog according to the present invention according to Cache coherence protocol, a watch-dog is adopted the protocol level behavior of Cache consistency treatment parts precisely to be monitored, it is possible to realize the behavior precise monitoring to each request bag; By the content in adjustment watch-dog so that Cache coherence protocol verification method is applicable to the checking of various consistence agreement.
Description
Technical field
The present invention relates to field of computer technology; More specifically, the present invention relates to a kind of Cache coherence protocol verification method; In addition, the present invention also relates to a kind of multi-core processor system that have employed this Cache coherence protocol verification method.
Background technology
Along with the develop rapidly of semiconductor fabrication process, the dominant frequency of single core processor has approached the limit gradually, in order to improve the arithmetic speed of treater further, people form on-chip multi-processor (ChipMulti mono-Processor, CMP) on a single die by integrated for multiple processor core.
In CMP, the shared of single internal memory space is made the contradiction of the velocity contrast distance between treater and primary storage more outstanding by multiple processor core, therefore CMP design must adopt multistage high-speed cache (Cache), alleviates this contradiction by the storage organization of stratification. CMP system must solve the Cache consistency problem and consistency checking problem that cause therefrom. Which type of Cache consistency model and its verification method is adopted all to produce material impact by the global design of CMP and exploitation.
Cache coherence protocol, as the important component part in multinuclear treater, directly has influence on exactness design and the performance of multinuclear treater, and Cache coherence protocol checking technology becomes one of the gordian technique in multinuclear CPU design checking stage.
But, in the prior art, Cache coherence protocol treating processes and processor structure on multinuclear treater are closely related, and the checking technology of Cache coherence protocol and the content of Cache coherence protocol are closely related, do not possess ubiquity.
Therefore it is intended that the Cache coherence protocol verification method of a kind of checking being applicable to various Cache coherence protocol can be proposed.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, a kind of Cache coherence protocol verification method based on watch-dog is provided, the request that memory access address is relevant is ensured the characteristic processed according to the order of sequence by it according to consistence agreement, a watch-dog is adopted the protocol level behavior of Cache consistency treatment parts precisely to be monitored, it is possible to realize the behavior precise monitoring to each request bag; By the content in adjustment watch-dog so that Cache coherence protocol verification method is applicable to the checking of various consistence agreement.
According to the first aspect of the invention, it provides a kind of Cache coherence protocol verification method, comprising: arrange multiple queue in watch-dog, each queue comprises multiple unit, not yet processes complete once asking for recording; The request that all addresses are relevant is kept in the unit of same queue according to its order entering consistency treatment parts successively; Utilize the behavior state of each unit independently tracked institute record request.
Preferably, the input and output of on-chip multi-processor only monitored by described watch-dog, only consider situation during the normal operation of on-chip multi-processor during monitoring.
Preferably, being provided with the once request queue of 256 256 degree of depth in described watch-dog, for recording the once request that on-chip multi-processor is processing, wherein same queue is entered in the request of identical Cache line address.
Preferably, in queue, according to once asking entering order to be queued up, each request entry is also provided with a request tracking state machine by each queue, and described request follows the tracks of the disposition that state machine is used for following the tracks of request.
Preferably, a tail pointer and a real head pointer are established in each queue, and tail pointer upgrades when each new request writes, at head pointer, real head pointer is referred to that request is for adding one when terminating state.
Preferably, each queue is provided with hangs empty pointer, the empty pointer of MAQ and the empty pointer of secondary request, point to respectively be in hang state request entry, just receive the entry of MAQ request and just received the entry of secondary request.
Preferably, it is in the request entry hanging state and comprises the request entry being in address suspension state and the request entry of MAQ queue suspension state.
Preferably, the once request entering on-chip multi-processor enters watch-dog simultaneously, enters one of queue according to the Cache line address asked in watch-dog; Wherein queue assignment method is: when there being the request of same request address to be registered in certain queue, then request enters this queue, otherwise an optional queue enters in empty queue, and the address of registration request is in queue management module.
Preferably, in same queue, any request all can not surmount the request being in address suspension state or MAQ queue suspension state and exit, and any MAQ request all can not surmount MAQ request and exit, and any secondary request can not surmount secondary request and exit.
According to the second aspect of the invention, it provides a kind of multi-core processor system that have employed Cache coherence protocol verification method described according to the first aspect of the invention.
According to the present invention, multiple queue is set in watch-dog, each queue comprises multiple unit, complete once asking not yet is processed for recording, the request that all addresses are relevant is kept in the unit of same queue according to the order entering consistency treatment parts successively, the behavior state of each unit independently tracked institute record request; Request type according to record, the sequence of port signal, it is possible to judge the lifetime of a request in consistency treatment accurately, and whether correct process is. Thus, the request that memory access address is relevant can be ensured the characteristic processed according to the order of sequence by the Cache coherence protocol verification method based on watch-dog according to the present invention according to Cache coherence protocol, a watch-dog is adopted the protocol level behavior of Cache consistency treatment parts precisely to be monitored, it is possible to realize the behavior precise monitoring to each request bag; By the content in adjustment watch-dog so that Cache coherence protocol verification method is applicable to the checking of various consistence agreement.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, more easily the present invention will be had more complete understanding and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the schematic diagram of the operation of watch-dog in Cache coherence protocol verification method according to embodiments of the present invention.
Fig. 2 schematically shows the schematic diagram of the two-dimentional queue adopted according to embodiments of the present invention.
Fig. 3 schematically shows the schematic diagram of the attribute of the two-dimentional queue adopted according to embodiments of the present invention.
Fig. 4 schematically shows the schematic diagram of the waiting list adopted according to embodiments of the present invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention. Note, represent that the accompanying drawing of structure may not be draw in proportion. Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make the content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, the content of the present invention is described in detail.
The Cache coherence protocol verification method of the present invention comprises: arrange multiple queue in watch-dog, and each queue comprises multiple unit, not yet processes complete once asking for recording; The request that all addresses are relevant is kept in the unit of same queue according to its order entering consistency treatment parts successively; Utilize the behavior state of each unit independently tracked institute record request. Thus, according to the request type of record, the sequence of port signal, it is possible to judge the lifetime of a request in consistency treatment accurately, and whether correct process is.
Cache coherence protocol verification method according to embodiments of the present invention will be specifically described below.
Fig. 1 schematically shows the schematic diagram of the operation of watch-dog in Cache coherence protocol verification method according to embodiments of the present invention.
In embodiments of the present invention, the input and output of on-chip multi-processor CPM only monitored by watch-dog, monitor the exactness of CPM behavior as a black box by CPM, only consider situation when CPM normally runs during monitoring.
As shown in Figure 1, the once request queue Q0 of 256 256 degree of depth is established in watch-dog ... Q255, for recording the once request that CPM is processing, same queue is entered in the request of identical Cache line address.
Further, according to once asking entering order to be queued up, each request entry is also provided with a request tracking state machine by each queue, and the disposition that state machine is used for following the tracks of request is followed the tracks of in this request.
When once asking write, asking tracking state chance to be in initial state, request tracking state machine exports rq2, response queue output ack by tracking MAQ queue output maq, secondary request queue, answers to input resp and deposit and control input mcack and change.
The life cycle of request process in CPM identifies by request tracking state machine, when asking to have processed completely in CPM, follows the tracks of state machine and will enter termination state. It is in the request terminating state and it is invalidation request, the command information exporting interface can not be transfused to and hit.
A tail pointer and a real head pointer are established in each queue, tail pointer upgrades when each new request writes and (increases progressively 1, namely+1), at head pointer, real head pointer is referred to that request is for adding one when terminating state, request entry after real head pointer may be in termination state prior to real head pointer instruction entry, and therefore real head pointer may upgrade continuously. When tail pointer catch up with real head pointer, queue full.
In actual applications, when queue depth is 256, queue generally can not be expired; Unless extremely extreme case, now, when queue full occurs, its reason to be looked into.
Each queue is also provided with three empty head pointers, hang empty pointer, the empty pointer of MAQ and the empty pointer of secondary request, point to respectively be in hang state (address hangs or MAQ hangs) request entry, just receive the entry of MAQ request and just received the entry of secondary request.
In the present embodiment, the once request entering CPM enters watch-dog simultaneously, enters one of queue (once asking one of queue for 256) according to the Cache line address asked in watch-dog. Wherein, queue assignment method is: when there being the request of same request address to be registered in certain queue, then request enters this queue, otherwise an optional queue enters in empty queue, and the address of registration request is in queue management module.
For the effective input and output on all outside interfaces of CPM, its institute incidentally SID (SecurityIdentifiers, secure ID accords with) number is all adopted once to ask 256 entries in queue to carry out comparing complete being connected with 256. Under normal circumstances, one inputs or outputs one that has active command once can hit and only can hit in 256 �� 256 entries on direction, otherwise reports an error. Same entry may be hit in two directions simultaneously. The tracking state machine of request can process this kind of situation. In addition, if the command information passed over from interface hits certain request entry 256 queues, but state is not mated, and also to be reported an error.
In same queue, any request all can not surmount the request being in address suspension state or MAQ queue suspension state and exit, and any MAQ request all can not surmount MAQ request and exit, and any secondary request can not surmount secondary request and exit. Also it is exactly 1) do not have the request entry after hanging empty pointed and hit by any port, hanging empty pointer only asks to be draped in entry just effective, suspension status is caught by secondary request, and some CPM hangs inside cannot be reflected by secondary request, then do not check; 2) the request entry before not having the empty pointer of MAQ request is exported hit by MAQ, the empty pointer continuously effective of MAQ request, and initial value equals real head pointer, exports with MAQ and upgrades; 3) the request entry before not having the empty pointer of secondary request is exported hit by secondary request, and the empty pointer continuously effective of secondary request, initial value equals real head pointer, exports with secondary request and upgrades.
At the end of test, 256 queues should be in sky state, otherwise reports an error.
Concrete example will be described below.
Following table shows a concrete example of the structure of queue unit:
Wherein:
Such as a ReadBlk request, connect successively and monitor MAQ reading, deposit control reading response, response (ReadData has APQ), then its state ID can be successively:
Initial: 00-000000-000000-000000-000000-000000-0000
MAQ reads: 10-000000-000000-000000-000000-000000-0000
Deposit control and read response: 10-000010-100000-000000-000000-000000-0000
Response: 10-000010-100011-000000-000000-000000-0000
Fig. 2 schematically shows the schematic diagram of the two-dimentional queue adopted according to embodiments of the present invention. Fig. 3 schematically shows the schematic diagram of the attribute of two dimension queue. For each queue, all there is the attribute shown in Fig. 3.
As shown in Figure 3, as the blocking=1 of dealaddr, forbid occurring the coherent signal of dealaddr+1.
Specifically, wherein
Cacheaddr:pa [38:7], Cache is capable in memory access address;
Tailaddr: tail pointer, points to the address wanting next write;
Headaddr: head pointer, the rq1type of current position unit move after turning into complete 1;
Dealaddr: process pointer, address of last current processed request, [headaddr, dealaddr-1) and the blocking mark of unit of (dealaddr+1, tailaddr) do not allow for 1; This address can only according to from headaddr-> direction of tailaddr moves;
The condition that adds 1 of dealaddr:
The blocking mark=0 of current address
The id0.port_type of && (dealaddr, tailaddr) address unit turns into his value from 00;
Maqdeal_addr:MAQ request process pointer, this pointer indicates the position once asked that last this address MAQ asks (compare { src, sid}, memory access address subscript is equal) corresponding; This address can only according to from headaddr-> direction of tailaddr moves;
The mobile condition of maqdeal_addr:
(maqdeal_addr, tailaddr) range cells monitor corresponding MAQ request, then needing maqdeal_addr assignment is corresponding unit address value;
Rq2deal_addr: secondary request process pointer, this pointer indicates the position once asked of last this address secondary request exported (compare { src, sid}) correspondence; This address can only according to from headaddr-> direction of tailaddr moves;
The mobile condition of rq2deal_addr:
(rq2deal_addr, tailaddr) range cells monitor corresponding rq2 request, then needing rq2deal_addr assignment is corresponding unit address value;
Respdeal_addr: answer treatment pointer, this pointer indicates this address that last inputs to answer the position once asked corresponding to (compare { src, sid}); This address can only according to from respdeal_addr-> direction of tailaddr moves;
The mobile condition of respdeal_addr:
(respdeal_addr, tailaddr) range cells monitor corresponding answer, then needing respdeal_addr assignment is corresponding unit address value;
Abnormal: following condition may be set up simultaneously
1) [headaddr, dealaddr-1) and (dealaddr+1, tailaddr) scope in have the blocking value 1 of unit
2) id0.port_type of unit is had to turn into his value from 00 in (dealaddr+2, tailaddr) scope
---------------is not order with the process of Address requests
3), during the blocking=1 of dealaddr unit, there is the blocking value 1 of other unit;
4) monitor [headaddr, maqdeal_addr) request of range cells has corresponding MAQ request;
5) monitor [headaddr, rq2deal_addr) request of range cells has corresponding secondary request;
6) monitor [headaddr, respdeal_addr) request of range cells has corresponding answer;
Fig. 4 schematically shows the schematic diagram of the waiting list adopted according to embodiments of the present invention.
As shown in Figure 4, but in this queue preserve be address unrelated, return response PA3 eliminate the still unclosed request with suffix * Dvic of flow process. Unit in this queue only may hit MAQ and writes and answer, and therefore only considers the hit situation of these two kinds of signals, and hit condition is consistent with two dimension queue unit, the succession still needing to follow MAQ request process and answering, it is necessary to pointer is as follows:
Tailaddr: tail pointer, points to the address wanting next write;
Headaddr: head pointer, the rq1type of current position unit move after turning into complete 1;
Maqdeal_addr:MAQ request process pointer, this pointer indicates the position once asked that last this address MAQ asks (compare { src, sid}, memory access address subscript is equal) corresponding; This address can only according to from headaddr-> direction of tailaddr moves;
Respdeal_addr: answer treatment pointer, this pointer indicates this address that last inputs to answer the position once asked corresponding to (compare { src, sid}); This address can only according to from respdeal_addr-> direction of tailaddr moves;
Abnormal: following condition may be set up simultaneously
1) monitor [headaddr, maqdeal_addr) request of range cells has corresponding MAQ request;
2) monitor [headaddr, respdeal_addr) request of range cells has corresponding answer.
According to embodiments of the present invention, by queue mechanism, the behavior of sequence between request is monitored, ensure the correct of consistence request process sequence; Further, followed the tracks of the change of request treated state by state-tracking mechanism, ensure that the process of request meets the definition of target consistence agreement.
According to embodiments of the present invention, by the method for watch-dog, the operation of dynamic monitoring consistency treatment parts, can run random uniformity test like this, and monitor the exactness of uniformity test. Greatly simplifie writing of uniformity test, increase the intensity of consistent test.
According to another preferred embodiment of the invention, present invention also offers a kind of multi-core processor system that have employed above-mentioned Cache coherence protocol verification method.
Although it should be appreciated that the present invention with better embodiment disclose as above, but above-described embodiment and be not used to limit the present invention. For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible variations and modification, or be revised as the equivalent embodiment of equivalent variations. Therefore, every content not departing from technical solution of the present invention, the technical spirit of foundation the present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a Cache coherence protocol verification method, it is characterised in that comprising:
Arranging multiple queue in watch-dog, each queue comprises multiple unit, not yet processes complete once asking for recording;
The request that all addresses are relevant is kept in the unit of same queue according to its order entering consistency treatment parts successively;
Utilize the behavior state of each unit independently tracked institute record request;
The once request queue being provided with 256 256 degree of depth in described watch-dog, for recording the once request that on-chip multi-processor is processing, wherein same queue is entered in the request of identical Cache line address.
2. Cache coherence protocol verification method according to claim 1, it is characterised in that, the input and output of on-chip multi-processor only monitored by described watch-dog, only consider situation during the normal operation of on-chip multi-processor during monitoring.
3. Cache coherence protocol verification method according to claim 1 and 2, it is characterized in that, in queue, queue up according to once asking entering order, each request entry is also provided with a request tracking state machine by each queue, and described request follows the tracks of the disposition that state machine is used for following the tracks of request.
4. Cache coherence protocol verification method according to claim 1 and 2, it is characterized in that, a tail pointer and a real head pointer are established in each queue, and tail pointer upgrades when each new request writes, at head pointer, real head pointer is referred to that request is for adding one when terminating state.
5. Cache coherence protocol verification method according to claim 1 and 2, it is characterized in that, each queue is provided with hangs empty pointer, the empty pointer of MAQ and the empty pointer of secondary request, point to respectively be in hang state request entry, just receive the entry of MAQ request and just received the entry of secondary request.
6. Cache coherence protocol verification method according to claim 1 and 2, it is characterised in that, it is in the request entry hanging state and comprises the request entry being in address suspension state and the request entry of MAQ suspension state.
7. Cache coherence protocol verification method according to claim 1 and 2, it is characterised in that, the once request entering on-chip multi-processor enters watch-dog simultaneously, enters one of queue according to the Cache line address asked in watch-dog; Wherein queue assignment method is: when there being the request of same request address to be registered in certain queue, then request enters this queue, otherwise an optional queue enters in empty queue, and the address of registration request is in queue management module.
8. Cache coherence protocol verification method according to claim 1 and 2, it is characterized in that, in same queue, any request all can not surmount the request being in address suspension state or MAQ suspension state and exit, any MAQ request all can not surmount MAQ request and exit, and any secondary request can not surmount secondary request and exit.
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| CN104049955A (en) * | 2014-06-27 | 2014-09-17 | 浪潮(北京)电子信息产业有限公司 | Multistage cache consistency pipeline processing method and device |
| US9858190B2 (en) | 2015-01-27 | 2018-01-02 | International Business Machines Corporation | Maintaining order with parallel access data streams |
| CN110674055B (en) * | 2019-09-11 | 2023-10-03 | 上海高性能集成电路设计中心 | Cache consistency simulation verification method for component level and component joint level |
| CN111782320B (en) * | 2020-06-23 | 2023-03-24 | 上海赛昉科技有限公司 | GUI interface method for debugging cache consistency C case and electronic equipment |
| CN111611120B (en) * | 2020-06-28 | 2023-05-30 | 中国人民解放军国防科技大学 | On-chip multi-core processor Cache consistency protocol verification method, system and medium |
| CN114217809B (en) * | 2021-04-14 | 2024-04-30 | 无锡江南计算技术研究所 | Implementation method of many-core simplified Cache protocol without transverse consistency |
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