CN102867540A - Operation method for raising multiport multichannel floating body memory performance - Google Patents

Abstract

The invention, belonging to the technical field of memory, discloses an operation method for raising the performances of a multiport multichannel floating body memory, characterized in that: the multiport multichannel floating body memory disclosed herein comprises a plurality of memory cells, each memory cell is provided with n transistors, each transistor comprises a source region, a drain region, grids, and a body region arranged between the source region and the drain region, the source regions and the drain regions between adjacent transistors are mutually connected or shared, and when each transistor breakovers, a conducting channel is formed between the source and the drain of the transistor. The invention provides a solution for a multichannel embedded dynamic random memory with 90nm and under nodes, thus the operation windows, data-hold characteristics, accuracy, reliability, and other storage characteristics can be obviously improved.

Description

Method of operation for improving performance of multi-port, multi-channel floating body memory

technical field

The invention belongs to the technical field of memory, and provides an operation method for improving the storage performance of a multi-port and multi-channel memory device. the

Background technique

Multi-port, multi-channel embedded DRAM includes several storage units, each storage unit has n transistors (n is a natural number, n≥2); multi-port, multi-channel floating body memory is shown in Figure 1 , where n=2, each memory cell has 2 transistors, each transistor includes a source region, a drain region, a gate and a body region between the source region and the drain region, the source region is shared between adjacent transistors, each transistor When turned on, a conductive channel is formed between the source and drain of the transistor; each transistor has 1 word line and 1 bit line; the bit line of each transistor can be connected to an input/output port; the different memory cells The transistors are located in the same floating body, and the floating body is electrically isolated from the surrounding; the word line and bit line pairs of different transistors are independent of each other, and can be selected simultaneously or time-sharing, and then corresponding different transistors can be selected simultaneously or time-sharing, and can be selected simultaneously or separately through the corresponding port read and refresh memory operations. The refresh operation and the read operation are independent of each other and do not affect each other. The peripheral circuit can read data from the storage unit at any time to achieve high-speed reading. This device can be used as an embedded dynamic random access memory, which can significantly increase the speed of the read operation, and can meet different power consumption requirements by adjusting the frequency of the refresh operation; when used for static random access, it can greatly reduce the area of the storage unit and power consumption. Fig. 1 (a) (b) is respectively multi-port, multi-channel random access memory (n=2) storage unit sectional structure and the embodiment that is made up of static random access memory by several storage units, there are two in a storage unit 100 In the case of an N-channel metal oxide field effect transistor, there are two channels and two ports, specifically: a P-type silicon substrate 101, an N-type buried layer 102, and the upper surface of 102 is on the P-type substrate 101 At the first depth below the surface, depletion regions 103 - 104 and shallow trench isolation region 105 are formed between 101 and 102 . 106 and 107 are the heavily doped N++ type source and drain regions of the first transistor respectively, 108 and 109 are respectively the lightly doped N+ type source and drain regions of the first transistor, and 110 is the second transistor heavily doped N++ type The drain region of the second transistor heavily doped N++ type is shared with the first transistor N++ heavily doped source region 106, 111 and 112 are respectively the second transistor lightly doped N+ type source region and drain region, 108 and 109 respectively represent the lightly doped N+ type source and drain regions of the first transistor, the gate electrode 114 of the first transistor, the gate electrode 115 of the second transistor, the sidewall regions 116-117 of the first transistor, and the Sidewall regions 118-119, gate oxide layers 120-121 of the first transistor and the second transistor, a depletion region 104 is formed between the N-type source and drain regions of the first transistor and the second transistor and the P-type substrate, The STI 105, the depletion region 103, and the depletion region 104 form a floating body region 113 electrically isolated from the surroundings. The source region 106 shared by the first transistor and the second transistor is generally grounded. The first transistor and the second transistor each have a pair of word line bit line pairs, wherein the first transistor bit line BL1 is connected to the drain region 107 of the first transistor, and is connected to the first port, and the second transistor bit line BL2 is connected to the second The drain region 109 of the transistor is connected to the second port, the first word line WL1 is connected to the gate electrode 114 of the first transistor, and the second word line WL2 is connected to the gate electrode 115 of the second transistor. The first transistor heavily doped N++ type drain region 107, floating body region 113, and two transistors share N++ heavily doped source region 106 to form a parasitic transistor 122; the second transistor heavily doped N++ type drain region 110, floating body region 113, The two transistors share the N++ heavily doped source region 106 to form a parasitic transistor 123, but under the existing operating voltage, 122 and 123 are always in the off state, and the read current is only the MOS current;

The operation method of the prior art multi-port, multi-channel floating body memory is as follows:

Write 1: Apply the first voltage to the bit line of a transistor (the transistor is called a write transistor), and apply the second voltage to the word line. The value of the first voltage is greater than the second voltage, which causes hot carrier injection and makes holes Inject the floating body to reduce the threshold voltage of the transistor; or apply a third voltage to the bit line of the write transistor, and a fourth voltage to the word line, and the fourth voltage is a negative voltage, causing gate-induced barrier lowering (GIDL), making the holes Inject the floating body, lowering the threshold voltage of the transistor. the

Write 0: apply the fifth voltage to the bit line of the write transistor, the fifth voltage is a negative voltage, and the sixth voltage is applied to the word line, causing the positive bias of the floating body-drain region PN junction, extracting the holes in the floating body, and improving the transistor’s performance. threshold voltage. the

Refresh: According to the original data of the memory cell, apply the voltage required to write 0 or write 1 to the word line and bit line of the first transistor to achieve the purpose of refreshing the original data of the memory cell

Read: Apply the seventh voltage and the eighth voltage to the bit line and word line of another transistor (the tube is called the read tube), respectively, and read the current of the MOS tube through the port of the read tube, and the states of 1 and 0 correspond to Large current and small current, so as to distinguish different storage states. the

The core idea of multi-port and multi-channel memory is that write/refresh and read are independent of each other, and can be written/refreshed at any time to replenish the lost storage holes, regardless of whether the read operation is performed. However, due to the insufficient isolation of the floating body device itself of the bulk silicon substrate, the effect of writing "1" and "0" is not obvious enough. The initial storage window of the traditional reading method is very small (storage window=I1-I0), only It is 6-7μA, while the reading threshold of general sense amplifier is 5μA. This requires a higher refresh rate, and misreading is easy to occur, as shown in Figure 2. After the device is scaled down, the storage space and the number of holes will also be reduced, and the I_gap will be reduced accordingly, and the "1" and "0" states cannot be distinguished. the

Therefore, the prior art multi-port, multi-channel floating body memory itself is not sufficiently isolated, and there is a problem of small reading current difference. the

Contents of the invention

In view of this, the present invention provides a solution for a 90nm and below-node multi-channel embedded DRAM, which can significantly improve the storage characteristics of the device such as the operating window, data retention characteristics, accuracy rate, and reliability. the

In order to achieve the above object, the present invention provides a multi-port, multi-channel memory unit, comprising: several storage units; each storage unit has n transistors (n is a natural number, n≥2), and each transistor includes a source region , the drain region, the gate, and the body region between the source region and the drain region. The source region and the drain region between adjacent transistors are connected or shared. When each transistor is turned on, the source and drain of the transistor form a conductive ditch. The source-body region-drain of the transistor forms a parasitic triode, and the parasitic transistor here can be optimized to make it more sensitive to changes in the potential of the body region; each transistor has 1 pair of word lines and bit lines, that is, 1 word line and 1 word line; the bit line of each transistor can be connected to an input/output port; different transistors in the memory cell are located in the same floating body, and the floating body is electrically isolated from the surrounding; injecting carriers into the floating body through at least one port Or extract carriers, adjust the threshold voltage of the transistor to achieve the purpose of writing signals; read out the channel current of the MOS transistor and the current of the parasitic triode through one port or through multiple ports at the same time, by distinguishing the magnitude of the current, to achieve For the purpose of reading the signal, a large current represents the first data state 1, and a small current represents the second data state 0; through at least one port, the original signal in the storage unit is periodically written back to achieve the purpose of refreshing the signal. the

Preferably, the word line and bit line pairs of different transistors are independent of each other, and can be selected simultaneously or time-sharing, and then corresponding different transistors are selected simultaneously or time-sharing, and the storage operation of reading and refreshing can be performed simultaneously or time-sharing through the corresponding ports . the

In order to achieve the above object, the present invention provides a novel operating method based on multi-port and multi-channel embedded DRAM, which uses the parasitic triode effect of the memory device itself to distinguish "1" and "0" instead of simply using The body effect of MOS devices significantly improves the reading accuracy and reliability, and is also an ideal operation mode for multi-port and multi-channel floating body memories to be scaled down to 90nm and below technology nodes. the

In order to achieve the above object, the present invention also provides a multi-port, multi-channel embedded DRAM memory, comprising: a multi-port, multi-channel embedded DRAM array, which includes arrays arranged in rows and columns Multiple multi-port, multi-channel memory cells; row decoder; column decoder; sense amplifier; word line driver module; bit line driver module; logic control module, used to control the word line driver module and the Timing of the bit line driver module in read operation, write operation, data hold operation and refresh operation. the

Description of drawings

Accompanying drawing 1 is the storage cell section structure of prior art multi-port, multi-channel random access memory and the embodiment that is made up of static random access memory by several memory cells;

Accompanying drawing 2 is prior art multi-port, multi-channel RAM read/write/refresh operation relationship diagram;

Accompanying drawing 3 is according to an embodiment of the present invention multi-port, multi-channel floating body memory operating method;

Accompanying drawing 4 (a) and (b) are the principle comparative figure of traditional mode of operation and mode of operation of the present invention;

Accompanying drawing 5 is multi-port, multi-channel RAM read/write/refresh operation relationship diagram of the present invention;

Accompanying drawing 6 is a multi-port, multi-channel random access memory operation pulse diagram according to an embodiment of the present invention;

Figure 7 is a peripheral circuit diagram of a multi-port, multi-channel random access memory according to an embodiment of the present invention. the

Detailed ways

Referring to FIG. 3 , it is a method for operating a multi-port, multi-channel floating body memory according to an embodiment of the present invention. the

The device in the accompanying drawing 3 is a kind of multi-port, multi-channel embedded DRAM unit, including several storage units; each storage unit has n transistors, n is a natural number, n≥2, and each transistor includes The source region, the drain region, the gate, and the body region between the source region and the drain region. The source region and the drain region between adjacent transistors are connected or shared. When each transistor is turned on, the source and drain regions of the transistor A conductive channel is formed; the source-body region-drain of the transistor forms a parasitic triode, where the characteristics of the parasitic triode can be optimized by reasonably controlling the process parameters, thereby improving memory performance (for example, making the parasitic triode more sensitive to changes in the potential of the body region, and easier conduction, etc.). Each transistor has 1 pair of word line and bit line pair, that is, 1 word line and 1 word line; the bit line of each transistor can be connected to an input/output port;

Different transistors in the storage unit are located in the same floating body, and the floating body is electrically isolated from the surrounding; injecting carriers or extracting carriers into the floating body through at least one port, adjusting the threshold voltage of the transistor, and achieving the purpose of writing signals; Read the current between the source and drain of the transistor through one port or through multiple ports at the same time. By distinguishing the size of the current, the purpose of reading the signal is achieved. The large current represents the first data state 1, and the small current represents the second data state 0. ; Regularly write back the original signal in the storage unit through at least one port to achieve the purpose of refreshing the signal; the word line and bit line pairs of different transistors are independent of each other, and can be selected at the same time or time-sharing, and then select corresponding different transistors at the same time or time-sharing , the storage operation of reading and refreshing can be performed simultaneously or in time-sharing through the corresponding port. the

In one embodiment, n may be equal to 2, and each cell includes two MOSFETs: a first transistor and a second transistor; the drain or source of the first transistor is connected or shared with the source or drain of the second transistor , and connected to the ground; the word lines of the first transistor and the second transistor are respectively connected to the gates of the first transistor and the second transistor; the bit lines of the first transistor and the second transistor are respectively connected to the source or drain of the first transistor and The drain or source of the second transistor is connected to the input/output ports of the first transistor and the second transistor respectively. The source, body and drain regions of both transistors form a parasitic triode structure. the

In one embodiment, n may be equal to 3, and the unit includes 3 metal oxide field effect transistors: the first transistor, the second transistor and the third transistor; the first transistor, the second transistor and the third transistor The gate of the gate is respectively connected with the word line of the first transistor, the word line of the second transistor and the word line of the third transistor; the drain or source of the first transistor is connected or shared with the source or drain of the third transistor, and is connected with the ground The source or drain of the second transistor is connected or shared with the drain or source of the third transistor; the source or drain of the first transistor, the drain or source of the second transistor and the drain or source of the third transistor are respectively connected to the position of the first transistor Line, the bit line of the second transistor and the bit line of the third transistor are connected, and are respectively connected with the input/output ports of the first transistor, the second transistor, and the third transistor. The source, body and drain regions of the transistor form a parasitic triode structure. the

When reading, the word line voltage of the read tube is about 0.2-0.8V, and the bit line voltage of the read tube is about 2.0V. After the multi-port and multi-channel memory writes "1" and keeps it, the body potential increases to V _B1 due to the storage of holes in the body, so that the emitter junction of the source-body-drain parasitic transistor of the read tube is forward biased (V _BE >0) , and the voltage at the drain (collector) is about 2V, so that the electrode junction is reverse-biased, so that the source-body-drain parasitic transistor of the read tube is turned on, and the current at the drain (collector) is relatively large, as shown in Figure 3 (a ) shows; after the multi-port, multi-channel memory writes "0" and keeps, the stored holes in the body have been discharged, and the body potential V _B0 is reduced to close to 0V, so that the emitter junction of the source-body-drain parasitic transistor of the read tube reverses bias (V _BE <= 0), while the electrode junction is still reverse biased, the source-body-drain parasitic transistor of the read tube is cut off, and the drain (collector) current is very small, as shown in Figure 3(b) .

When the transistors are two N-channel metal-oxide field-effect transistors, the specific operation method is:

Write 1: Apply the first voltage to the bit line of the first transistor, and apply the second voltage to the word line. The value of the first voltage is greater than the second voltage, causing hot carrier injection, injecting holes into the floating body, and reducing the threshold of the transistor. voltage; or apply the third voltage to the bit line of the first transistor, apply the fourth voltage to the word line, and the fourth voltage is a negative voltage, which causes gate-induced barrier lowering (GIDL), injects holes into the floating body, and reduces the threshold of the transistor Voltage. the

Write 0: apply the 5th voltage to the bit line of the first transistor, the 5th voltage is a negative voltage, and the 6th voltage is applied to the word line, causing the positive bias of the PN junction of the floating body-drain region, extracting the holes in the floating body, and improving the transistor threshold voltage. the

Refresh: According to the original data of the memory cell, the voltage required for writing 0 or writing 1 is applied to the word line and the bit line of the first transistor, so as to achieve the purpose of refreshing the original data of the memory cell. the

Read: apply the 7th voltage and the 8th voltage to the bit line and the word line of the second transistor respectively. For state 1, the source-body-drain parasitic transistor of the second transistor is turned on, and the current read through the port of the second transistor is equal to The parasitic triode current of the second transistor is added to the channel current of the second transistor, and the parasitic triode of the second transistor is obviously greater than the channel current. For state 0, because the body potential is low, the emitter junction of the source-body-drain parasitic transistor of the second transistor cannot be turned on, the parasitic transistor is turned off, and the current read through the port of the second transistor is only the channel of the second transistor channel current, and because the threshold voltage of state 0 is greater than the threshold voltage of state 1, the channel current of the second transistor is smaller than the channel current of state 1 at this time, so the current difference between state 1 and state 0 is very large, and the storage state is easy distinguish. the

Selecting the word line bit line of the second transistor to perform a read operation on the memory cell and selecting the word line bit line of the first transistor to perform a refresh operation on the memory cell are independent of each other. When refresh, the refresh frequency can be high speed, medium speed, or slow speed. the

When the transistors are three N-channel metal-oxide field-effect transistors, the specific operation method is:

Write 1: Apply the 9th voltage to the bit line of the third transistor, apply the 10th voltage to the word line, the value of the 9th voltage is greater than the 10th voltage, use impact ionization to generate electron-hole pairs, trigger hot carrier injection, Inject holes into the floating body region to lower the threshold voltage of the transistor; or ground the bit line of the third transistor, apply the 11th voltage to the word line, and the 11th voltage is a negative voltage, causing gate-induced barrier lowering (GIDL), making the empty The holes are injected into the floating body region, lowering the threshold voltage of the transistor. the

Write 0: apply the 12th voltage to the bit line of the third transistor, the 12th voltage is negative, and the word line applies the 13th voltage positively, causing the positive bias of the PN junction of the floating body-drain region, extracting holes in the floating body, and improving threshold voltage of the transistor. the

Refresh: According to the original data of the memory cell, periodically apply the voltage required for writing 0 or writing 1 to the word line and bit line of the third transistor, so as to achieve the purpose of refreshing the original data of the memory cell. the

Read: Apply the 14th and 15th voltages to the bit line and the word line of the first transistor respectively. For state 1, the source-body-drain NPN parasitic transistor of the second transistor is turned on, and the current read through the port of the second transistor is The parasitic triode current of the second transistor is added to the channel current of the second transistor, and the parasitic triode of the second transistor is obviously greater than the channel current. For state 0, since the body potential is low, the source-body-drain parasitic transistor of the second transistor is turned off, the current read through the port of the second transistor is only the channel current of the second transistor, and because the threshold voltage of state 0 is greater than the threshold voltage of state 1, at this time the channel current of the second transistor is smaller than the channel current of state 1, so the current difference between state 1 and state 0 is very large, and the storage state is easy to distinguish. It is also possible to apply a positive 16th voltage higher than its source terminal voltage to the bit line of the second transistor, apply a positive 17th voltage to the word line of the second transistor, and read the channel voltage of the second transistor through the port of the second transistor. channel current and parasitic triode current, 1 or 0 states correspond to large and small currents respectively, so as to distinguish the data in the memory cell; it is also possible to simultaneously apply the voltage required for reading to the bit line and word line of the first transistor and the second transistor , while reading channel currents and parasitic transistor currents of the first transistor and the second transistor through the first transistor port and the second transistor port, and simultaneously obtaining stored data from the first transistor port and the second transistor port. the

Selecting the word line bit line of the third transistor to perform a refresh operation on the memory cell and selecting the word line bit line of the first transistor and/or the second transistor to perform a read operation on the memory cell are independent of each other, and the refresh frequency can be high speed, medium speed , slow. the

Figure 4 is a principle comparison between the traditional operation mode and the newly invented operation mode, in which Figure 4(a) is the traditional reading method, due to the body effect, the different body potentials of state "1" and state "0" correspond to different thresholds Voltage, when reading, the read tube is biased in the linear region, and the read MOS current will be different, but from Figure 4(a), it can be seen that the read current is only proportional to the square root of the body potential VB, and is not sensitive to changes in VB. Therefore, the read current difference of the conventional MOS read method is relatively small. Its formula is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; MOS</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; gap</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}\mathrm{<span\; class="notranslate">\; \&mu;</span>}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; DS"\; filenames="HSA00000531431200022.png,HSA00000531431200032.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; DS"\; filenames="HSA00000531431200022.png,HSA00000531431200032.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}}<span\; class="notranslate">\; (</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; -</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span>$

However, in the operation method of the present invention, different body potentials are used to adjust the switching state of the parasitic triode, and the relationship between the read current and the body potential VB is exponential, as shown in Figure 4(b), and the read current difference caused by the difference of VB is also more significant. Of course, the read current in the new operating mode may include both the MOS current and the triode current, so as to further increase the read current difference. Its formula is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; BJT</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; gap</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; E.</span>}}\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}}\mathrm{<span\; class="notranslate">\; cos</span>}\mathrm{<span\; class="notranslate">\; echo</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; exp</span>}\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="q\; V\; B"\; filenames="HSA00000531431200032.png"\; state="\{\{state\}\}">q</figure-callout></span><figure-callout\; id="1"\; label="q\; V\; B"\; filenames="HSA00000531431200032.png"\; state="\{\{state\}\}">\; </figure-callout>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{}{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}_{}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; exp</span>}\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="q\; V\; B"\; filenames="HSA00000531431200012.png,HSA00000531431200042.png"\; state="\{\{state\}\}">q</figure-callout></span><figure-callout\; id="0"\; label="q\; V\; B"\; filenames="HSA00000531431200012.png,HSA00000531431200042.png"\; state="\{\{state\}\}">\; </figure-callout>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{}{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}_{}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; )</span>$

The invention provides a multi-port and multi-channel floating body memory reading method with superior effect. After testing, the reading current window of the two states 1 and 0 using the method can reach 20-150 μA, which is 4 times lower than that of the traditional reading method. ~30 times, as shown in Figure 5. As the process size decreases, the base length WB of the parasitic triode will also decrease (device gate length shrinks), the current gain of the triode will increase, and according to relevant literature reports, the current difference of the traditional operation mode will decrease, so as the device The advantages of the new reading method will be more significant when the scale is reduced. the

The multi-port, multi-channel floating body memory operating voltage table of the present invention is given below, as shown in the following table:

Table I:

Voltage WL1 BL1 WL2 BL2 Source N_buried write 1 1.2V 2.0V 0 0 0 0.5 write 0 -2.0V -2.0V 0 0 0 0.5 read 0 0 0.2～0.8V 2.0V 0 0.5 Keep 0 0 0 0 0 0.5

The operating pulse is shown in Figure 6. It can be seen from the figure that the write tube is refreshed every once in a while, and the read tube can be read at any time, here 10us, 100us, 1ms, and 10ms are respectively read once. the

When reading, if the gate voltage of the read tube is biased at Vg=0.6V, there will be MOS current and multi-electrode current at the same time, but the triode current is the main one, and the MOS current difference also contributes to the total read current difference. the

Table II:

Referring to FIG. 7 , its peripheral circuit diagram includes a row decoder, a column decoder, a sense amplifier, a word line driver module, a bit line driver module, a logic control module, and the like. The function of the logic control module is to control the timing of the word line driver module and the bit line driver module in read operation, write operation, data hold operation and refresh operation. Among them, the change of the bit line voltage of the selected row and selected column can be distinguished by the sense amplifier, and compared with the reference source to obtain the readout data. The number of row addresses is input to a row decoder for selecting WWL and RWL in the array, and the column address is input to a column decoder. the

While preferred embodiments of the present invention have been shown and described, it would be obvious to those skilled in the art that many changes and modifications can be made without departing from the invention in its broader aspects. The present invention includes process optimization, design strategy and test algorithm based on the triode reading principle: for example, in the device structure, the 111 and 112 lightly doped N regions in Figure 1 are changed to heavily doped N++ regions to shorten the triode base region length, increase the current gain of the triode; properly adjust the voltage of the 102N-type buried layer when reading to obtain a larger current difference, etc. The present invention is applicable to multi-port and multi-channel floating body memory devices with various device structures, such as SOI, double gate, triple gate and ring gate structures, and includes appropriate improvement and optimization of the operation method based on the device structure characteristics. the

Claims (8)

1. a multiport, many channel transistor structures unit comprise:

Several storage unit;

Each storage unit has n transistor, wherein n is natural number, n 〉=2, each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, and during each transistor turns, form conducting channel between this transistorized source and leakage, transistorized source region, tagma and drain region form bipolar transistor structure, i.e. parasitic triode;

Each transistor has 1 pair of wordline bits line pair, i.e. 1 word line and 1 word line; Each transistorized bit line can link to each other with an input/output end port; Different crystal pipe in the storage unit is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; By at least one port injected carrier or extract charge carrier in the described buoyancy aid, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read simultaneously transistor conducting channel electric current and parasitic triode electric current by a plurality of ports by a port, by differentiating the size of electric current, reach the purpose of read output signal, large electric current represents the first data mode 1, and little electric current represents the 2nd data mode 0; Regularly original signal in the storage unit is write back by at least one port, reached the purpose of refresh signal;

The wordline bits line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding port.

2. according to claim 1 multiport, many channel transistor structures unit is characterized in that described float structure is the float structure that is formed in the monocrystalline substrate, wherein:

The float structure that is formed in the monocrystalline substrate is as follows: form the buried layer with second conduction type below the semiconductor surface with first conduction type, the buried layer upper surface is positioned at following first degree of depth of semiconductor surface, the zone that has the first conduction type above buried layer forms storage unit, isolated by shallow trench isolation region between the storage unit, the degree of depth of shallow trench isolation region is deeper than following first degree of depth of semiconductor surface; Comprise n transistor in each storage unit, wherein n is natural number, n 〉=2, each transistor comprises source region, drain region and the tagma between source region and drain region with second conduction type, transistorized source region, tagma and drain region form parasitic audion, between buried layer and tagma, between source region and tagma, form depletion region between drain region and tagma, depletion region and shallow trench isolation region surround the float structure that forms with electricity isolation all around.

3. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n transistor in the described same storage unit can all be N channel metal-oxide field effect transistor, and wherein n is natural number, n 〉=2.

4. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n can equal 2, and each unit comprises two MOS (metal-oxide-semiconductor) memory: the first transistor and transistor seconds; The source of the leakage of the first transistor or source and transistor seconds or leak links to each other or is shared, and is connected to the ground; The word line of the first transistor and transistor seconds connects respectively to the grid of the first transistor and transistor seconds; The bit line of the first transistor and transistor seconds connects respectively to the source of the first transistor or leakage or the source of leakage and transistor seconds, and be connected input/output end port with transistor seconds with the first transistor respectively and be connected, two transistorized source regions, tagma and drain regions all form parasitic audion.

5. according to claim 1 multiport, many channel transistor structures unit is characterized in that, n can equal 3, comprises 3 metal-oxide-semiconductor field effect t transistors in the described unit: the first transistor, transistor seconds and the 3rd transistor; The first transistor, transistor seconds and the 3rd transistorized grid are connected with the 3rd transistorized word line with the word line of the first transistor, the word line of transistor seconds respectively; The leakage of the first transistor or source and the 3rd transistorized source or leakage is connected or share, and be connected with ground; The source of transistor seconds or leak with the 3rd transistorized leakage or the source links to each other or shared; The leakage of the source of the first transistor or leakage, transistor seconds or source are connected with the 3rd transistorized bit line with the bit line of the first transistor, the bit line of transistor seconds respectively with the 3rd transistorized leakage or source, and be connected with the first transistor, transistor seconds, the 3rd transistorized input/output end port respectively, transistorized source region, tagma and drain region form parasitic audion.

6. the methods of storage operating of a multiport, many channel transistor structures unit, when described transistor was two N channel metal-oxide field effect transistors, described method comprised:

Write 1: the bit line to the first transistor applies the 1st voltage, and the word line applies the 2nd voltage, and the value of the 1st voltage is larger than the 2nd voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces transistorized threshold voltage; Perhaps for the bit line of the first transistor applies the 3rd voltage, the word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject buoyancy aid, reduces transistorized threshold voltage;

Write 0: for the bit line of the first transistor applies the 5th voltage, the 5th voltage is negative voltage, and the word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;

Refresh: be that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage according to the original data of storage unit, reach the purpose of refresh of memory cells legacy data;

Read: for bit line and the word line of transistor seconds applies respectively the 7th voltage and the 8th voltage, for state 1, because body potential raises, source-the body of transistor seconds-leakage NPN parasitic triode is opened, the electric current that port by transistor seconds reads is the channel current that the parasitic triode electric current of transistor seconds adds transistor seconds, and the parasitic triode of transistor seconds is obviously greater than channel current; For state 0, body potential is lower, the emitter junction of the living triode of the source-body of transistor seconds-omit can conducting, this parasitic transistor cuts out, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, this moment transistor seconds channel current less than the channel current of state 1, therefore the electric current difference of state 1 and state 0 is very large, and store status is easy to differentiate;

The wordline bits line of choosing transistor seconds carries out read operation and the wordline bits line of choosing the first transistor to storage unit, and that storage unit is carried out refresh operation is separate, when reading, can refresh, also can when not reading, refresh, the frequency that refreshes can be at a high speed, middling speed, at a slow speed.

7. the methods of storage operating of a multiport, many channel transistor structures unit, when described different components was 3 N channel metal-oxide field effect transistor transistors, its methods of storage operating comprised:

Write 1: be that the 3rd transistorized bit line applies the 9th voltage, the word line applies the 10th voltage, and the value of the 9th voltage is greater than the 10th voltage, utilize impact ionization to produce electronics---hole pair, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be the 3rd transistorized bit line ground connection, the word line applies the 11st voltage, and the 11st voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject floater area, reduces transistorized threshold voltage;

Write 0: be that the 3rd transistorized bit line applies the 12nd voltage, the 12nd voltage is negative sense, and the word line applies forward the 13rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;

Refresh: according to the original data of storage unit, regularly be that the 3rd transistorized word line and bit line apply and write 0 or write 1 required voltage, reach the purpose of refresh of memory cells legacy data;

Read: for bit line and the word line of the first transistor applies respectively the 14th and the 15th voltage, for state 1, source-the body of transistor seconds-leakage NPN parasitic triode is opened, the electric current that port by transistor seconds reads is the channel current that the parasitic triode electric current of transistor seconds adds transistor seconds, the parasitic triode of transistor seconds is obviously greater than channel current, for state 0, because bulk potential is lower, source-the body of transistor seconds-omit living triode to close, the electric current that port by transistor seconds reads only is the channel current of transistor seconds, and since the threshold voltage of state 0 greater than the threshold voltage of state 1, the channel current of transistor seconds is less than the channel current of state 1 at this moment, therefore the electric current difference of state 1 and state 0 is very large, and store status is easy to differentiate; Also can apply for the bit line of transistor seconds forward the 16th voltage that is higher than its source voltage terminal, for the word line of transistor seconds applies forward the 17th voltage, read channel current and the parasitic triode electric current of transistor seconds by the port of transistor seconds, 1 or 0 state is the large and little electric current of correspondence respectively, thereby tells the data in the storage unit; Can also be simultaneously for applying, the bit line of the first transistor and transistor seconds and word line read required voltage, read simultaneously channel current and the parasitic triode electric current of the first transistor and transistor seconds by first crystal pipe port and transistor seconds port, obtain the storage data from first crystal pipe port and transistor seconds port simultaneously;

Choosing the 3rd transistorized wordline bits line that storage unit is carried out refresh operation and the wordline bits line of choosing the first transistor and/or transistor seconds, that storage unit is carried out read operation is separate, and the frequency that refreshes can be at a high speed, middling speed, at a slow speed.

8. a multiport, many channel transistor structures is characterized in that, comprising:

Multiport, many channel transistor structures array, it comprises the arbitrary described multiport of a plurality of claims 1 to 4, the many channel transistor structures unit of arranging by the form of row and column;

Line decoder;

Column decoder;

Sense amplifier;

Word line driver module;

The bit-line drive module;

Logic control module is for controlling described word line driver module and the described bit-line drive module sequential at read operation, write operation, data maintenance operation and refresh operation.

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