CN102857202B - Integrated system with double-gate enhancement-mode HEMT (high electron mobility transistor) device - Google Patents

Abstract

The invention relates to an integrated system with a double-gate enhancement-mode HEMT (high electron mobility transistor) device. The integrated system comprises a base and a double-gate four-terminal III-nitride enhancement-mode HEMT device which is installed on the base. The device comprises a heterostructure, and a source and a drain which are electrically connected through two-dimensional electrons in the heterostructure. The heterostructure comprises a first semiconductor which is arranged between the source and the drain, a second semiconductor which is arranged on the surface of the first semiconductor, a main gate which is arranged on the surface of the second semiconductor, a dielectric layer which is formed on the surfaces of the second semiconductor and the main gate, a top gate which is arranged on the surface of the dielectric layer, a voltage division and compensation circuit which is used for enabling the main gate and the top gate to realize synchronous signal control, and the like, wherein the voltage division and compensation circuit comprises a discrete capacitor and/or discrete resistor which are arranged in series and/or in parallel between base leading-out ends which are respectively and electrically connected with the source, the main gate and the top gate. The integrated system with the double-gate enhancement-mode HEMT device has the advantages that the current collapse effect in the enhancement-mode HEMT device can be effectively controlled and the double-gate four-terminal device can be equivalently used as a three-terminal device in the integrated system.

Description

Integrated System Containing Dual Gate Enhancement Mode HEMT Devices

technical field

The present invention particularly relates to an integrated system including a dual-gate enhanced high electron mobility transistor device (Enhancement-mode High Electron Mobility Transistor, E-mode HEMT).

Background technique

Due to piezoelectric polarization and spontaneous polarization effects, a high-concentration two-dimensional electron gas can be formed on a group III nitride semiconductor heterostructure (Heterostructure), such as AlGaN/GaN. In addition, group III nitride semiconductors have high dielectric breakdown electric field strength and good high temperature resistance characteristics. HEMTs prepared by group III nitride heterostructures can not only be used in high-frequency devices, but also suitable for high-voltage, high-current power switching devices. When applied to high-power switching circuits, for the sake of simple circuit design and safety considerations, switching devices are generally required to be normally off, that is, enhanced devices (E-MODE).

When the existing group III nitride semiconductor E-MODE HEMT devices are applied to high-voltage and high-power switching devices, the drain output current often cannot keep up with the change of the gate electrode control signal, that is, the turn-on transient delay is relatively large, which is the III The "current collapse phenomenon" of the group nitride semiconductor HEMT device has a serious impact on the practicability of the device. One of the existing explanations for the "current collapse phenomenon" is the "virtual gate model". The "virtual gate model" believes that when the device is in the off state, electrons are injected into the surface or interior of the semiconductor near the gate, and are captured by surface states or defects to form a negatively charged region (virtual gate). The negatively charged virtual gate is due to Electrostatic induction will reduce the channel electron concentration in the gate-drain and gate-source connection regions. When the device is turned on, although the channel under the gate can quickly accumulate a large amount of electrons, the channel under the virtual gate will The electron concentration is low, so the output current of the drain terminal is small, and only after the virtual gate charge is fully released, the drain terminal current can return to the level of the DC state. At present, the commonly used methods to suppress "current collapse" are: surface treatment of semiconductors to reduce the surface state or interface state density; reduce the electric field intensity of the gate electrode near the drain through the field plate structure, and reduce the capture of electrons by surface states and defects. The probability of suppressing the current collapse. However, the above method of suppressing current collapse is not ideal in the case of high current and high voltage.

In order to suppress the "current collapse effect", the inventors of this case have proposed a new group III nitride E-MODE HEMT device with a stacked double gate structure, which can be enhanced by performing F ion implantation on the local area under the gate to form a negative charge region. type device, which regulates the two-dimensional electron gas in the channel through the mutual cooperation of the top gate and the main gate, so that the drain output current of the E-MODE HEMT (Enhancement-mode High Electron Mobility Transistor) It is consistent with the change of the gate terminal voltage and fundamentally suppresses the "current collapse effect". However, the new stacked double-gate HEMT device is different from the traditional source, drain, and gate three-terminal HEMT device, which is a four-terminal device. However, the current power switching devices in power electronic circuits work in the form of three terminals, and the application of four-terminal devices in the circuit requires further modification of the circuit design, which will increase the complexity of the system.

Contents of the invention

The purpose of the present invention is to provide an integration scheme, which can integrate the stacked double-gate four-terminal HEMT device into a circuit and make it work in a three-terminal form.

In order to realize the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

An integrated system including a dual-gate enhancement mode HEMT device, comprising:

base,

And, a double-gate four-terminal III-nitride enhanced HEMT device mounted on a submount, including a heterostructure and a source and drain electrically connected by a two-dimensional electron gas in the heterostructure,

Wherein, the heterogeneous structure includes:

a first semiconductor disposed between the source and the drain,

The second semiconductor is formed on the surface of the first semiconductor and has a band gap wider than that of the first semiconductor, and the surface of the second semiconductor is provided with a main gate, and the main gate is located between the source and the drain near the source side , and forms a metal-semiconductor contact with the second semiconductor,

A dielectric layer, which is formed on the surface of the second semiconductor and the main gate, and is arranged between the source and the drain, and the surface of the dielectric layer is provided with a top gate, the top gate forms a full coverage of the main gate, and at least the top gate One side edge of the gate extends to the direction of the drain or the source for a set length distance;

The source, the drain, the main gate and the top gate are respectively electrically connected to a plurality of pedestal outlets distributed on the pedestal;

Further, the integrated system containing dual-gate enhanced HEMT devices also includes:

A voltage division compensation circuit for realizing synchronous signal control of the main gate and the top gate, the voltage division compensation circuit includes series and/or parallel connections arranged on the bases electrically connected to the source, the main gate and the top gate respectively Capacitance and/or resistance between terminals.

Further, the voltage division compensation circuit includes:

At least one first capacitor and/or at least one first resistor arranged in parallel between the base terminal connected to the source and the base terminal connected to the main gate,

At least one second capacitor and/or at least one second resistor arranged in parallel between the base terminal connected to the main grid and the base terminal connected to the top gate.

As one of the preferred schemes, the source, the main gate and the top gate are respectively electrically connected to a first pedestal connection terminal, a fourth pedestal connection terminal and a third pedestal connection terminal, and the first capacitor The first resistor is connected in parallel between the first base terminal and the fourth base terminal, and the second capacitor and the second resistor are connected in parallel between the fourth base terminal and the third base terminal. between the outlets.

As one of the preferred solutions, the first capacitor, the second capacitor, the first resistor and the second resistor are all discrete components.

As one of the preferred schemes, the source and the drain are respectively connected to the low potential and the high potential of the power supply.

As one of the preferred schemes, the main gate is arranged on the surface of the F ion region of the second semiconductor, and the F ion region is a negative charge with a set thickness formed after F ion implantation in the local area of the second semiconductor. district.

Furthermore, the negative charge region is a stable negative charge region formed by implanting F ions and annealing at a certain temperature and time, thereby reducing the barrier height and depleting the two-dimensional electron gas in the channel below the gate. . The negative charge region can also be a high-temperature thermal oxidation region or a groove, etc., which can realize an enhanced device structure.

As one of the preferred solutions, both the first semiconductor and the second semiconductor are Group III nitride semiconductors.

As one of the preferred schemes, the edges on both sides of the top gate respectively extend to the direction of the source and the drain for a set length distance,

Alternatively, the top gate only extends a set length distance toward the source or the drain with one side edge thereof.

As one of the preferred solutions, when the HEMT device is in the on state, the potential of the top gate control signal is higher than the potential of the main gate control signal.

When the HEMT device is working, the amplitude and phase of the voltage applied to the main gate and the top gate are controlled by the same signal through the compensation voltage divider circuit.

As one of the preferred solutions, the drain is electrically connected to a second base terminal.

Description of drawings

Fig. 1 is the cross-sectional structure schematic diagram of double gate E-MODE HEMT of the present invention;

Figure 2 is a schematic diagram of the local structure of a common E-MODE HEMT device;

Fig. 3 is the partial structure schematic diagram of double gate E-MODE HEMT device of the present invention;

Fig. 4 is the sectional structure schematic diagram of E-MODE HEMT device in the embodiment of the present invention;

Fig. 5 is a top view structural diagram of the E-MODE HEMT device in the embodiment of the present invention.

Detailed ways

Referring to Figure 2, the reason for the current collapse of an ordinary E-MODE HEMT device is that when the device is in the off state, negative charges will accumulate on both sides of the gate metal, the AlGaN layer 3 and the insulating dielectric layer 7, and their interface, forming an interface negative charge. In the charge accumulation region 21 , due to electrostatic induction, these negative charges will reduce or even completely deplete the two-dimensional electron gas in the channel region below it, forming a channel depletion region 22 . When the device is turned on (transition from the off state to the on state), the two-dimensional electron gas in the channel under the gate rises under the control of the gate electrode voltage, but the negative charge in the charge accumulation region 21 cannot be released in time due to its deep energy level. , so the two-dimensional electron gas in the corresponding channel is still less, so the device cannot be completely turned on. As time increases, the negative charges in the interface charge accumulation region are gradually released from the deep energy level, and the corresponding electron concentration in the channel increases. , the device gradually transitions to a fully turned-on state. According to the current research results, the time for negative charges to be released from the deep energy level is about the order of microseconds to seconds.

In order to overcome the current collapse phenomenon of the above-mentioned common E-MODE HEMT device, the inventors of this case proposed a group III nitride double-gate four-terminal E-MODE HEMT device (hereinafter referred to as the double-gate E-MODE HEMT device), see Figure 1, The source 8 and the drain 9 of the device are located on both sides, and there is a gate electrode on the surface of the second semiconductor 3 (for example, AlGaN layer) near the source 8, which is called the main gate 4. The injected negative charge region 6 has an insulating dielectric layer 7 above the main gate, and another gate electrode above the insulating dielectric layer, which is called the top gate 5 . As shown in FIG. 1 , the top gate is located above the main gate, overlaps with both sides of the main gate on the vertical projection plane, and extends toward the source and drain to a certain extent. The aforementioned first semiconductor 2 (such as a GaN layer) can be disposed on a substrate 1 .

Referring to Figure 3, in the off state of the aforementioned dual-gate E-MODE HEMT device proposed by the inventor of this case, the bias of the main gate is below the threshold voltage, and a sufficiently high positive bias is applied to the top gate 5', although the main gate 4' Negative charges will also accumulate at the interface between the second semiconductor layer on both sides of the metal and the insulating medium. However, due to the effect of a sufficiently high forward bias on the top gate, the negative charges at the interface cannot completely shield the electric field of the top gate, and there is enough electric field to induce The two-dimensional electron gas in the channel region keeps the channel 23 under the charge accumulation region turned on; when the main gate voltage rises and the device transitions from the off state to the on state, the top gate voltage remains unchanged, and the charge accumulation region below the interface The channel remains on, so the device does not suffer from the delay caused by the current collapse. the

The aforementioned dual-gate E-MODE HEMT device proposed by the inventor of this case has two gate electrodes, a main gate and a top gate. When the device is applied to a circuit, the device is equivalent to working in a four-terminal mode, and it is a brand-new working mode. In the present invention, the inventor of the present case uses a voltage division compensation circuit so that the device can be integrated into the switching circuit system. With the aforementioned voltage division compensation circuit, the same pulse signal can be added to the main grid and the top grid. By adjusting the resistance and capacitance in the compensation circuit, the phase and amplitude relationship between the top grid voltage and the main grid voltage can be adjusted accordingly. Usually, the same phase can be used, and the voltage amplitude of the top gate is higher than that of the main gate voltage. When the device transitions from the off state to the on state, the high voltage of the top gate can overcome the shielding of the negative charge on the interface and force the induction below it. Sufficient two-dimensional electron gas is generated to avoid current collapse; in the off state, the low potential of the top gate can inhibit the capture of negative charges by surface states and defects, thereby inhibiting current collapse.

The technical solution of the present invention has been summarized above. In order to enable the public to understand the technical means of the present invention more clearly and implement it according to the contents of the specification, the technical solution of the present invention will be described below by taking devices based on AlGaN/GaN heterojunction as an example. Further clarification.

Referring to FIG. 4, the integrated system involved in this embodiment includes an E-MODE HEMT having the following structure, and the E-MODE HEMT includes: a first semiconductor 13 (GaN), and a second semiconductor formed on the first semiconductor 13 14 (AlGaN). The first semiconductor 13 is not intentionally doped. The n-type impurity may or may not be doped in the second semiconductor 14 . The band gap of the second semiconductor 14 is wider than that of the first semiconductor 13 . The thickness of the second semiconductor 14 is about 15 to 30 nm. The first semiconductor 13 and the second semiconductor 14 form a heterostructure, forming a two-dimensional electron gas (2DEG) at the interface.

This E-MODE HEMT has a drain 11 and a source 12 separated by a predetermined distance. The drain 11 and the source 12 extend through the second semiconductor 14 to the first semiconductor 13 and are connected to the two-dimensional electron gas in the channel. The drain electrode 11 and the source electrode 12 are made of multi-layer metals (such as: Ti/Al/Ti/Au or Ti/Al/Ni/Au, etc.) to form ohmic contacts through rapid high-temperature annealing.

The E-MODE HEMT has a negative charge region 19, which is a negative charge region formed by F ion implantation in the second semiconductor below the main gate, and can consume the two-dimensional electrons in the corresponding channel do.

The E-MODE HEMT has a main and auxiliary double gate structure, the main gate 16 is fabricated between the source and the drain, close to one end of the source, the main gate 16 is directly in contact with the surface of the second semiconductor 14, and forms a Schottky contact . The top gate 18 is disposed on the dielectric layer 17 (such as Si ₃ N ₄ ), overlaps the main gate in the vertical direction, and extends toward the source and the drain respectively.

Further, referring to FIG. 5, the E-MODE HEMT included in the integrated system is packaged in a base 30, the source 12 is connected to the base terminal 31 through a lead, and the drain 11 is connected to the base through a lead. The output terminal 32 is connected, the main grid 16 is connected to the base terminal 34 through a lead wire, and the top grid 18 is connected to the base terminal 32 through a lead wire. The voltage division compensation circuit includes resistors 26, 27 and capacitors 28, 29. By adjusting the relationship between the resistors 26, 27 and the capacitors 28, 29, the amplitude and phase of the voltage applied to the main grid and the top grid are adjusted. Resistors 26, 27 and capacitors 28, 29 are discrete components. The device works in the form of three terminals 31 , 32 , 33 in the same way as a common HEMT three-terminal device in the system.

With the foregoing design, the present invention can effectively control the "current collapse effect" in the enhanced HEMT device, and can apply the double-gate electrode four-terminal device to the system equivalent to the three-terminal device, without increasing the system's the complexity.

The above-mentioned embodiments are only to illustrate the technical conception and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. containing an integrated system for double grid enhancement mode HEMT device, comprising:

Pedestal (30),

And, be encapsulated in the double grid four end III group-III nitride enhancement mode HEMT devices on pedestal (30), comprise heterostructure and form the source electrode (12) and drain electrode (11) of electrical connection by the two-dimensional electron gas (2DEG) in heterostructure

Wherein, described heterostructure comprises:

The first semiconductor (13), it is arranged between source electrode (12) and drain electrode (11),

The second semiconductor (14), it is formed at the first semiconductor (13) surface, and there is the band gap that is wider than the first semiconductor (13), and the second semiconductor (14) surface is provided with main grid (16), described main grid (16) is positioned between source electrode (12) and drain electrode (11) near source electrode (12) one sides, and contact with the second semiconductor (14) formation metal-semiconductor

Dielectric layer (17), it is formed at the second semiconductor (14) and main grid (16) surface, and be arranged between source electrode (12) and drain electrode (11), and dielectric layer (17) surface is provided with top grid (18), described top grid (18) form all standing to main grid (16), and a lateral edge portion of at least described top grid (18) is extended preseting length distance to drain electrode (11) or source electrode (12) direction;

Described source electrode (12), drain electrode (11), main grid (16) and top grid (18) respectively be distributed in a plurality of pedestals on pedestal (30) and pick out to hold and be electrically connected;

It is characterized in that, it also comprises:

Be used for making described main grid (16) and top grid (18) to realize the dividing potential drop compensating circuit of synchronizing signal control, described dividing potential drop compensating circuit comprises series connection and/or is arranged in parallel at the each pedestal being electrically connected with source electrode (12), main grid (16) and top grid (18) respectively and picks out electric capacity and/or the resistance between end.

2. the integrated system containing double grid enhancement mode HEMT device according to claim 1, is characterized in that, described dividing potential drop compensating circuit comprises:

Be arranged in parallel the pedestal being connected with source electrode (12) pick out end and and the pedestal that is connected of main grid (16) pick out at least one the first electric capacity (28) and/or at least one the first resistance (26) between end,

Be arranged in parallel in the pedestal being connected with main grid (16) pick out end and and the pedestal that is connected of top grid (18) pick out at least one the second electric capacity (29) and/or at least one the second resistance (27) between end.

3. the integrated system containing double grid enhancement mode HEMT device according to claim 2, it is characterized in that, described source electrode (12), main grid (16) and top grid (18) pick out end (31) with one first pedestal respectively, one the 4th pedestal picks out end (34) and one the 3rd pedestal picks out end (33) electrical connection, the first electric capacity (28) and the first resistance (26) parallel connection are located at that the first pedestal picks out end (31) and the 4th pedestal picks out between end (34), described the second electric capacity (29) and the second resistance (27) parallel connection are located at that the 4th pedestal picks out end (34) and the 3rd pedestal picks out between end (33).

4. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 2-3, it is characterized in that, described the first electric capacity (28), the second electric capacity (29), the first resistance (26) and the second resistance (27) all adopt discrete device.

5. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 1-3, it is characterized in that, described source electrode (12) is connected with electronegative potential and the high potential of power supply respectively with drain electrode (11).

6. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 1-3, it is characterized in that, described main grid (16) is located at the surface, F ion district (19) of the second semiconductor (14), and described F ion district (19) is the negative charge region with setting thickness that the regional area in the second semiconductor (14) forms after F Implantation is processed.

7. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 1-3, it is characterized in that, described the first semiconductor and the second semiconductor equalizing adopt III group-III nitride semiconductor.

8. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 1-3, it is characterized in that, preseting length distance is extended to source electrode (12) and drain electrode (11) direction respectively in the both sides of the edge of described top grid (18)

Or described top grid (18) only extend preseting length distance with one lateral edge portion to source electrode (12) or drain electrode (11) direction.

9. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 1-3, it is characterized in that, at described HEMT device, during in conducting state, the current potential of described top grid (18) control signal is higher than the current potential of main grid (16) control signal.

10. according to the integrated system containing double grid enhancement mode HEMT device described in any one in claim 2-3, it is characterized in that, described drain electrode (11) picks out end (32) with one second pedestal and is electrically connected.