CN102856304A - Semiconductor chip packaging structure - Google Patents

Abstract

Disclosed is a semiconductor chip package structure, comprising at least one chip package substrate and/or at least one interposer; the chip package substrate is provided with an electromagnetic band gap; the interposer is provided with an electromagnetic band gap. The semiconductor chip packaging structure provided by the present invention can realize isolation and shielding of chip power supply noise within the ultra-wide frequency band covering low-frequency bands in the package, and simultaneously take into account the suppression of chip power supply noise within the ultra-wide frequency band.

Description

A semiconductor chip packaging structure

technical field

The invention relates to the technical field of integrated circuit packaging, in particular to a semiconductor chip packaging structure.

Background technique

With VLSI entering deep sub-micron, the technology node of CMOS process is advancing from 65nm and 45nm to 32nm and 22nm, and CMOS chips have been developing in the direction of low voltage. 2.5V to 1.8V at 90nm, the supply voltage of the core drops from 5V to 1V at 90nm. The chip power supply voltage drops all the way, which leads to the continuous reduction of the power supply noise tolerance that the chip can tolerate, and the chip is more sensitive to the interference of the power supply system in the time domain and frequency domain. On the other hand, the number of transistors contained in integrated circuit chips continues to increase, and more current is required to drive all these transistors to work. At the same time, the transient switching noise current generated by the chip increases; and the increase in transistor switching speed makes the transient switching noise current The bandwidth of the frequency distribution is wider, so the integrated circuit chip produces a larger power supply noise voltage (dV=L*dI/dt), and its frequency domain distribution is wider at the same time. That is to say, the power supply noise generated by the current integrated circuit chip will become larger and larger, and its ability to tolerate the power supply noise will become weaker and weaker.

High-frequency high-speed, multi-functional, high-performance, small size and high reliability are the development direction of electronic products. Functions realized at the module level or even the system board level in the past will be required to be realized at the packaging level. Multi-chip packaging (MCM), POP (Package-on-Package), and 3-dimensional chip stack packaging are not limited by homogeneous materials and chip process compatibility, and can achieve high-quality integration of radio frequency chips, photonic chips, MEMS sensor chips and integrated circuit chips. Density heterogeneous integration has thus received extensive attention. As the pitch of each chip in the same package is reduced to tens of microns, mutual power noise interference increases; especially when RF chips, analog chips or micro-sensing chips are included in addition to digital chips, the situation is more complicated, such as RF chips are a strong source of interference, while analog chips or micro-sensing chips are extremely sensitive to interference. Providing pure and efficient power supply for each chip in the same package has become a thorny issue. It is necessary to ensure that the power distribution network (PDN) provides low input impedance to each chip in the ultra-wideband frequency range to suppress the power supply noise generated by each chip. The power distribution network (PDN) provides sufficient isolation between each chip in the ultra-wideband frequency range to suppress the propagation and interference of power supply noise generated by each chip between chips, and at the same time provide isolation from external power supply noise to avoid external power generation of the package. The impact of power supply noise on each chip in the package.

Today, there are many studies on the power integrity of PCB main boards. The method of suppressing power supply noise propagation on PCB main boards is to adopt an electromagnetic bandgap (EBG) structure on the power/ground plane, and introduce a layer between the power/ground planes. Electromagnetic absorption ferrite material, or combine EBG structure and ferrite material, and use λ/4 periodic arrangement of through-hole pairs between power/ground planes to suppress plane resonance between power supply and ground planes, thereby suppressing PCB Power supply noise propagation on the board. Among them, the EBG structure is compatible with the PCB board process, and the EBG structure can be designed into the PCB board power distribution network (PDN). By designing a suitable EBG structure shape, a wide bandwidth isolation can be achieved, and changing the size of the EBG structure can be adjusted. Operating frequency, the electromagnetic bandgap (EBG) structure usually includes mushroom type (MT-EBG) and planar type (PT-EBG). The above electromagnetic bandgap (EBG) structure shows that when its operating frequency is in the range of 1-10GHz, the size of one cycle is about 30mm×30mm, which is larger than the area of the entire package, which is obviously not suitable for package substrates or interposer boards. .

Contents of the invention

The object of the present invention is to overcome the power supply noise interference between chips in the package and the interference of external power supply noise to the chip in the package existing in the existing integrated circuit package, and provide a structure and shielding structure for the noise isolation and shielding of the chip power supply in the package. method to improve packaged system performance. A semiconductor chip packaging structure proposed according to the present invention includes at least one chip packaging substrate and/or at least one interposer; the chip packaging substrate is provided with an electromagnetic bandgap structure; and the interposer is provided with an electromagnetic bandgap structure.

Further, at least one planar power distribution layer is provided on the packaging substrate;

The plug-in board is provided with at least one planar power distribution layer.

Further, at least two planar power distribution layers stacked on each other are provided on the packaging substrate;

The plug-in board is provided with at least two planar power distribution layers stacked on each other.

Further, the planar power distribution layer includes at least two sub-planar power distribution layers electrically insulated from each other;

Each of the sub-plane power distribution layers carries a supply voltage.

Further, the planar power distribution layer is composed of a ground plane, a power plane and a high dielectric constant dielectric layer;

The high dielectric constant dielectric layer is located between the ground plane and the associated power plane;

Each of the planar power distribution layers carries a supply voltage.

Further, the planar power distribution layer is composed of two ground planes, a power plane and two high dielectric constant dielectric layers;

The two ground planes, one power plane and two high dielectric constant dielectric layers are arranged in order according to the ground plane, high dielectric constant dielectric layer, power supply plane, high dielectric constant dielectric layer, and ground plane;

Each of the planar power distribution layers carries a supply voltage.

Further, an electromagnetic bandgap structure is provided on the planar power distribution layer or the sub-planar power distribution layer;

The shape of the electromagnetic bandgap structure includes linear, right-angled or box-shaped;

The distribution position of the electromagnetic bandgap structure on the planar power distribution layer or the sub-planar power distribution layer includes top, middle or bottom; The planar power distribution layer is divided into two areas; one area is used as a feed point area for power feed into or out of the chip package substrate or the interposer board; the other area is used as the chip package substrate or the interposer board The area of the feed point that feeds power to the chip it carries;

The area of the feeding point serving as the chip packaging substrate or the interposer board to feed power to the chip carried by it is larger than the area of the power feeding into or out of the chip packaging substrate or the interposer board. The area of the feed point;

The power plane and the ground plane of the region serving as a feed point for the chip package substrate or the interposer to feed power to the chips thereon are continuous.

Further, an electromagnetic bandgap structure is provided on the planar power distribution layer;

The shape of the electromagnetic bandgap structure includes linear, right-angled or box-shaped;

The distribution position of the electromagnetic bandgap structure on the planar power distribution layer includes top, middle or bottom; the electromagnetic bandgap structure divides the planar power distribution layer into two regions; one of the regions is used as a power feed-in or A feed point area that feeds out the chip package substrate or the interposer board; another area serves as a feed point area for the chip package substrate or the interposer board to feed power to the chip it carries;

The area of the feeding point serving as the chip packaging substrate or the interposer board to feed power to the chip carried by it is larger than the area of the power feeding into or out of the chip packaging substrate or the interposer board. The area of the feed point;

The power plane and the ground plane of the region serving as a feed point for the chip package substrate or the interposer to feed power to the chips thereon are continuous.

Further, the electromagnetic bandgap structure is part of the planar power distribution layer;

The power plane in the electromagnetic bandgap structure is a periodic structure, and the corresponding ground plane is a continuous plane or a periodic structure corresponding to the periodic structure on the power plane.

Further, the periodic structure power supply plane in the electromagnetic bandgap structure region is composed of continuous planar metal blocks arranged in a 2-dimensional period and metal wires connecting two adjacent continuous planar metal blocks;

The continuous planar metal block includes a square, a regular hexagon or a triangle;

The shape of the metal wire includes straight line, 'Z' curved line, ring or spiral;

The ground plane in the region of the electromagnetic bandgap structure is continuous or a region of the ground plane corresponding to the metal wire region on the power plane is hollow.

Further, the chip packaging substrate includes an organic material or a ceramic material;

Wherein, the organic material includes FR4, BT or PI;

The ceramic material includes LTCC or HTCC;

The chip packaging substrate includes a rigid substrate, a flexible substrate or a semi-rigid substrate;

The interposer material includes silicon, glass or ceramics.

Further, the thickness of the high dielectric constant dielectric layer is 100 nanometers to 20 microns; the dielectric constant of the high dielectric constant dielectric layer is 10-5000.

The semiconductor chip packaging structure provided by the present invention can realize isolation and shielding of chip power supply noise within the ultra-wide frequency band covering low-frequency bands in the package, and simultaneously take into account the suppression of chip power supply noise within the ultra-wide frequency band.

Description of drawings

Fig. 1 is a schematic cross-sectional view of an embodiment of a semiconductor chip packaging structure of the present invention;

2a and 2b are schematic cross-sectional views of two different composition structures of a planar power distribution layer shown in an embodiment of the present invention;

3a and 3b are schematic cross-sectional views of two different compositional structures of another planar power distribution layer shown in the embodiment of the present invention;

4 is a schematic diagram of a distributed equivalent LC two-dimensional network structure of an electromagnetic bandgap (EBG) structure shown in an embodiment of the present invention;

5a, 5b, and 5c are top views of a planar power distribution layer with an electromagnetic bandgap (EBG) structure shown in an embodiment of the present invention;

Fig. 6a is a schematic diagram of a power plane structure in which a continuous planar metal block in an electromagnetic bandgap (EBG) structural unit shown in an embodiment of the present invention is in a square shape;

Fig. 6b is a schematic diagram of a ground plane with a corresponding periodic structure corresponding to the power plane structure of Fig. 6a;

Fig. 7a is a schematic diagram of the plane structure of the power supply in which the continuous planar metal block in the electromagnetic bandgap (EBG) structural unit shown in the embodiment of the present invention is a regular hexagon;

Fig. 7b is a schematic diagram of a ground plane with a corresponding periodic structure corresponding to the power plane structure of Fig. 7a;

8 is a schematic cross-sectional view of another embodiment of a semiconductor chip packaging structure of the present invention;

9 is a schematic cross-sectional view of a third embodiment of a semiconductor chip packaging structure of the present invention;

10 is a schematic cross-sectional view of a fourth embodiment of a semiconductor chip packaging structure of the present invention;

FIG. 11 is a schematic cross-sectional view of a fifth embodiment of a semiconductor chip packaging structure of the present invention.

in,

1: PoP encapsulation;

2: PCB main board;

3: Chip packaging substrate;

4: Semiconductor chip;

5: bump;

6: solder ball;

7: BGA solder ball;

8: insert board;

9: Vertical interconnection based on conductive vias TSVs penetrating each interposer board;

10: 3D chip stack packaging;

11: conductive via (TSV);

12: power plane;

13: High dielectric constant dielectric layer;

14: ground plane;

15: Electromagnetic bandgap (EBG) structure;

16: Planar power distribution layer;

17: Periodic structure power plane in electromagnetic bandgap (EBG) structure;

18: A continuous planar metal block in a periodic structural unit on the power plane can be regarded as an equivalent capacitance part;

19: The metal wire area connecting two adjacent continuous plane metal blocks in the periodic structure on the power plane can be regarded as the equivalent inductance part;

20: The ground plane with the corresponding periodic structure in the electromagnetic bandgap (EBG) structure;

21: The hollowed out area on the ground plane corresponding to the metal wire area on the power plane;

22: Power feed-in or feed-out feed point in the chip package substrate;

23: The feed point where the chip packaging substrate feeds power to the chip on it;

24: The feed point where the power feeds into or out of the plug-in board;

25: The feed point where the plug-in board feeds power to the chips on it;

26: Metal Redistribution Layer (RDL).

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clearly described, the following will be described in conjunction with specific examples and accompanying drawings. The multiple semiconductor chip packaging structures described in the present invention can not only realize the isolation and shielding of chip power supply noise within the ultra-wide frequency band covering the low-frequency band in the package, but also take into account the impact on chip power supply noise within the ultra-wide frequency band. inhibition.

Example 1:

FIG. 1 is a schematic diagram of a double-layer chip stack package based on a chip package substrate with power noise isolation. The packaging structure includes two semiconductor chips 4 , two chip packaging substrates 3 , several bumps 5 , several solder balls 6 and several BGA solder balls 7 . The semiconductor chip 4 is directly assembled on the chip packaging substrate 3 through bumps 5 , and the two semiconductor chips 4 are connected through solder balls 6 . There are multiple layers of wiring inside the chip package substrate 3, and the BGA solder ball 7 is the external electrical connection port of the whole package. The planar power distribution layer 16 is a part of the chip packaging substrate 3 . An electromagnetic bandgap (EBG) structure 15 on the planar power distribution layer 16 divides the planar power distribution layer 16 into an O region and an O' region. The area of O' area is greater than the area of O area; the feed point 22 of the power feed-in or feed-out chip package substrate 3 is located in the O area, and the feed point 23 of the power supply from the chip package substrate 3 to the semiconductor chip 4 is located in O' area.

A planar power distribution layer 16 structure as shown in 2 a and 2 b includes a power plane 12 , a ground plane 14 and a high dielectric constant dielectric layer 13 . The power plane 12, the ground plane 14 and the high dielectric constant dielectric layer 13 sandwiched between the two planes form an electromagnetic resonant cavity. The power plane 12 in the planar power distribution layer 16 locally has a periodic structure. The ground plane 14 can be a continuous plane (as shown in FIG. 2 b ), or there can be a corresponding periodic structure on the area corresponding to the area of the periodic structure on the power plane 12 (as shown in FIG. 2 a ). The periodic structure on the power plane 12 , the corresponding ground plane 14 , and the corresponding high dielectric constant dielectric layer 13 together form an electromagnetic bandgap (EBG) structure 15 .

A planar power distribution layer as shown in 3 a and 3 b is composed of two ground planes 14 , one power plane 12 and two high dielectric constant dielectric layers 13 . Two ground planes 14, one power plane 12 and two high dielectric constant dielectric layers 13 are arranged in sequence according to the ground plane 14, high dielectric constant dielectric layer 13, power supply plane 12, high dielectric constant dielectric layer 13, and ground plane 14 . The power plane 12 has a periodic structure locally, and the ground plane 14 can be a continuous plane (as shown in FIG. 3 a ), or any ground plane 14 corresponding to the area where the periodic structure on the power plane 12 is located. There is a corresponding periodic structure on the area (not shown in the figure), and it can also be that the two ground planes 14 have corresponding periodic structures on the area corresponding to the area where the periodic structure on the power plane 12 is located (as shown in Figure 3b shown). The periodic structure on the power plane 12, the corresponding ground plane 14, and the corresponding high dielectric constant dielectric layer 13 together form an electromagnetic bandgap (EBG) structure 15 with a certain forbidden bandgap, that is, constitute a certain filtering The EBG structure 15 with isolation bandwidth, compared with the ground plane being a continuous plane, the filter isolation frequency of the EBG structure 15 formed by the latter two cases can cover lower frequencies in turn.

Since the power distribution network (PDN) mainly provides the semiconductor chip 4 with a DC constant voltage supply that does not vary with time, any voltage fluctuation that changes with time can be regarded as power supply noise, and the low-frequency end limit of the power supply noise frequency distribution of the power distribution network It is close to DC, and usually the power supply noise component in the frequency band below 1GHz also occupies a considerable proportion, so the power supply noise suppression and isolation of the power distribution network has the characteristics of covering the low frequency band, and the electromagnetic bandgap (EBG) structure15 can be regarded as an equivalent A distributed LC two-dimensional network composed of inductance L and equivalent capacitance C. As shown in FIG. 4 , the response frequency of the electromagnetic bandgap (EBG) structure 15 is related to the size of L and C. When the values of L and (or) C are increased, the response frequency can move to a lower frequency. The chip packaging substrate 3 and the interposer 8 in the integrated circuit package are limited by the size of the package, and its size is usually within 5 cm. In the chip package substrate 3 and the interposer 8, the electromagnetic bandgap ( EBG) structure 15 requires a structure with a large equivalent capacitance density and/or a large equivalent inductance density.

The structural top view of the planar power distribution layer 16 shown in FIG. 1 is shown in FIGS. 5 a , 5 b , and 5 c , but is not limited thereto. Figures 5a, 5b and 5c show top views of planar power distribution layers 16 in three different shapes of electromagnetic bandgap (EBG) structures 15: linear, rectangular and square. They are applicable not only to a planar power distribution layer 16 composed of a power plane 12 and a ground plane 14 , but also to a planar power distribution layer 16 composed of a power plane 12 and two ground planes 14 . The region where the electromagnetic bandgap (EBG) structure 15 is located is also the region where the periodic structure on the power plane 12 is located, and is also the area where the corresponding periodic structure is located on the ground plane 14 . An electromagnetic bandgap (EBG) structure 15 divides the planar power distribution layer 16 into an O region and an O' region. Due to the existence of the electromagnetic bandgap (EBG) structure 15, there is a certain bandwidth and depth of isolation between the O region and the O' region of the planar power distribution layer 16, and its isolation bandwidth and isolation depth are determined by an electromagnetic bandgap (EBG) structure The shape of the period is related to the period number of the EBG structure in the EBG structure 15 . The area of the O' region is larger than that of the O region. The power plane 12 and the ground plane 14 in the O' region are continuous metal planes. The decoupling capacitance provided by the large capacitance density and large-area O' region effectively suppresses the generation of power supply noise of the semiconductor chip 4 on the chip package substrate 3 and/or the interposer 8 . The shape of the electromagnetic bandgap (EBG) structure 15 is arbitrary, and the distribution position of the electromagnetic bandgap (EBG) structure 15 can be the top, middle, bottom, etc. on the planar power distribution layer 16, which is also arbitrary. That is to say, the shape of the O region and the O' region is arbitrary, and the specific position of the O region and the O' region on the planar power distribution layer 16 is determined by the pin distribution of the semiconductor chip 4 carried thereon, and the function and Performance decides. For example, in Figure 5a, the O region is on one side of the planar power distribution layer 16, in Figure 5b, the O region is at a corner of the planar power distribution layer 16, and in Figure 5c, the O region is living around the planar power distribution layer 16, but not limited to this.

The structure of the power plane 12 of the electromagnetic bandgap (EBG) structure 15 of the planar power distribution layer 16 shown in FIG. Limited to this; on the power plane 12 of the electromagnetic bandgap (EBG) structure 15, the continuous planar metal blocks in the electromagnetic bandgap (EBG) structural unit can be square (as shown in Figure 6a), regular hexagonal (as shown in Figure 7a ), triangular, but not limited to. A metal wire with a certain width and length is connected to two adjacent continuous plane metal blocks, only the two ends of the metal wire are in contact with the two adjacent continuous plane metal blocks to form electrical communication, and the other parts of the metal wire are in contact with the continuous plane metal blocks. There is a certain isolation gap between them, which is non-contact. That is to say, if the metal wires are removed, the different continuous planar metal blocks are electrically insulated. The shape of the metal wire can be straight line, 'Z' curved line, ring (including circular ring, rectangular ring and polygonal ring), spiral (including circular spiral, rectangular spiral and polygonal spiral), but Not limited to this. The isolation gaps between the metal wires and their segments, and the isolation gaps between the metal wires and the continuous planar metal block together constitute the metal wire area 19 . The ground plane 14 of the electromagnetic bandgap (EBG) structure 15 can be continuous, and the area corresponding to the metal wire region 19 on the power plane can also be hollow (as shown in Figures 6b and 7b, on the ground plane and on the power plane The metal wire region 19 corresponds to the hollowed out region 21 ), the filter isolation frequency of the electromagnetic bandgap (EBG) structure 15 obtained by the latter can cover lower frequencies.

The thickness of the high dielectric constant dielectric layer 13 is in the range of 100 nanometers to 20 microns. The dielectric constant of the high dielectric constant dielectric layer 13 is in the range of 10 to 5000. The thinner the high dielectric constant dielectric layer 13 is, the larger the dielectric constant is, and the forbidden band of the electromagnetic bandgap (EBG) structure 15 of the same shape and size covers a lower frequency, and the semiconductor chip packaging structure isolates and shields the power supply noise of the semiconductor chip 4 The frequency band, and the frequency band that suppresses the power supply noise of the semiconductor chip 4 can cover lower frequencies, and the frequency band is wider; the thinner the high dielectric constant dielectric layer 13, the larger the dielectric constant, for the same shape electromagnetic bandgap (EBG) structure 15. When the same working frequency band is used, the size of a single electromagnetic bandgap (EBG) structural unit is smaller, which is more suitable for small-size, high-density chip packaging.

The high dielectric constant dielectric layer material can be organic material, organic-inorganic composite material, inorganic material, ceramic material, etc., but not limited thereto;

The chip packaging substrate 3 is usually made of organic materials, including FR4, BT, PI, etc., but not limited thereto, LTCC and HTCC ceramic materials can also be used. The chip packaging substrate 3 may be a rigid substrate, a flexible substrate, or a semi-rigid substrate.

The interposer board 8 usually adopts a silicon wafer, but some interposer boards with low cost, large size and low density of via holes also use glass wafers.

When a semiconductor chip 4 requires two or more voltages for power supply due to functional and performance requirements, for example, two or more voltages are required to supply power to different functional areas of the semiconductor chip, these two or more power supply voltages The values (volts) may be the same or different. That is to say, different functional regions of the semiconductor chip may require power supplies of different voltage levels (different voltage values), for example: 5V, 3.3V, 1.8V, 1.2V and so on. It is also possible that although different functional areas of the semiconductor chip require the same power supply voltage level (voltage value), the signal types of different functional areas are different, for example: digital signal area, analog signal area, microwave radio frequency signal area, low-speed signal area , high-speed signal areas, etc., the power supplies of different functional areas need to be isolated to prevent mutual power supply noise interference. In a word, in order to prevent the power supply noise interference between the two or more voltage power supplies, it is usually necessary to have a certain degree of isolation between the above two or more voltage power supplies. Under the above circumstances, the chip packaging substrate 3 and/or the interposer 8 carrying the above-mentioned semiconductor chips 4 requiring two or more voltage power supplies may include two or more planar power distribution layers stacked on each other, each A planar power distribution layer carries a voltage supply. It is also possible to divide a planar power distribution layer 16 in the chip packaging substrate 3 and/or interposer 8 into two or more sub-planar power distribution layers electrically insulated from each other, each sub-planar power distribution layer carrying a voltage supply. It is also possible to use the above-mentioned two or more planar power distribution layers 16 stacked on each other in the chip package substrate 3 and/or the interposer 8 and two or more sub-planar power distribution layers that are co-layered with each other. combined method.

The structure of a sub-planar power distribution layer is similar to the above-mentioned planar power distribution layer 16 . The sub-planar power distribution layer has a local sub-electromagnetic bandgap (EBG) structure 15, which divides the sub-planar power distribution layer into an O sub-region and an O' sub-region, and the O' sub-region area is greater than the O sub-region area; The feed point for feeding into or out of the sub-planar power distribution layer is located in the O sub-region, and the feed point for feeding power from the sub-planar power distribution layer to the semiconductor chip 4 thereon is located in the O' sub-region.

The case of the double-layer chip stack package in this embodiment can be easily extended to the case of multi-layer chip stack package and single-layer chip package.

This embodiment only shows the case that one chip packaging substrate 3 includes one planar power distribution layer, and it can be easily extended to the case of including multiple planar power distribution layers. The chip packaging substrate 3 includes at least one planar power distribution layer composed of a power plane and a ground plane or a planar power distribution layer composed of a power plane and two ground planes. When the O area of the planar power distribution layer 16 is used as the feed area for power feed into or out of the chip package substrate 3, the feed points for power feed into or out of the chip package substrate 3 can be at the same point , can also be at different points, but they are all in the O area. And when using the O' area as the feed area where the chip package substrate 3 feeds power to the semiconductor chip 4 thereon, it not only ensures the power supply at the power supply pin of the semiconductor chip 4 on the chip package substrate 3 and the connection between the chip package substrate 3 The power supply noise isolation and shielding in the power supply room, and the decoupling capacitance provided by the large capacitance density and large-area O' area effectively suppress the generation of power supply noise of the semiconductor chip 4 on the chip packaging substrate 3 .

The structure shown in this embodiment can not only realize the ultra-wideband power supply noise isolation covering the low frequency band between two semiconductor chips, but also between the two semiconductor chips and the external power supply system, prevent the power supply noise crosstalk between the two semiconductor chips, and the external power supply system Power supply noise interferes with the two semiconductor chips, and at the same time provides ultra-wideband power decoupling for the two semiconductor chips, suppressing the generation of power supply noise of the two semiconductor chips.

Example 2

Because the thermal expansion coefficient TCE of the organic packaging substrate is much higher than that of silicon, GaAs, InP and other semiconductor materials, the mechanical stress is large, which has a serious impact on larger chips. At the same time, the thermal conductivity of the organic packaging substrate is very low, which is not conducive to the heat dissipation of the chip on it, and affects the life and reliability of the chip. In addition, whether it is an organic packaging substrate or a ceramic packaging substrate is limited by the preparation process, the line width and line spacing of the wiring are difficult to be below 50 microns, which limits the I/O (input/output) port density of the chip on it. In view of the above reasons, an interposer 8 is inserted between the chip packaging substrate 3 and the semiconductor chip 4, and the interposer 8 is used as a carrier plate for the semiconductor chip 4. The interposer 8 usually adopts a silicon chip, but some low-cost and large-sized, low-density The insert plate 8 of the via hole also can adopt glass sheet. The thickness of the insert board 8 can range from tens of microns to hundreds of microns according to different requirements. Vertical conductive vias (TSVs) 11 penetrating through the interposer board 8 realize electrical connection between the upper and lower surfaces of the interposer board 8 . The diameter of the conductive via (TSV) 11 can range from a few microns to hundreds of microns according to different requirements, and the vertical conductive via (TSV) 11 penetrating through the interposer 8 is also conducive to the heat dissipation of the semiconductor chip thereon. Since the interposer 8 can adopt integrated circuit planar technology, the line width and line distance of the wiring can reach several microns, which can effectively realize the matching transformation and redistribution of I/O port density between the chip packaging substrate and the semiconductor chip.

8 is a schematic diagram of a chip stack package structure based on a plug-in board with power supply noise isolation; the difference between this embodiment and the first embodiment is that the chip stack package structure described in this embodiment includes two semiconductor chips 4, two plug-in Board 8, several bumps 5, several conductive vias (TSV) 11 penetrating through the plug-in board 8, and two metal redistribution layers (RDL) 26 are respectively used as a part of the two plug-in boards 8, respectively located on the two plug-in boards 8 on. The semiconductor chip 4 is directly assembled on the interposer 8 through the bump 5, and each interposer 8 and the semiconductor chip 4 on it are realized vertically through the conductive through-holes (TSV) 11 distributed around each interposer 8 and penetrating each interposer 8. electrical interconnection. The planar power distribution layer 16 is a part of the metal redistribution layer (RDL) 26 on the interposer board 8, and the metal redistribution layer (RDL) 26 is a multilayer wiring. An electromagnetic bandgap (EBG) structure 15 on the planar power distribution layer 16 divides the planar power distribution layer 16 into an O region and an O' region. The area of the O' area is greater than the area of the O area; the feed point 24 of the power feed into or out of the plug-in board 8 is located in the O area, and the feed point 25 from the plug-in board 8 to the semiconductor chip 4 on which the power is fed is located in the O' area. Other parts are completely consistent with Embodiment 1.

The case of the double-layer chip stack package in this embodiment can be easily extended to the case of multi-layer chip stack package and single-layer chip package.

This embodiment only shows the case where one plug-in board 8 includes one planar power distribution layer, and it can be easily expanded to include multiple planar power distribution layers. The plug-in board 8 includes at least one planar power distribution layer composed of a power plane and a ground plane or a planar power distribution layer composed of a power plane and two ground planes. When the O region of the planar power distribution layer 16 is used as the power feed-in or feed-out area of the plug-in board 8, the feed points of the power feed-in or feed-out of the plug-in board 8 can be at the same point, or It can be at different points, but they are all in the O area. And when using the O' region as the power supply area where the plug-in board 8 feeds power to the semiconductor chip 4 on it, it not only ensures the power supply at the power supply pin of the semiconductor chip 4 on the plug-in board 8 and the power supply of the plug-in board 8. The power supply noise is isolated and shielded, and at the same time, due to the decoupling capacitance provided by the large capacitance density and the large-area O' region, the generation of power supply noise of the semiconductor chip 4 on the plug-in board 8 is effectively suppressed.

The structure shown in this embodiment can not only realize the ultra-wideband power supply noise isolation covering the low frequency band between two semiconductor chips, but also between the two semiconductor chips and the external power supply system, prevent the power supply noise crosstalk between the two semiconductor chips, and the external power supply system Power supply noise interferes with the two semiconductor chips, and at the same time provides ultra-wideband power decoupling for the two semiconductor chips, suppressing the generation of power supply noise of the two semiconductor chips.

Example 3

Fig. 9 is a schematic diagram of a POP (Package-on-Package) package structure; this embodiment is an application example of the first embodiment: the POP package structure is to stack two or more single-layer packages through solder balls 6 distributed around A stacked packaging form, the solder balls 6 play the role of mechanical support and electrical connection. The BGA solder ball 7 at the bottom of the bottom chip package substrate 3 is the electrical connection port between the entire POP package 1 and the external PCB main board 2 .

Example 4

FIG. 10 is a schematic diagram of a 3-dimensional chip stack package based on an interposer board with conductive vias. The difference between this embodiment and the first embodiment and the second embodiment is that the semiconductor chip 4 is directly assembled on the interposer 8, and the upper and lower surfaces of the interposer 8 can only have one side assembled with the semiconductor chip 4, or both sides can be assembled. There are semiconductor chips 4, and a plurality of insert boards 8 carrying semiconductor chips 4 are stacked, and then assembled on the package substrate 3 through the bumps 5 at the bottom of the bottom insert board 8, and each insert board 8 and the semiconductor chips 4 thereon pass through The conductive through-holes (TSV) 11 distributed around each interposer board and penetrating each interposer board 8 realize vertical mutual electrical connection, and the BGA solder ball 7 at the bottom of the package substrate is the external electrical connection port of the entire 3D chip stack package. Compared with the packaging structure of direct 3-dimensional stacking of chips, the direct 3-dimensional stacking of semiconductor chips requires 11 conductive vias (TSVs) to be made on the active chip, which is not only difficult, but also high in process scrap rate. The direct three-dimensional stacking of the semiconductor chips 4 requires the collaborative design of each chip, and the research and development costs are high, especially for packaging that needs to realize complex functions, which is difficult to realize. Due to the consideration of mechanical stress, the direct three-dimensional stacking of semiconductor chips 4 generally requires materials of the same material, such as Si chips, and it is difficult to directly stack semiconductor chips of heterogeneous materials. In addition, due to the limited shielding measures for direct 3-dimensional stacking of semiconductor chips 4, it is difficult to directly stack digital, analog, radio frequency, optical, MEMS, and sensor chips with different functions. Therefore, the 3D chip stack package structure based on the interposer board with conductive vias shown in this embodiment has strong practicability and wide application range. Other parts of this embodiment are completely consistent with Embodiment 1 and Embodiment 2.

Example 5

FIG. 11 is a schematic diagram of a single-chip package structure using an interposer as a chip carrier;

The difference between this embodiment and the first embodiment and the second embodiment is: a semiconductor chip 4, a chip packaging substrate 3, an interposer 8, several bumps 5, several BGA solder balls 7 and several penetration The plug-in board 8 conducts through-vias (TSVs) 11 . The semiconductor chip 4 is assembled directly on the interposer board 8 via the bumps 5 . The bumps 5 at the bottom of the interposer 8 are assembled on the package substrate 3 , and the semiconductor chip 4 and the chip package substrate 3 are vertically electrically connected to each other through conductive vias (TSVs) 11 penetrating the interposer 8 . The BGA solder balls 7 on the bottom of the chip package substrate 3 are external electrical connection ports of the package structure described in this embodiment. Insert interposer 8 between package substrate 3 and semiconductor chip 4, use interposer 8 as the carrying plate of semiconductor chip 4, help to reduce the mechanical stress of semiconductor chip 4, strengthen the heat dissipation of semiconductor chip 4, improve the heat dissipation of semiconductor chip 4 life and reliability, at the same time, the plug-in board 8 effectively realizes the matching conversion and redistribution of the I/O port density between the packaging substrate 3 and the semiconductor chip 4 . Other parts are completely consistent with Embodiment 1 and Embodiment 2.

The packaging structure of the above embodiments can be easily extended to the situation that multiple semiconductor chips are carried in one layer of packaging substrate or one layer of interposer in the packaging structure, that is, two-dimensional MCM packaging (Multi-ChipModule, referring to multiple A packaging form in which bare semiconductor chips are assembled on a carrier substrate).

In the packaging structure of the above embodiments, the direct electrical connection between the semiconductor chip and the packaging substrate directly carrying the semiconductor chip and the interposer can be a metal bump connection (such as a flip-chip form), or a metal wire connection (such as a wire- bonding form), compared with metal wire connection, metal bump connection has the advantages of short connection path, small parasitic parameters and high connection density.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (14)

1. A semiconductor chip package structure, comprising:

at least one chip package substrate and/or at least one interposer;

an electromagnetic band gap structure is arranged on the chip packaging substrate;

an electromagnetic band gap structure is arranged on the insertion plate.

2. The semiconductor chip package structure according to claim 1, wherein:

the packaging substrate is provided with at least one planar power distribution layer;

at least one planar power distribution layer is disposed on the interposer board.

3. The semiconductor chip package structure according to claim 1, wherein:

the packaging substrate is provided with at least two planar power distribution layers which are mutually stacked;

the insertion plate is provided with at least two planar power distribution layers stacked on each other.

4. A semiconductor chip package according to claim 2 or 3, wherein:

the planar power distribution layer comprises at least two sub-planar power distribution layers electrically insulated from each other;

each of the sub-planar power distribution layers carries a supply voltage.

5. A semiconductor chip package according to claim 2 or 3, wherein:

the planar power distribution layer is composed of a ground plane, a power plane and a high-dielectric-constant dielectric layer;

the high dielectric constant dielectric layer is positioned between the ground plane and the power plane;

each of the planar power distribution layers carries a supply voltage.

6. A semiconductor chip package according to claim 2 or 3, wherein:

the planar power distribution layer is composed of two ground planes, a power plane and two high-dielectric-constant dielectric layers;

the two ground planes, the power plane and the two high-dielectric-constant dielectric layers are sequentially arranged according to the ground plane, the high-dielectric-constant dielectric layer, the power plane, the high-dielectric-constant dielectric layer and the ground plane;

each of the planar power distribution layers carries a supply voltage.

7. The semiconductor chip package structure according to claim 4, wherein:

the planar power distribution layer or the sub-planar power distribution layer is provided with an electromagnetic band gap structure;

the shape of the electromagnetic band gap structure comprises a linear shape, a right-angle shape or a square frame shape;

the distribution positions of the electromagnetic bandgap structures on the planar power distribution layer or the sub-planar power distribution layer comprise a top part, a middle part or a bottom part; the electromagnetic bandgap structure divides the planar power distribution layer or the sub-planar power distribution layer into two regions; one of the areas is used as a power supply to feed in or feed out a feed point area of the chip packaging substrate or the inserting plate; the other area is used as a feeding point area for feeding power to a chip carried by the chip packaging substrate or the inserting plate;

the area of the region serving as a feeding point for feeding power to the chip carried by the chip package substrate or the interposer is larger than the area of the region serving as a feeding point for feeding power to or from the chip package substrate or the interposer;

the power plane and ground plane are continuous in the area that is the feed point to which the chip package substrate or interposer board feeds power to the chip thereon.

8. The semiconductor chip package structure according to claim 5, wherein:

the planar power distribution layer is provided with an electromagnetic band gap structure;

the shape of the electromagnetic band gap structure comprises a linear shape, a right-angle shape or a square frame shape;

the distribution positions of the electromagnetic band gap structures on the planar power distribution layer comprise a top part, a middle part or a bottom part; the electromagnetic bandgap structure divides the planar power distribution layer into two regions; one of the areas is used as a power supply to feed in or feed out a feed point area of the chip packaging substrate or the inserting plate; the other area is used as a feeding point area for feeding power to a chip carried by the chip packaging substrate or the inserting plate;

the area of the region serving as a feeding point for feeding power to the chip carried by the chip package substrate or the interposer is larger than the area of the region serving as a feeding point for feeding power to or from the chip package substrate or the interposer;

the power plane and ground plane are continuous in the area that is the feed point to which the chip package substrate or interposer board feeds power to the chip thereon.

9. The semiconductor chip package structure according to claim 6, wherein:

the planar power distribution layer is provided with an electromagnetic band gap structure;

the shape of the electromagnetic band gap structure comprises a linear shape, a right-angle shape or a square frame shape;

the distribution positions of the electromagnetic band gap structures on the planar power distribution layer comprise a top part, a middle part or a bottom part; the electromagnetic bandgap structure divides the planar power distribution layer into two regions; one of the areas is used as a power supply to feed in or feed out a feed point area of the chip packaging substrate or the inserting plate; the other area is used as a feeding point area for feeding power to a chip carried by the chip packaging substrate or the inserting plate;

the area of the region serving as a feeding point for feeding power to the chip carried by the chip package substrate or the interposer is larger than the area of the region serving as a feeding point for feeding power to or from the chip package substrate or the interposer;

the power plane and ground plane are continuous in the area that is the feed point to which the chip package substrate or interposer board feeds power to the chip thereon.

10. The semiconductor chip package structure according to claim 1, wherein:

the electromagnetic bandgap structure is part of the planar power distribution layer;

the power plane in the electromagnetic band gap structure is a periodic structure, and the corresponding ground plane is a continuous plane or a periodic structure corresponding to the periodic structure on the power plane.

11. The semiconductor chip package structure according to claim 1 or 10, wherein:

the periodic structure power supply plane in the electromagnetic band gap structure region consists of continuous planar metal blocks which are periodically arranged in a 2-dimensional mode and metal leads which are connected with two adjacent continuous planar metal blocks;

the continuous plane metal block comprises a square shape, a regular hexagon shape or a triangular shape;

the shape of the metal wire comprises a linear type, a Z-shaped bent broken line type, a ring type or a spiral type;

the ground plane in the region of the electromagnetic bandgap structure is continuous or the region of the ground plane corresponding to the region of the metal conductor on the power plane is hollow.

12. The semiconductor chip package structure according to any one of claims 1 to 3, wherein:

the chip packaging substrate comprises an organic material or a ceramic material;

wherein the organic material comprises FR4, BT, or PI;

the ceramic material comprises LTCC or HTCC;

the chip packaging substrate comprises a rigid substrate, a flexible substrate or a semi-rigid substrate;

the interposer material comprises silicon, glass, or ceramic.

13. The semiconductor chip package structure according to claim 5, wherein:

the thickness of the high dielectric constant dielectric layer is 100 nanometers to 20 micrometers; the dielectric constant of the high dielectric constant dielectric layer is 10-5000.

14. The semiconductor chip package structure according to claim 6, wherein:

the thickness of the high dielectric constant dielectric layer is 100 nanometers to 20 micrometers; the dielectric constant of the high dielectric constant dielectric layer is 10-5000.

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