CN102856260B - A kind of CMOS transistor and manufacture method thereof - Google Patents
A kind of CMOS transistor and manufacture method thereof Download PDFInfo
- Publication number
- CN102856260B CN102856260B CN201210365186.1A CN201210365186A CN102856260B CN 102856260 B CN102856260 B CN 102856260B CN 201210365186 A CN201210365186 A CN 201210365186A CN 102856260 B CN102856260 B CN 102856260B
- Authority
- CN
- China
- Prior art keywords
- photoresist
- channel region
- layer
- raceway groove
- cmos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052796 boron Inorganic materials 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 125000004437 phosphorous atom Chemical group 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000002425 crystallisation Methods 0.000 claims abstract description 6
- 230000008025 crystallization Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 69
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000002207 thermal evaporation Methods 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000006356 dehydrogenation reaction Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of manufacture method of CMOS transistor, be included in and substrate formed raceway groove, gate electrode, ohmic contact layer and source, drain electrode; The step wherein forming described raceway groove comprises: S1. is deposition of amorphous silicon layers on substrate, is then polysilicon layer by described amorphous silicon layer crystallization; Described polysilicon layer is carried out etching and form N channel region and P channel region; Correspond to described N channel region by a patterning processes and form photoresist half reserve area, form the full reserve area of photoresist corresponding to described P channel region; S3. adopt cineration technics to be removed and the photoresist of the full reserve area of reserve part photoresist by the photoresist of photoresist half reserve area, adopt the mode of ion implantation to inject phosphorus atoms, form N raceway groove; S4. peel off the photoresist on removal P channel region surface by wet method or dry method and inject boron atom formation P raceway groove.Present invention reduces complexity and the manufacturing cost of low temperature polysilicon process.
Description
Technical field
The present invention relates to low temperature polycrystalline silicon display field, be specifically related to the channel doping technique of polysilicon, particularly relate to a kind of low temperature polycrystalline silicon CMOS transistor and manufacture method thereof.
Background technology
For traditional amorphous silicon LCD display, drive IC and glass substrate are the separation designs of not accessible site, therefore, need a large amount of connectors between drive IC and glass substrate.In general, one piece of amorphous silicon LCD, the connector quantity of needs is at about 4000, and this unavoidably causes structure to become complicated, and modular manufacture cost remains high, and the less stable of panel, failure rate can be higher.Moreover the separation design of drive IC and glass substrate also allows LCD be difficult to realize lightening further, and this is all a no small strike for light and thin notebook computer and dull and stereotyped PC.By contrast, low-temperature polysilicon silicon technology does not have this problem.Drive IC can be directly integrated with glass substrate, and required connector quantity falls sharply to less than 200, and the components and parts of display sum is totally fewer than traditional a-Si amorphous silicon technology 40%.This also makes, and the structure of panel becomes very simple, stability is stronger, and in theory, the manufacturing cost of polysilicon LCD also will lower than conventional art.Meanwhile, integrated structure need not occupy additional space by drive IC, and LCD display can be done lighter and thinner,
The full name of low temperature polycrystalline silicon is " Low Temperature Poly-Silicon (LTPS, polysilicon is again referred to as p-Si, lower same) ", and it is a branch of polycrystalline silicon technology.Concerning LCD display, Polysilicon Liquid Crystal material is adopted to have many advantages, as thin film circuit can do thinner less, power consumption is lower etc.
Low-temperature polysilicon Si semiconductor has higher mobility, and can form cmos semiconductor device, thus can be applied to high aperture, high integrated TFT-LCD and AMOLED.
But cost is higher because technological process is complicated for low temperature polycrystalline silicon CMOS technology.
Summary of the invention
(1) technical problem
The invention solves low temperature polysilicon process complexity in prior art, based on the high technical problem of the display device cost of low temperature polysilicon process.
(2) technical scheme
The invention provides a kind of manufacture method of CMOS transistor, be included in and substrate formed raceway groove, gate electrode, ohmic contact layer and source, drain electrode; The step wherein forming described raceway groove comprises:
Then described amorphous silicon layer crystallization is polysilicon layer by S1. deposition of amorphous silicon layers on substrate;
S2. described polysilicon layer is carried out etching and form N channel region and P channel region; Correspond to described N channel region by a patterning processes and form photoresist half reserve area, form the full reserve area of photoresist corresponding to described P channel region;
S3. adopt cineration technics to be removed and the photoresist of the full reserve area of reserve part photoresist by the photoresist of photoresist half reserve area, adopt the mode of ion implantation to inject phosphorus atoms, form N raceway groove;
S4. peel off the photoresist of the full reserve area of removal photoresist by wet method or dry method and inject boron atom formation P raceway groove.
Optionally, the thickness of described amorphous silicon layer is
Optionally, inject phosphorus atoms in step s3 and adopt PH
3/ H
2or PCl
3/ H
2gas.
Optionally, inject boron atom in step s 4 which and adopt B
2h
6/ H
2or BF
3/ H
2gas.
Optionally, in step sl, the process being polysilicon layer by described amorphous silicon layer crystallization comprises dehydrogenation and laser irradiation.
Optionally, before deposition of amorphous silicon layers, also step S0 is comprised: on substrate: deposit thickness is
resilient coating.
Optionally, the step forming described gate electrode comprises:
S5. deposit gate oxide, then the metal of deposited monolayers or multilayer or alloy on described gate oxide, and etching forms gate electrode.
Optionally, the step forming described ohmic contact layer comprises:
S6. adopt the mode of ion implantation to inject boron atom and carry out heavy doping, form P raceway groove ohmic contact layer;
S7. after the described P raceway groove ohmic contact layer of formation, adopt the mode of ion implantation to inject phosphorus atoms and carry out heavy doping, form N raceway groove ohmic contact layer.
Optionally, form described source, the step of drain electrode comprise:
S8. deposit interlayer insulating film 10 by the mode of PECVD, then utilize a masking process to form contact hole at described interlayer insulating film;
S9. formed metal level or the alloy-layer of single or multiple lift structure by the method deposition of sputtering or thermal evaporation, then etching formation holding wire and source, drain electrode are carried out to described metal level or alloy-layer.
The present invention also provides a kind of manufacturing method of array base plate, the manufacture method of foregoing CMOS transistor, and described manufacturing method of array base plate also comprises:
S10. by PECVD method deposit passivation layer, and via hole is formed at passivation layer;
S11. pass through the method deposit transparent conductive layer of sputtering or thermal evaporation, form transparent pixels electrode by a photoetching.
(3) technique effect
Invention achieves the technique effect of a minimizing patterning processes, save the manufacturing cost of display device.
Accompanying drawing explanation
Fig. 1 represents a kind of CMOS transistor manufacturing process that one embodiment of the present invention proposes;
Fig. 2 represents a kind of CMOS transistor manufacturing process that another embodiment of the present invention proposes;
Fig. 3 represents the N channel region and P channel region that utilize etching technics to be formed;
Fig. 4 represents the mode injecting phosphorus atoms at N channel region;
Fig. 5 represents the mode injecting boron atom at P channel region;
Fig. 6 represents and utilizes grid metal to carry out the lightly doped mode of source and drain as the lightly doped mask plate of N-type;
Fig. 7 represents that adopting the mode of ion implantation to inject boron atom carries out heavily doped mode;
Fig. 8 represents that adopting the mode of ion implantation to inject phosphorus atoms carries out heavily doped mode;
Fig. 9 represents deposition interlayer insulating film, and the sectional view form contact hole on described interlayer insulating film after;
Figure 10 represents deposit transparent conductive layer, and on described transparency conducting layer, form the sectional view after transparent pixels electrode.
Embodiment
The present invention by the halftoning/gray tone technique of a composition, phosphonium ion injects and boron ion implantation technology (inject on a small quantity, do not form inversion layer in N ditch region), forms the technique of poly-silicon pattern and N-type, P type raceway groove.
Embodiment 1:
As shown in Figure 1, the present embodiment provides a kind of manufacture method of CMOS transistor, is included in and substrate is formed raceway groove, gate electrode, ohmic contact layer and source, drain electrode; The step wherein forming described raceway groove comprises:
S1. deposit thickness is on substrate 1
amorphous silicon layer 3, then dehydrogenation process is taked to described amorphous silicon, and by the techniques such as laser irradiation by amorphous silicon layer crystallization formed polysilicon layer 3, described substrate can be clear glass or quartz etc. substrate;
S2. as shown in Figure 3, described polysilicon layer is carried out etching and form N channel region and P channel region; Correspond to described N channel region formation photoresist half reserve area by a patterning processes, correspond to the full reserve area of described P channel region formation photoresist; ;
Wherein, describedly photoresist half reserve area 4 is formed by patterning processes and the full reserve area 5 of described photoresist can utilize intermediate tone mask version or gray tone mask plate to realize.
S3. adopt cineration technics to be removed and the photoresist of the full reserve area of reserve part photoresist by the photoresist of photoresist half reserve area, as shown in Figure 4, adopt the mode of ion implantation to inject phosphorus atoms, form N raceway groove 4, the gas that ion implantation adopts can be PH
3/ H
2or PCl
3/ H
2;
S4. as shown in Figure 5, peel off the photoresist of the full reserve area of removal photoresist by wet method or dry method and inject boron atom formation P raceway groove.Control boron Atom injection amount, do not form inversion channel in N-type region territory, the gas that boron Atom injection adopts can be B
2h
6/ H
2or BF
3/ H
2.
The present embodiment forms photoresist half reserve area and the full reserve area of photoresist by a composition, reach the technique effect of a minimizing patterning processes, save the manufacturing cost of cmos device, solve low temperature polysilicon process complexity in prior art, based on the high technical problem of the display device cost of low temperature polysilicon process.
Optionally, before step S1, step S0 can be carried out: on substrate by PECVD method deposit thickness be
resilient coating 2, resilient coating can select SiN
x/ SiO
2or SiO
2;
As shown in Figure 2:
Optionally, the step forming described gate electrode comprises:
S5. by the mode deposit thickness of PECVD be
gate oxide 5, gate oxide 5 can select SiN
x/ SiO
2or SiO
2; Then the metal or the alloy that pass through method deposited monolayers or multilayer on described gate oxide of sputtering or thermal evaporation form metal level, and the thickness of this metal level is about
this metal can be selected from any one of Al, Ta, Cr, Mo etc.; A photoetching is utilized to form gate electrode 6.As shown in Figure 6, gate electrode can be utilized to carry out source and drain light dope as the lightly doped mask plate of N-type and to form lightly-doped layer 7.
Optionally, the step forming described ohmic contact layer comprises:
S6. as shown in Figure 7, adopt the mode of ion implantation to inject boron atom and carry out heavy doping, form P raceway groove ohmic contact layer 8, the gas that ion implantation adopts can be B
2h
6/ H
2or BF
3/ H
2;
S7. after the described P raceway groove ohmic contact layer of formation, adopt the mode of ion implantation to inject phosphorus atoms by mask plate and carry out heavy doping, form N raceway groove ohmic contact layer 9.The gas that ion implantation adopts can be PH
3/ H
2or PCl
3/ H
2, as shown in Figure 8.
Optionally, form described source, the step of drain electrode comprise:
S8. deposit interlayer insulating film 10 by the mode of PECVD, the thickness of described interlayer insulating film 10 is
described interlayer insulating film can select SiO
2/ SiN
xor SiO
2, then utilize a masking process to form contact hole at described interlayer insulating film, as shown in Figure 9;
S9. by the metal level 11 that the metal of method deposited monolayers or multilayer on described interlayer insulating film 10 or the alloy of sputtering or thermal evaporation are formed, the thickness of this metal level is about 1000 ~
this metal can be selected from any one of Al, Ta, Cr, Mo etc.; Then a photoetching is carried out to described metal level and form holding wire and source, drain electrode.
Embodiment 2
Present embodiments provide a kind of low temperature polycrystalline silicon CMOS (complementary metal oxide semiconductors (CMOS)) device array substrate and TFT-LCD (Thin Film Transistor (TFT) LCD) manufacturing method of array base plate, it, except comprising the manufacture method of the CMOS transistor described in embodiment 1, also comprises:
S10. be about by PECVD method deposit thickness
passivation layer 12, and passivation layer formed via hole;
S11. deposit a layer thickness by sputtering or the method for thermal evaporation to be about
transparency conducting layer 13, transparency conducting layer is generally ITO or IZO, also can be other metal and metal oxide; Form transparent pixels electrode by a photoetching, its sectional view as shown in Figure 10.
Embodiment 3:
The present embodiment also provides a kind of CMOS transistor of being produced by above-mentioned manufacture method, the raceway groove comprising substrate and formed on substrate, gate electrode, ohmic contact layer and source, drain electrode; Wherein said raceway groove is included in described polysilicon layer forms N channel region, photoresist half reserve area, P channel region and corresponding P channel region corresponding to the N channel region full reserve area of photoresist by composition; By the photoresist of photoresist half reserve area being removed and the photoresist part of complete for photoresist reserve area being removed, inject phosphorus atoms to described N channel region and form N raceway groove; Boron atom formation P raceway groove is injected to P channel region by all being removed by the photoresist of complete for photoresist reserve area.
CMOS transistor manufacturing process described in the present embodiment is simple, and stable performance, can make more complicated array base palte on this basis.
Optionally, described P channel region is also provided with gate oxide and gate electrode that the metal level be made up of metal or the alloy of single or multiple lift structure or alloy-layer are etched.
Optionally, the N raceway groove ohmic contact layer 9 described metal level or alloy-layer being provided with the P raceway groove ohmic contact layer 8 injecting the formation of boron atom and being formed by injection phosphorus atoms.
Optionally, described N raceway groove ohmic contact layer is provided with interlayer insulating film 10, described interlayer insulating film is provided with contact hole, described interlayer insulating film is provided with the metal level be made up of metal or the alloy of single or multiple lift structure or alloy-layer 11 are etched source, drain electrode.
Optionally, described metal level or alloy-layer are provided with passivation layer 12, passivation layer is provided with via hole, described passivation layer is provided with transparency conducting layer 13.
Optionally, the transparent pixels electrode formed by photoetching is included at described transparency conducting layer.
The present embodiment also provides a kind of array base palte, and it comprises foregoing CMOS transistor.
The present embodiment also provides a kind of complementary mos device, and it comprises foregoing array base palte.
The present embodiment also provides a kind of Thin Film Transistor (TFT) LCD, and it comprises foregoing array base palte.
Above execution mode is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. a manufacture method for CMOS transistor, is included in and substrate is formed raceway groove, gate electrode, ohmic contact layer and source, drain electrode; The step wherein forming described raceway groove comprises:
Then described amorphous silicon layer crystallization is polysilicon layer by S1. deposition of amorphous silicon layers on substrate;
S2. described polysilicon layer is carried out etching and form N channel region and P channel region; Correspond to described N channel region by a patterning processes and form photoresist half reserve area, form the full reserve area of photoresist corresponding to described P channel region, specifically comprise: form the full reserve area of photoresist of N channel region, photoresist half reserve area, P channel region and corresponding P channel region corresponding to N channel region at described polysilicon layer by composition;
S3. adopt cineration technics to be removed and the photoresist of the full reserve area of reserve part photoresist by the photoresist of photoresist half reserve area, adopt the mode of ion implantation to inject phosphorus atoms, form N raceway groove;
S4. peel off the photoresist of the full reserve area of removal photoresist by wet method or dry method and inject boron atom formation P raceway groove.
2. the manufacture method of CMOS transistor as claimed in claim 1, be further characterized in that, the thickness of described amorphous silicon layer is
3. the manufacture method of CMOS transistor as claimed in claim 1, is further characterized in that: inject phosphorus atoms in step s3 and adopt PH
3/ H
2or PCl
3/ H
2gas.
4. the manufacture method of CMOS transistor as claimed in claim 1, is further characterized in that: inject boron atom in step s 4 which and adopt B
2h
6/ H
2or BF
3/ H
2gas.
5. the manufacture method of CMOS transistor as claimed in claim 1, be further characterized in that: in step S1, the process being polysilicon layer by described amorphous silicon layer crystallization comprises dehydrogenation and laser irradiation.
6. the manufacture method of CMOS transistor as claimed in claim 1, is further characterized in that, before deposition of amorphous silicon layers, also comprises step S0: on substrate: deposit thickness is
resilient coating.
7. the manufacture method of CMOS transistor as claimed in claim 1, be further characterized in that, the step forming described gate electrode comprises:
S5. deposit gate oxide, then the metal of deposited monolayers or multilayer or alloy on described gate oxide, and etching forms gate electrode.
8. the manufacture method of CMOS transistor as claimed in claim 7, be further characterized in that, the step forming described ohmic contact layer comprises:
S6. adopt the mode of ion implantation to inject boron atom and carry out heavy doping, form P raceway groove ohmic contact layer;
S7. after the described P raceway groove ohmic contact layer of formation, adopt the mode of ion implantation to inject phosphorus atoms and carry out heavy doping, form N raceway groove ohmic contact layer.
9. the manufacture method of CMOS transistor as claimed in claim 8, is further characterized in that, forms described source, the step of drain electrode comprises:
S8. deposit interlayer insulating film by the mode of PECVD, then utilize a masking process to form contact hole at described interlayer insulating film;
S9. formed metal level or the alloy-layer of single or multiple lift structure by the method deposition of sputtering or thermal evaporation, then etching formation holding wire and source, drain electrode are carried out to described metal level or alloy-layer.
10. a manufacturing method of array base plate, is characterized in that, comprise the manufacture method of the CMOS transistor described in any one of power 1 to power 9, described manufacturing method of array base plate also comprises:
S10. by PECVD method deposit passivation layer, and via hole is formed at passivation layer;
S11. pass through the method deposit transparent conductive layer of sputtering or thermal evaporation, form transparent pixels electrode by a photoetching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210365186.1A CN102856260B (en) | 2012-09-26 | 2012-09-26 | A kind of CMOS transistor and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210365186.1A CN102856260B (en) | 2012-09-26 | 2012-09-26 | A kind of CMOS transistor and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102856260A CN102856260A (en) | 2013-01-02 |
| CN102856260B true CN102856260B (en) | 2015-08-19 |
Family
ID=47402715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210365186.1A Active CN102856260B (en) | 2012-09-26 | 2012-09-26 | A kind of CMOS transistor and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102856260B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103123902A (en) * | 2013-01-16 | 2013-05-29 | 京东方科技集团股份有限公司 | Semiconductor layer structure, polysilicon thin film transistor, manufacturing method and display device |
| CN104701254B (en) * | 2015-03-16 | 2017-10-03 | 深圳市华星光电技术有限公司 | A kind of preparation method of low-temperature polysilicon film transistor array base palte |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490883A (en) * | 2002-09-10 | 2004-04-21 | �ձ�������ʽ���� | Thin film semiconductor device and manufacturing method thereof |
| CN1913163A (en) * | 2005-08-13 | 2007-02-14 | 三星电子株式会社 | Thin film transistor substrate and method of manufacturing the same |
| CN102683338A (en) * | 2011-09-13 | 2012-09-19 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101153297B1 (en) * | 2004-12-22 | 2012-06-07 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating the same |
-
2012
- 2012-09-26 CN CN201210365186.1A patent/CN102856260B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490883A (en) * | 2002-09-10 | 2004-04-21 | �ձ�������ʽ���� | Thin film semiconductor device and manufacturing method thereof |
| CN1913163A (en) * | 2005-08-13 | 2007-02-14 | 三星电子株式会社 | Thin film transistor substrate and method of manufacturing the same |
| CN102683338A (en) * | 2011-09-13 | 2012-09-19 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102856260A (en) | 2013-01-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9006059B2 (en) | CMOS transistor and method for fabricating the same | |
| US9252278B2 (en) | Array substrate, display device and manufacturing method thereof | |
| CN105390451A (en) | Manufacture method of low-temperature polysilicon TFT substrate | |
| CN101656233B (en) | Method for manufacturing thin film transistor substrate | |
| US20100133541A1 (en) | Thin film transistor array substrate, its manufacturing method, and liquid crystal display device | |
| KR20080093709A (en) | Thin film transistor substrate and manufacturing method thereof | |
| CN105702623B (en) | Manufacturing method of TFT array substrate | |
| US9356239B2 (en) | Method for manufacturing high resolution AMOLED backplane | |
| CN103840010B (en) | Thin film transistor, manufacturing method thereof, array substrate with thin film transistor and display device | |
| CN103311128A (en) | Self-aligning metal oxide thin film transistor and manufacturing method thereof | |
| CN107046003B (en) | Low temperature polysilicon TFT substrate and manufacturing method thereof | |
| CN104576750A (en) | Thin-film transistor structure | |
| CN105097552A (en) | Manufacturing methods of thin film transistor and array substrate, array substrate and display device | |
| CN103296058B (en) | Display panel and manufacturing method thereof | |
| CN101533779A (en) | Manufacturing method for film transistor and image display device | |
| CN103972299A (en) | A kind of thin film transistor and its manufacturing method, display substrate, display device | |
| CN103985716B (en) | Method for manufacturing thin film transistor array substrate and thin-film transistor array base-plate | |
| CN103451607A (en) | Oxide semiconductor sputtering target, thin-film transistor manufactured by the same and manufacturing method thereof | |
| KR102148957B1 (en) | Display substrate and method of manufacturing a display substrate | |
| CN1893116B (en) | Thin film transistor panel and manufacturing method thereof | |
| US10629746B2 (en) | Array substrate and manufacturing method thereof | |
| US20090039354A1 (en) | Tft array substrate and manufacturing method thereof | |
| CN102856260B (en) | A kind of CMOS transistor and manufacture method thereof | |
| WO2021120378A1 (en) | Array substrate and method for manufacturing same | |
| CN103296032B (en) | Thin-film transistor array base-plate and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |