CN102855204B

CN102855204B - A kind of access control method and system and master control borad

Info

Publication number: CN102855204B
Application number: CN201210292314.4A
Authority: CN
Inventors: 齐建明
Original assignee: Raisecom Technology Co Ltd
Current assignee: Raisecom Technology Co Ltd
Priority date: 2012-08-16
Filing date: 2012-08-16
Publication date: 2015-08-12
Anticipated expiration: 2032-08-16
Also published as: CN102855204A

Abstract

The invention provides a kind of access control method and system and master control borad.Described method, CPU and chip are positioned on different board, comprise: in CPU access chip process, if detect that first answer signal of chip to CPU access feedback cannot indicate CPU to terminate access, then described first answer signal is adjusted to and CPU can be indicated to terminate second answer signal of accessing, and the second answer signal is sent to CPU.

Description

Access control method and system and main control board

Technical Field

The present invention relates to the field of electronic circuits, and in particular, to an access control method and system and a main control board.

Background

In order to meet the requirements of different users and different services at the same time, a plurality of devices are designed with plug-in cards, aiming at carrying out resource allocation aiming at the classification of different users and services.

The Central Processing Unit (CPU) and the chip are in communication between each other, that is, the CPU and the chip are located on different boards, and two types are commonly used:

one is a multi-central processing unit (multi-CPU) performing distributed control. Usually, the main control board has a Central Processing Unit (CPU), and the service board also has a Central Processing Unit (CPU). The communication between the two uses various communication protocols for interaction.

The other is a single central processing unit (single CPU). Only the main control board has a central processing unit (single CPU), and the service board has no Central Processing Unit (CPU). The former is based on the latter type and thus knows the address range of the latter, directly accessing the latter.

The first scheme performs distributed control by using multiple central processing units (multiple CPUs). The system is huge, the protocol is complex and the cost is high.

The second scheme adopts a single central processing unit (single CPU), the system is simpler, a communication protocol between the CPUs is not needed, and the cost is low. The second solution is therefore commonly used in some small devices.

When the second scheme is adopted, the service board can be selected according to different users and different services, and may be replaced at any time, and the whole device cannot be powered off, so that the hot plug function of the service board needs to be realized.

But the plugging and unplugging of the service boards are random in time. If the service board is directly pulled out without performing effective processing when the service board is pulled out (before), and the Central Processing Unit (CPU) on the main control board accesses the pulled-out service board chip, a "crash" problem may occur due to incomplete read or write cycles of the Central Processing Unit (CPU) on the main control board, and the whole system may have disastrous results.

The general solution is: when (before) the service board is unplugged, an instruction for unplugging the service board must be manually sent to the main control board, so that the main control board stops accessing the service board, and then the service board is unplugged. The general command is not limited to a configuration command of software, and may be a control button such as a dial or a key.

But doing so would add additional configuration of software or various buttons on the hardware of the device. The equipment is complicated, the operation is complicated, and misoperation is easy to occur.

Disclosure of Invention

The invention provides an access control method and system and a main control board, and aims to solve the technical problem of how to realize hot plug of a chip.

In order to solve the technical problems, the invention provides the following technical scheme:

an access control method, wherein a CPU and a chip are positioned on different boards, the method comprises the following steps:

in the process of accessing the chip by the CPU, if the first response signal fed back by the chip to the CPU access cannot indicate the CPU to finish the access, the first response signal is adjusted to be a second response signal capable of indicating the CPU to finish the access, and the second response signal is sent to the CPU.

Wherein, the detecting that the first response signal fed back by the chip to the access of the CPU can not indicate the CPU to finish the access comprises:

after the time elapsed after the CPU sends the request to the chip reaches a preset threshold, the level of the first response signal is not changed; or,

the pulse width of the first response signal cannot enable the CPU to sample a signal for indicating the end of the access;

wherein adjusting the first response signal to a second response signal capable of instructing the CPU to end the access comprises:

after the time elapsed after the CPU sends the request to the chip reaches a preset threshold, generating a third response signal with the level opposite to that of the first response signal, and carrying out AND operation on the third response signal and the first response signal to obtain a second response signal; or,

and if the pulse width of the first response signal can not enable the CPU to sample to obtain a signal for indicating the end of the access, performing pulse widening processing on the first response signal to obtain a second response signal.

Preferably, the access control method further has the following features: the threshold is greater than a maximum normal access period.

Preferably, the access control method further has the following features: the threshold is more than 1.2 times the maximum normal access period.

Preferably, the access control method further has the following features: the time of the delay generated by the pulse widening processing on the first response signal is integral multiple of the clock period of the CPU.

Preferably, the access control method further has the following features: the time for which the pulse widening processing delays the generation of the first response signal is 2 to 5 clock cycles of the CPU.

An access control device comprising:

the adjusting module is used for adjusting a first response signal fed back by the chip to the CPU access to a second response signal capable of indicating the CPU to finish the access if the first response signal is detected not to indicate the CPU to finish the access in the process that the CPU accesses the chip;

and the sending module is used for sending the second response signal to the CPU.

The adjustment module includes:

the timing unit is connected with a clock signal line and a chip selection signal line of the CPU and used for timing the current access when detecting that the CPU sends an access request to the chip and starting the signal generating unit when the time obtained by timing exceeds a preset threshold;

the signal generating unit is connected with the timing unit and used for generating a third response signal with the level opposite to that of the first response signal;

the signal synthesis unit is connected with the signal generation unit, connected with the chip and the CPU through a response signal line of the CPU and used for carrying out AND operation on the third response signal and the high-level first response signal output by the chip to obtain a second response signal; or,

the signal synthesis unit is further used for carrying out pulse broadening processing on the first response signal to obtain a second response signal if the pulse width of the first response signal cannot enable the CPU to sample to obtain a signal for indicating ending of access;

the pulse width of the first reply signal does not enable the CPU to sample a signal indicating the end of the access.

Preferably, the access control device further has the following features: the threshold used by the timing unit is greater than the maximum normal access period.

Preferably, the access control device further has the following features: the threshold is more than 1.2 times the maximum normal access period.

Preferably, the access control device further has the following features: and a response signal wire between the signal synthesis unit and the chip is connected with a pull-up resistor.

Preferably, the access control device further has the following features: the adjustment module comprises one or more asynchronous zero clearing units, wherein:

the asynchronous zero clearing unit is connected with a bus of the CPU, connected with the chip and the CPU through a response signal line of the CPU and used for performing asynchronous zero clearing processing on a first response signal output by the chip, wherein the response signal line between the asynchronous zero clearing unit and the chip is connected with a pull-up resistor.

Preferably, the access control device further has the following features: the time of the asynchronous zero clearing unit in the adjusting module delaying the first response signal is integral multiples of the clock period of the CPU.

Preferably, the access control device further has the following features: the time of the asynchronous zero clearing unit in the adjusting module delaying the first response signal is 2 to 5 clock cycles of the CPU.

Preferably, the access control device further has the following features: the asynchronous zero clearing unit is a D trigger.

A master control board comprising a CPU and an access control device as described above.

According to the method, the system and the main control board provided by the invention, when the service board is unplugged, the response signal fed back by the chip is used for adjusting, the abnormal phenomenon of a Central Processing Unit (CPU) of the main control board is eliminated, and the hot plug of the service board is realized.

Drawings

Fig. 1 is a schematic flowchart of an access control method according to an embodiment of the present invention;

fig. 2 is a timing diagram of normal CPU access in an application scenario according to a first embodiment of the present invention;

fig. 3 is a timing diagram of pulling out a service board during a read or write operation of a CPU on a chip in an application scenario according to a first embodiment of the present invention;

fig. 4 is a signal diagram illustrating an access control method according to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating normal access of a CPU in an application scenario according to a second embodiment of the present invention;

fig. 6 is a timing diagram of pulling out the service board during the read or write operation of the CPU on the chip in the application scenario of the second embodiment of the present invention;

fig. 7 is a signal diagram illustrating an access control method according to a second embodiment of the present invention;

fig. 8 is a schematic connection diagram of a D flip-flop according to a second embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Fig. 1 is a schematic flowchart of an access control method according to an embodiment of the present invention. In the embodiment of the method shown in fig. 1, the CPU and the chip are located on different boards, and the method includes:

step 101, in the process of accessing a chip by a CPU, if a first response signal fed back by the chip to the CPU access cannot indicate the CPU to finish the access, adjusting the first response signal into a second response signal capable of indicating the CPU to finish the access;

and 102, sending the second response signal to the CPU.

The method provided by the invention adjusts through the response signal fed back by the chip when the service board is unplugged, eliminates the abnormal phenomenon of the central processing unit CPU of the main control board and realizes the hot plug of the service board.

Example one

The application scenarios used in this embodiment are as follows:

the main control board Central Processing Unit (CPU) sends chip selection signals, and response signals of the accessed chips to the chip selection signals are TA signals and represent responses of data transmission completion. For the CPU, the time taken for one access is the time from the time when the CPU sends out the chip select signal to the time when the TA signal fed back by the accessed chip is received, which is called the normal access cycle. Wherein:

as can be seen from the figure, in this application scenario, the chip select signal is active when low, and conversely, the chip select signal is inactive when high. The TA signal is active when low, and conversely, is inactive when high.

Fig. 3 is a timing diagram of pulling out the service board during the read or write operation of the CPU on the chip in the application scenario according to the first embodiment of the present invention.

As can be seen by comparing with fig. 3, the TA signal is always at a high level, so that the CPU cannot end the access.

Therefore, for the above application scenario, all that needs to be done is that the timing chart when the service board is pulled out during the read or write operation of the CPU on the chip is consistent with fig. 3.

Fig. 4 is a signal diagram illustrating an access control method according to a second embodiment of the present invention. The embodiment includes steps a 01-a 07, which are as follows:

step A01, the CPU in the main control board outputs the chip selection signal to the accessed chip, wherein the chip selection signal is low level, so as to read or write the business board chip;

step A02, after the timer in the main control board detects that the CPU outputs the chip selection signal, the timer uses the clock of the CPU to start timing the time used for the access, on the contrary, if the chip selection signal is high level, the counting value is cleared.

Step A03, the timer judges whether the recorded time is larger than the preset threshold, if the recorded time is larger than the preset threshold, the signal generator in the main control board is started;

the threshold value is the time larger than the maximum normal access cycle, that is, the time obtained by timing is larger than the threshold, which indicates that the CPU may be halted, and thus the signal generator is started. Preferably, the threshold is greater than 1.2 times the maximum normal access period.

If the time recorded by the timer does not reach the threshold during normal operation, that is, the signal generator is not started, the corresponding TA' signal is always output high, and once the threshold is exceeded, it indicates that the situation that the chip is pulled out during the read or write operation of the CPU on the chip may occur, then the CPU does not receive the TA signal of low level in this scenario, and therefore the access cannot be ended. In this case, therefore, it is necessary to adjust the level of the TA signal sent to the CPU to be low to trigger the CPU to end the access operation.

Step a04, the signal generator outputs a TA' signal of low level to the signal synthesizer, which is connected to the accessed chip.

Step A05, the signal synthesizer performs AND operation on the TA 'signal output by the signal generator and the accessed TA' signal on the chip to obtain a TA signal;

specifically, after the low-level TA' signal of the signal generator and the high-level TA "signal output by the service board are anded, a low-level TA signal is generated to the CPU of the main control board, and the read or write operation is ended.

Step A06, the signal synthesizer sends the TA signal to the CPU;

and step A07, after the CPU obtains the TA signal, ending the visit.

For steps a 05-a 07, when the service board normally works, the TA' signal of the signal generator is high, i.e. 1, the TA "signal output by the service board is low, i.e. 0, after the signal synthesizer and the two signals, the resulting TA signal is low level and sent to the Central Processing Unit (CPU) of the main control board, so that the CPU can normally work to end the access. That is, although the above components are added, the normal access operation of the CPU is not affected.

When the CPU reads or writes the chip, after the chip is pulled out, the interface of the chip for outputting the TA signal is in a suspended state, so that the TA signal is in a high level; on the other hand, under the condition that the time recorded by the timer reaches the threshold and the low-level TA signal is not detected, the timer triggers the signal generator to generate a low-level TA ' signal to the signal synthesizer, and after the signal synthesizer receives the low-level TA ' signal and the high-level TA ' signal, and the two signals are subjected to and operation, a low-level TA signal is obtained and sent to the CPU of the main control board, so that the CPU finishes the access, namely, when the chip is pulled out, the problem of overtime ' halt ' of the CPU is avoided.

Preferably, when the chip is pulled out, because the interface of the chip outputting TA "is in a floating state, the floating state may be damaged by external influence, for example, the TA" signal becomes a low level, so that in order to ensure the level stability of the TA "signal received by the signal synthesizer when the chip is pulled out, a pull-up resistor on the main control board is located between the signal generator and the chip and connected to a signal line for transmitting the TA" signal.

Wherein the timer, the signal generator, and the signal synthesizer in the above may be implemented by a Field Programmable Gate Array (FPGA) or a Programmable Logic Device (PLD).

Example two

Fig. 5 is a timing chart of normal CPU access in an application scenario according to the second embodiment of the present invention.

In the timing diagram shown in fig. 5, the CPU sends a chip selection signal, the chip outputs a response signal READY signal after receiving the chip selection signal, where a pulse of the READY signal is a negative pulse, the CPU samples the negative pulse to obtain an neewait signal, and ends this access.

Fig. 6 is a timing diagram of pulling out the service board during the read or write operation of the CPU on the chip in the application scenario of the second embodiment of the present invention.

As can be seen from comparison with fig. 5, after being pulled out, the interface outputting the READY signal is in a floating state, and a certain amount of current is maintained, so that the READY signal is always at a low level, and therefore, the negative pulse condition shown in fig. 5 does not occur, and the CPU cannot sample the READY signal to obtain the neewait signal, and cannot end the access.

Therefore, for the above application scenario, what needs to be done is: firstly, the level of the READY signal is pulled back to high level, so that a negative pulse can be generated, and then the width of the negative pulse of the READY signal is ensured to be wide enough, namely wide enough to obtain the nEWAIT signal sampled by a CPU.

Fig. 7 is a signal diagram illustrating an access control method according to a second embodiment of the present invention. Fig. 7 shows an embodiment of the method. The embodiment includes steps B01 to B04, which are specifically as follows:

step B01, in the process of accessing the chip by the CPU, if the pulse width of the READY signal fed back by the chip can not enable the CPU to sample a signal for indicating the end of the access, the nEWAIT generator acquires the READY signal; the main control board is provided with a pull-up resistor which is positioned between the nEWAIT generator and the chip and is connected with a signal line for transmitting a READY signal;

specifically, according to the characteristics of the pull-up resistor, an uncertain signal is clamped at a high level through a resistor, so that in the process of reading or writing a chip according to a chip selection signal, because a READY signal is at a certain low level, the READY signal cannot be pulled up, and the normal operation of the chip cannot be influenced; in addition, once the chip is pulled out, the level of the READY signal becomes indeterminate, and the level of the READY signal becomes a stable high level through the pull-up resistor, but if the READY signal needs to have a reasonable negative pulse, step B02 needs to be executed.

Step B02, the nEWAIT generator carries out asynchronous zero clearing on the READY signal to obtain a widened negative pulse;

and step B03, the nEWAIT generator sends the READY signal after pulse widening to the CPU.

And step B04, the CPU samples the READY signal after pulse widening to obtain an nEWAIT signal, thereby ending the visit.

As can be seen from this, although the READY signal is narrowed after the chip is pulled out, by performing the pulse width widening processing, the READY signal can be restored to the READY signal when the chip is not pulled out, and the CPU can detect this signal and terminate the access.

And when the chip on the service board normally works, the pulse widening processing is not carried out on the READY signal, so that the sampling work of the CPU is not influenced.

It should be noted that, in step B02, the pulse widening operation is only performed when READY is high, that is, the asynchronous clearing operation is performed by connecting the corresponding one or more components in series.

Taking the D flip-flop to realize asynchronous zero clearing as an example, when the chip on the service board normally works, the READY signal output by the chip is at a low level, the D flip-flop does not perform asynchronous zero clearing operation, and only performs sampling and delay processing on the READY signal, and because the sampling and delay processing cannot affect the width of a pulse, the sampling result of the CPU cannot be affected, when the signal is sent to the CPU of the main control board, the CPU can still obtain an neewait signal for finishing the access from the READY signal, namely when the chip is not pulled out, the normal access of the CPU is not affected; correspondingly, once the chip is pulled out, the READY signal on the chip is in a high level, and the D trigger carries out asynchronous zero clearing operation on the READY signal, so that the width of the negative pulse is widened, and the situations that the READY negative pulse is too narrow and the CPU clock cannot sample when the service card is pulled out do not exist.

It should be noted that, the description is only given by taking one or more D flip-flops of the nwait generator as an example, but not limited thereto, and elements capable of implementing asynchronous zero clearing in the prior art are all applicable to the present invention, and are not given here by way of example.

Fig. 8 is a schematic connection diagram of a D flip-flop according to a second embodiment of the present invention. In the embodiment, when the level of the nCLR signal is set to be low, the output of the D flip-flop is set to be zero, and vice versa, and the level of the nCLR signal is determined by the READY signal. The number of delayed beats of the D flip-flop needs to be determined according to parameter information of the CPU (see CPU manual), and should be an integral multiple of a clock cycle of the CPU, for example, 2-5 clock cycles are selected.

After the sampling of the CPU clock and the processing of the D trigger, the time sequence requirement of nEWAIT can be met. The CPU is enabled to end the read or write operation, thereby avoiding the problem of 'dead halt' of the Central Processing Unit (CPU) of the main control board under the condition that the nEWAIT signal can not be detected.

For the embodiment, because the CPU determines whether to end the access according to the result of sampling the negative pulse of the READY signal, the asynchronous clear operation is triggered only when the READY signal is at a high level, that is, the asynchronous clear operation is determined according to the level of the READY signal; of course, similarly, if the CPU determines whether to end the access by the result of sampling the positive pulse of the READY signal, the asynchronous clear operation is triggered only when the READY signal is low.

By the method, when the service board is unplugged, the abnormal phenomenon of a Central Processing Unit (CPU) of the main control board can be eliminated, and hot plugging of the service board is realized.

It should be noted that the first response signal indicating that the chip has fed back to the CPU access cannot instruct the CPU to end the access is understood that the signal for feeding back the chip is not a signal for ending the CPU access described in the CPU manual. The CPU manual is a tool book for specifying parameter information of the CPU, and is defined by a manufacturer that produces the CPU, so that when the CPU access is ended, there are different ways such as defining a signal that is effective at a high level and can end the CPU access, but as long as a signal fed back from a chip does not conform to the description in the CPU manual, the above-described method can be used for processing, and thus the present invention is not limited to the above-described embodiment.

Corresponding to the above method, the present invention further provides an access control device, where the CPU and the chip are located on different boards, including:

Preferably, the adjusting module includes:

the timing unit is connected with a clock signal line and a chip selection signal line of the CPU and used for timing the current access when detecting that the CPU sends an access request to the chip and starting the signal generator when the time obtained by timing exceeds a preset threshold;

and the signal synthesis unit is connected with the signal generation unit, connected with the chip and the CPU through a response signal line of the CPU and used for carrying out AND operation on the third response signal and the high-level first response signal output by the chip to obtain a second response signal.

Wherein the threshold used by the timing unit is greater than the maximum normal access period.

Wherein the threshold is more than 1.2 times of the maximum normal access period.

And a response signal wire between the signal synthesis unit and the chip is connected with a pull-up resistor.

Preferably, the adjusting module includes one or more asynchronous clear units, wherein:

The time of the asynchronous zero clearing unit in the adjusting module delaying the first response signal is integral multiple of the clock period of the CPU.

The time for delaying the first response signal by the asynchronous zero clearing unit in the adjusting module is 2 to 5 clock cycles of the CPU.

And the asynchronous zero clearing unit is a D trigger.

When the service board is unplugged, the device provided by the invention adjusts through the response signal fed back by the chip, eliminates the abnormal phenomenon of the CPU of the central processing unit of the main control board, and realizes the hot plug of the service board.

In addition, the invention also provides a main control board which is characterized by comprising a CPU and any one of the access control devices.

When the service board is unplugged, the main control board provided by the invention adjusts through the response signal fed back by the chip, eliminates the abnormal phenomenon of the Central Processing Unit (CPU) of the main control board, and realizes the hot plug of the service board.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An access control method is characterized in that a CPU and a chip are positioned on different boards, and the method comprises the following steps:

in the process of accessing the chip by the CPU, if detecting that a first response signal fed back by the chip to the CPU access cannot indicate the CPU to finish the access, adjusting the first response signal into a second response signal capable of indicating the CPU to finish the access, and sending the second response signal to the CPU;

adjusting the first response signal to a second response signal capable of instructing the CPU to end the access, comprising:

2. The method of claim 1, wherein the threshold is greater than a maximum normal access period.

3. The method of claim 2, wherein the threshold is greater than 1.2 times a maximum normal access period.

4. The method of claim 1, wherein the pulse widening process delays the first response signal by an integer multiple of a clock period of the CPU.

5. The method of claim 4, wherein the pulse widening process delays the first response signal by between 2 and 5 CPU clock cycles.

6. An access control apparatus, comprising:

the sending module is used for sending the second response signal to the CPU;

the adjustment module includes:

7. The apparatus of claim 6, wherein the threshold used by the timing unit is greater than a maximum normal access period.

8. The apparatus of claim 7, wherein the threshold is greater than 1.2 times a maximum normal access period.

9. The apparatus of claim 8, wherein a pull-up resistor is connected to the response signal line between the signal synthesizing unit and the chip.

10. The apparatus of claim 6, wherein the adjustment module comprises one or more asynchronous zero units, wherein:

11. The apparatus of claim 10, wherein the delay time generated by the asynchronous clear unit in the adjustment module for the first response signal is an integer multiple of a clock period of the CPU.

12. The apparatus of claim 11, wherein the delay time generated by the asynchronous clear unit in the adjustment module for the first response signal is 2 to 5 clock cycles of the CPU.

13. The apparatus of claim 10, wherein the asynchronous clear unit is a D flip-flop.

14. A master control board comprising a CPU and an access control device according to any one of claims 6 to 13.