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CN102844870B - 匹配器件中的纳米线电路 - Google Patents

匹配器件中的纳米线电路 Download PDF

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CN102844870B
CN102844870B CN201180018658.XA CN201180018658A CN102844870B CN 102844870 B CN102844870 B CN 102844870B CN 201180018658 A CN201180018658 A CN 201180018658A CN 102844870 B CN102844870 B CN 102844870B
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effect transistor
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CN102844870A (zh
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S·邦萨伦提普
G·科恩
A·马宗达
J·W·斯雷特
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

一种反向器器件，包括第一纳米线，其连接至电压源节点与接地节点；第一p型场效晶体管(pFET)器件，其具有设置在所述第一纳米线上的栅极；以及第一n型场效晶体管(nFET)器件，其具有设置在所述第一纳米线上的栅极。

Description

匹配器件中的纳米线电路
技术领域
本发明涉及半导体纳米线场效晶体管。
背景技术
纳米线场效晶体管(FET)包括纳米线的掺杂部分，其接触沟道区并作为器件的源极区与漏极区。FET可用互补金属氧化物半导体方法制造以形成多种集成电路。
发明内容
根据本发明的一个实施例，反向器器件包括连接至电压源节点与接地节点的第一纳米线；具有设置在所述第一纳米线上的栅极的第一p型场效晶体管(pFET)器件；以及具有设置在所述第一纳米线上的栅极的第一n型场效晶体管(nFET)器件。
根据本发明的替代实施例，形成反向器器件的方法包括形成第一纳米线；形成具有设置在所述第一纳米线上的栅极的第一p型场效晶体管(pFET)器件；形成具有设置在所述第一纳米线上的栅极的第一n型场效晶体管(nFET)器件；以及电连接所述第一pFET器件的所述栅极至所述第一nFET器件的所述栅极。
根据本发明的另一替代实施例，存储器器件包括连接至第一位线节点与接地节点的第一纳米线；具有设置在所述第一纳米线上的栅极的第一场效晶体管(FET)；具有设置在所述第一纳米线上的栅极的第二FET；连接至电压源节点与第一输入节点的第二纳米线；具有设置在所述第二纳米线上的栅极的第三FET；连接至所述电压源节点与第二输入节点的第三纳米线；具有设置在所述第三纳米线上的栅极的第四FET；连接至第二位线节点与所述接地节点的第四纳米线；具有设置在所述第四纳米线上的栅极的第五FET；以及具有设置在所述第四纳米线上的栅极的第六FET。
根据本发明又另一替代实施例，形成存储器器件的方法包括形成连接至第一位线节点与接地节点的第一纳米线；形成具有设置在所述第一纳米线上的栅极的第一场效晶体管(FET)；形成具有设置在所述第一纳米线上的栅极的第二FET；形成连接至电压源节点与第一储存节点的第二纳米线；形成具有设置在所述第二纳米线上的栅极的第三FET；形成连接至所述电压源节点与第二储存节点的第三纳米线；形成具有设置在所述第三纳米线上的栅极的第四FET；形成连接至第二位线节点与所述接地节点的第四纳米线；形成具有设置在所述第四纳米线上的栅极的第五FET；以及形成具有设置在所述第四纳米线上的栅极的第六FET。
透过本发明的技术可实现其它特征与优点。本说明书内详细描述本发明的其它实施例与方面，且这些实施例与方面视为所主张发明的一部分。为了更加了解本发明的优点与特征，请参阅说明与附图。
附图说明
在本说明书结论处的权利要求中特别指出并要求保护认为是本发明的主旨。从下列搭配附图的详细说明中，可了解本发明的上述与其它特征和优点，其中：
图1例示反向器电路的现有技术实例的附图。
图2例示静态随机存取存储器(SRAM)电路的现有技术实例的附图。
图3例示纳米线反向电路的示范实施例。
图4例示纳米线SRAM电路的示范实施例。
具体实施方式
集成电路可包括由纳米线沟道FET形成的许多不同类型场效应晶体管。纳米线沟道FET包括连接至源极区与漏极区的硅纳米线，以及完全(或部分)包围纳米线的栅极。沟道形成于栅极之下的纳米线的表面上(或在直径小于约5nm的纳米线的纳米线体内)。栅极完全包围纳米线时，该器件称的为环绕栅极(GAA)FET。栅极部分包围纳米线时，如同纳米线固定至绝缘体的情况，该器件称的为欧米伽栅极FET。纳米线FET可制造来形成例如nFET和pFET器件。nFET和pFET器件可相连，以形成多种集成电路器件，例如反向器以及静态随机存取存储器(SRAM)。在电路器件中，多个FET一般需要通过例如相似的阈值电压与驱动电流而匹配。
晶片上形成的纳米线FET器件可包括任意数量的纳米线。该制造工艺可包括例如使用各向同性蚀刻工艺在掩埋氧化物衬底上形成硅纳米线。该蚀刻工艺产生椭圆(包括圆柱)形状的纳米线，其可悬浮在衬底之上方或可部分置于衬底上。在该纳米线上形成金属或多晶硅栅极结构。邻近该栅极结构形成源极与漏极区，并且可形成接触，以将源极、漏极和栅极结构连接至其它器件。
该工艺特别可产生具有不同性质的纳米线，像是例如由于晶片上特定纳米线的位置，晶片上纳米线的直径可能与另一纳米线的直径不同。虽然在晶片上的两条不同纳米线的直径会改变，不过每一特定纳米线的直径通常维持不变，并且在所需的容差范围内。
像是例如SRAM和反向器的这类集成电路器件都包含许多pFET和nFET器件，其置于设置在晶片上的纳米线上。由于这些纳米线的性质(例如纳米线直径)实现器件的操作，因此需要设置器件，使得纳米线性质差异的影响能降低。
图1例示反向器的现有技术实例的附图，该反向器包括连接至nFET器件103的pFET器件101。器件101连接至电压源节点(Vdd)106、输入节点(A)102和输出节点(Q)104。器件102连接至接地节点(Vss)108、A和Q。
图2例示静态随机存取存储器(SRAM)电路的现有技术实例的附图。SRAM包括连接至第一位线节点(BL)202、第一输出节点(Q)204和字线节点(WL)206的第一nFET器件(M6)201。第二nFET器件(M3)203连接至Q节点204、接地节点(Vss)208和第二输出节点第一pFET器件(M4)205连接至Q节点204、节点210和电压源节点(Vdd)212。第二pFET器件(M2)207连接至Vdd节点212、Q节点204和节点210。第三nFET器件(M1)209连接至Vss节点208、Q节点204和节点210。第四nFET器件(M5)211连接至第二位线节点WL节点206和节点210。
如上讨论，晶片上的纳米线可具有不同直径，影响置于纳米线上的栅极的性能特性。当器件内特定FET具有类似特性时，包括例如图1和图2现有技术实例的集成电路的性能可获得改善。因此，通过在共公线(commonwire)内使用更好匹配的器件，设计集成电路使得特定FET分享公共纳米线可改善电路的性能。
图3例示纳米线反向电路300的示范实施例，其如上述用衬底上形成的硅纳米线器件所制造。电路300包括连接至电压源节点(Vdd)306与接地节点(Vss)308的第一纳米线320。pFET器件301和nFET器件303具有设置在第一纳米线320上的栅极区(G)。器件301和303的漏极区(D)连接至输出节点(Q)304。器件301的源极区(S)连接至Vdd节点306，且器件303的源极区(S)连接至Vss节点308。器件301和303的栅极都连接至输入节点(A)302。例示的实施例包括类似于反向电路300的第二反向电路350。反向电路350形成于第二纳米线321上。第二反向电路350的A节点302通过硅构件352连接至Q节点304。通过将FET器件301和303置于相同纳米线，导致具有类似性能特性的FET器件301和303，第一纳米线320上反向电路300的设置改善电路300的性能。利用第二反向电路350的设置，可获得类似的优点。
图4例示纳米线SRAM电路400的示范实施例，其以上述类似方式用硅纳米线器件所制造。电路400包括连接至位线节点(BL)402与第一接地节点(Vss)408a的第一纳米线420。第一nFET器件(M6)401形成于第一纳米线420上，并连接至BL节点402、第一输出节点(Q)404和第一字线节点(WL)406a。第二nFET器件(M3)403形成于第一纳米线420上，并且连接至Q节点404、第一Vss节点408a和第二输出节点第二纳米线421连接至Q节点404和第一电压源节点(Vdd)412a。第一pFET器件(M4)405形成于第二纳米线421上，并且连接至Q节点404、节点410和Vdd节点412a。第三纳米线422连接至第二Vdd节点412b和节点410。第二pFET器件(M2)407形成于第三纳米线422上，并且连接至Vdd节点412b、Q节点404和节点410。第四纳米线423连接至第二Vss节点408b和位线节点第三nFET器件(M1)409连接至第二Vss节点408b、Q节点404和节点410。第四nFET器件(M5)411连接至位线节点第二WL节点406b和节点410。可形成硅构件452，以将第一纳米线420连接至Q节点404，并且可形成硅构件453，以将第四纳米线423连接至节点410。
虽然所例示的实施例包括在集成电路内实施匹配FET的两个实例，但是，通过将特定FET器件设置在特定纳米线上，上述方法可应用于任何一种集成电路，以改善电路性能，使得相同纳米线的FET器件具有类似性能特性。
此处所使用的术语仅为说明特定实施例，并非用于限制本发明。如此处所使用，除非上下文有明确指示，否则该单数形式“一”和“该”也包含复数形式。将更了解，说明书中使用的术语“包含”和/或“包括”指明所陈述的特征、整体、步骤、操作、元件和/或部件的存在，但是不排除还有一或多个其它特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加。
对应的结构、材料、动作以及以下权利要求内所有装置或步骤加功能元件的同等物，都旨在包含任何结构、材料或动作，以结合特别主张的其它主张元件来执行该功能。本发明的描述已经为了例示与描述的目的而呈现，而非要将本发明毫无遗漏地限制在所揭示形式中。在不脱离本发明的范围与精神的前提下，本领域一般技术者将了解许多修正以及变化。实施例经过选择与说明来最佳阐述本发明原理及实际应用，并且使其它本领域的一般技术者了解用于各种实施例的本发明，这些实施例具有适合于所考虑的特定用途的各种修改。
本说明书内说明的附图只是一个实例，在不悖离本发明精神的情况下，本说明书内说明的附图或步骤(或操作)可有许多变化。例如，步骤可用不同顺序执行，或可增加、删减或修改步骤。所有这些变化都视为所要求保护的发明的一部分。
虽然已经说明本发明的优选实施例，但精通此技术的人员可了解，目前与未来可在所附权利要求范围的范围内进行各种改善与增强。这些权利要求应被视为对首先描述的本发明维持适当保护。

Claims (19)

1.一种反向器器件，包括：
第一纳米线，连接至电压源节点和接地节点；
第一p型场效晶体管器件，具有设置在所述第一纳米线上的栅极；以及
第一n型场效晶体管器件，其具有设置在所述第一纳米线上的栅极；
其中所述器件还包括连接到所述第一p型场效晶体管器件的所述栅极和所述第一n型场效晶体管器件的所述栅极的第三节点。
2.根据权利要求1的器件，其中所述器件还包括：
第二纳米线，连接至所述电压源节点与所述接地节点；
第二p型场效晶体管器件，具有设置在所述第二纳米线上的栅极；以及
第二n型场效晶体管器件，具有设置在所述第二纳米线上的栅极。
3.根据权利要求2的器件，其中所述器件还包括连接至所述第二p型场效晶体管器件的所述栅极与所述第二n型场效晶体管器件的所述栅极的第四节点。
4.根据权利要求3的器件，其中所述器件包括所述第四节点与所述第一p型场效晶体管器件的漏极区和所述第一n型场效晶体管器件的漏极区之间的连接。
5.根据权利要求1的器件，其中所述第一纳米线为硅纳米线。
6.根据权利要求1的器件，其中所述第一纳米线悬浮在衬底之上。
7.一种形成反向器器件的方法，所述方法包括：
形成第一纳米线；
形成第一p型场效晶体管器件，其具有设置在所述第一纳米线上的栅极；
形成第一n型场效晶体管器件，其具有设置在所述第一纳米线上的栅极；以及
电连接所述第一p型场效晶体管器件的所述栅极至所述第一n型场效晶体管器件的所述栅极。
8.根据权利要求7的方法，其中所述方法还包括：
形成第二纳米线；
形成第二p型场效晶体管器件，其具有设置在所述第二纳米线上的栅极；
形成第二n型场效晶体管器件，其具有设置在所述第二纳米线上的栅极；以及
电连接所述第二p型场效晶体管器件的所述栅极至所述第二n型场效晶体管器件的所述栅极、所述第一p型场效晶体管器件的漏极区以及所述第一n型场效晶体管器件的漏极区。
9.根据权利要求7的方法，其中所述方法还包括将所述第一p型场效晶体管器件的源极区连接至电压源节点。
10.根据权利要求7的方法，其中所述方法还包括将所述第一n型场效晶体管器件的源极区至接地节点。
11.一种存储器器件，包括：
第一纳米线，连接至第一位线节点与接地节点；
第一场效晶体管，具有设置在所述第一纳米线上的栅极；
第二场效晶体管，具有设置在所述第一纳米线上的栅极；
第二纳米线，连接至第一电压源节点与第一输入节点；
第三场效晶体管，具有设置在所述第二纳米线上的栅极；
第三纳米线，连接至第二电压源节点与第二输入节点；
第四场效晶体管，具有设置在所述第三纳米线上的栅极；
第四纳米线，连接至第二位线节点与所述接地节点；
第五场效晶体管，具有设置在所述第四纳米线上的栅极；以及
第六场效晶体管，具有设置在所述第四纳米线上的栅极。
12.根据权利要求11的器件，其中所述第一场效晶体管的栅极端子连接至第一字线节点，所述第二场效晶体管的栅极端子连接至所述第二输入节点，所述第三场效晶体管的栅极端子连接至所述第二输入节点，所述第四场效晶体管的栅极端子连接至所述第一输入节点，所述第五场效晶体管的栅极端子连接至所述第一输入节点，以及所述第六场效晶体管的栅极端子连接至第二字线节点。
13.根据权利要求11的器件，其中所述第一场效晶体管为n型场效晶体管，所述第二场效晶体管为n型场效晶体管，所述第三场效晶体管为p型场效晶体管，所述第四场效晶体管为p型场效晶体管，所述第五场效晶体管为n型场效晶体管，以及所述第六场效晶体管为n型场效晶体管。
14.根据权利要求11的器件，其中所述第一纳米线为硅纳米线。
15.根据权利要求11的器件，其中所述第一纳米线悬浮在衬底之上。
16.根据权利要求11的器件，其中所述第一纳米线的一部分连接至所述第一输入节点，并且所述第四纳米线的一部分连接至所述第二输入节点。
17.一种形成存储器器件的方法，所述方法包括：
形成连接至第一位线节点与接地节点的第一纳米线；
形成第一场效晶体管，其具有设置在所述第一纳米线上的栅极；
形成第二场效晶体管，其具有设置在所述第一纳米线上的栅极；
形成连接至第一电压源节点与第一储存节点的第二纳米线；
形成第三场效晶体管，其具有设置在所述第二纳米线上的栅极；
形成连接至第二电压源节点与第二储存节点的第三纳米线；
形成第四场效晶体管，其具有设置在所述第三纳米线上的栅极；
形成连接至第二位线节点与所述接地节点的第四纳米线；
形成第五场效晶体管，其具有设置在所述第四纳米线上的栅极；以及
形成第六场效晶体管，其具有设置在所述第四纳米线上的栅极。
18.根据权利要求17的方法，其中所述第一纳米线为用各向同性蚀刻方法形成的硅纳米线。
19.根据权利要求17的方法，其中所述第一纳米线悬浮在衬底之上。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
CN102522426B (zh) * 2011-11-30 2014-05-28 上海华力微电子有限公司 硅纳米线探测单元
WO2013095384A1 (en) * 2011-12-20 2013-06-27 Intel Corporation Semiconductor device with isolated body portion
US9000530B2 (en) * 2013-04-23 2015-04-07 International Business Machines Corporation 6T SRAM architecture for gate-all-around nanowire devices
US8900951B1 (en) 2013-09-24 2014-12-02 International Business Machines Corporation Gate-all-around nanowire MOSFET and method of formation
WO2015200363A1 (en) * 2014-06-23 2015-12-30 Synopsys, Inc. Memory cells and logic cells having transistors with different numbers of nanowires or 2d material strips
US9400862B2 (en) 2014-06-23 2016-07-26 Synopsys, Inc. Cells having transistors and interconnects including nanowires or 2D material strips
US9985026B2 (en) 2014-08-15 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor, integrated circuit and method of fabricating the same
US9893159B2 (en) 2014-08-15 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor, integrated circuit and method of fabricating the same
US9431388B1 (en) 2015-04-29 2016-08-30 Globalfoundries Inc. Series-connected nanowire structures
US9607900B1 (en) 2015-09-10 2017-03-28 International Business Machines Corporation Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
CN108701653B (zh) * 2016-02-25 2022-07-29 株式会社索思未来 半导体集成电路装置
US10312229B2 (en) 2016-10-28 2019-06-04 Synopsys, Inc. Memory cells including vertical nanowire transistors
JPWO2019142670A1 (ja) 2018-01-19 2021-01-07 株式会社ソシオネクスト 半導体集積回路装置
WO2019159739A1 (ja) * 2018-02-15 2019-08-22 株式会社ソシオネクスト 半導体集積回路装置
US11678475B2 (en) * 2021-07-21 2023-06-13 International Business Machines Corporation Static random access memory using vertical transport field effect transistors
CN114171589B (zh) * 2022-02-11 2022-04-29 晶芯成(北京)科技有限公司 半导体器件结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit

Family Cites Families (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638769A (en) 1985-03-18 1987-01-27 Caterpillar Inc. Engine having a multipiece cylinder block
JPH04299569A (ja) 1991-03-27 1992-10-22 Nec Corp Ｓｏｉｓの製造方法及びトランジスタとその製造方法
US5308445A (en) 1991-10-23 1994-05-03 Rohm Co., Ltd. Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate
JPH0637302A (ja) 1992-07-14 1994-02-10 Mitsuteru Kimura トンネルトランジスタ
JP3319472B2 (ja) 1992-12-07 2002-09-03 富士通株式会社 半導体装置とその製造方法
US6365465B1 (en) 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
US6982460B1 (en) 2000-07-07 2006-01-03 International Business Machines Corporation Self-aligned gate MOSFET with separate gates
US6642115B1 (en) 2000-05-15 2003-11-04 International Business Machines Corporation Double-gate FET with planarized surfaces and self-aligned silicides
TW540086B (en) * 2000-08-14 2003-07-01 Matrix Semiconductor Inc Dense arrays and charge storage devices, and methods for making same
US20060175601A1 (en) 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
CA2442985C (en) 2001-03-30 2016-05-31 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
DE10118405A1 (de) 2001-04-12 2002-10-24 Infineon Technologies Ag Heterostruktur-Bauelement
JP2004537174A (ja) * 2001-07-26 2004-12-09 テクニシェ ユニヴェルシテイト デルフト カーボンナノチューブを利用した電子デバイス
US6891227B2 (en) 2002-03-20 2005-05-10 International Business Machines Corporation Self-aligned nanotube field effect transistor and method of fabricating same
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6815750B1 (en) 2002-05-22 2004-11-09 Hewlett-Packard Development Company, L.P. Field effect transistor with channel extending through layers on a substrate
US6919740B2 (en) 2003-01-31 2005-07-19 Hewlett-Packard Development Company, Lp. Molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits, and more complex circuits composed, in part, from molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US6903013B2 (en) 2003-05-16 2005-06-07 Chartered Semiconductor Manufacturing Ltd. Method to fill a trench and tunnel by using ALD seed layer and electroless plating
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7060576B2 (en) 2003-10-24 2006-06-13 Intel Corporation Epitaxially deposited source/drain
US7311776B2 (en) 2003-12-30 2007-12-25 The Regents Of The University Of California Localized synthesis and self-assembly of nanostructures
US7180107B2 (en) 2004-05-25 2007-02-20 International Business Machines Corporation Method of fabricating a tunneling nanotube field effect transistor
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
US20070257277A1 (en) * 2004-06-04 2007-11-08 Nec Corporation Semiconductor Device and Method for Manufacturing the Same
US7443025B2 (en) 2004-06-07 2008-10-28 Broadcom Corporation Thermally improved placement of power-dissipating components onto a circuit board
KR100618831B1 (ko) 2004-06-08 2006-09-08 삼성전자주식회사 게이트 올 어라운드형 반도체소자 및 그 제조방법
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
CN101010793B (zh) * 2004-06-30 2011-09-28 Nxp股份有限公司 制造具有通过纳米线接触的导电材料层的电子器件的方法
US8288813B2 (en) 2004-08-13 2012-10-16 Infineon Technologies Ag Integrated memory device having columns having multiple bit lines
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7473943B2 (en) 2004-10-15 2009-01-06 Nanosys, Inc. Gate configuration for nanowire electronic devices
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7465973B2 (en) 2004-12-03 2008-12-16 International Business Machines Corporation Integrated circuit having gates and active regions forming a regular grating
US7598516B2 (en) 2005-01-07 2009-10-06 International Business Machines Corporation Self-aligned process for nanotube/nanowire FETs
US20080121932A1 (en) 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100594327B1 (ko) 2005-03-24 2006-06-30 삼성전자주식회사 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법
KR101127132B1 (ko) 2005-05-13 2012-03-21 삼성전자주식회사 실리콘 나노와이어 기판 및 그 제조방법, 그리고 이를이용한 박막 트랜지스터의 제조방법
US7230286B2 (en) 2005-05-23 2007-06-12 International Business Machines Corporation Vertical FET with nanowire channels and a silicided bottom contact
WO2006132659A2 (en) 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures
US7387946B2 (en) 2005-06-07 2008-06-17 Freescale Semiconductor, Inc. Method of fabricating a substrate for a planar, double-gated, transistor process
KR100618900B1 (ko) 2005-06-13 2006-09-01 삼성전자주식회사 다중 채널을 갖는 모스 전계효과 트랜지스터의 제조방법 및그에 따라 제조된 다중 채널을 갖는 모스 전계효과트랜지스터
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7354831B2 (en) 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
TW200709413A (en) * 2005-08-29 2007-03-01 Univ Nat Chiao Tung Nano-Wire FET and Nano-Wire biosensor/regulator, and manufacturing method thereof
US7452759B2 (en) 2005-11-29 2008-11-18 Micron Technology, Inc. Carbon nanotube field effect transistor and methods for making same
US7871912B2 (en) 2005-12-13 2011-01-18 Versatilis Llc Methods of making semiconductor-based electronic devices by forming freestanding semiconductor structures
US7498211B2 (en) 2005-12-28 2009-03-03 Intel Corporation Independently controlled, double gate nanowire memory cell with self-aligned contacts
TWI292218B (en) * 2006-02-13 2008-01-01 Wang Chih-Hsin An electrically erasable and programmable nonvolatile memory device and array and method for operating thereof
US7495877B2 (en) * 2006-03-26 2009-02-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and method to reduce ringing in the semiconductor power switching circuits
US7449373B2 (en) 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7608489B2 (en) 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7772071B2 (en) 2006-05-17 2010-08-10 Chartered Semiconductor Manufacturing Ltd. Strained channel transistor and method of fabrication thereof
US7880160B2 (en) 2006-05-22 2011-02-01 Qimonda Ag Memory using tunneling field effect transistors
JP5060740B2 (ja) * 2006-05-26 2012-10-31 シャープ株式会社 集積回路装置およびその製造方法、ならびに表示装置
US7456068B2 (en) 2006-06-08 2008-11-25 Intel Corporation Forming ultra-shallow junctions
US7629603B2 (en) 2006-06-09 2009-12-08 Intel Corporation Strain-inducing semiconductor regions
US20080014689A1 (en) 2006-07-07 2008-01-17 Texas Instruments Incorporated Method for making planar nanowire surround gate mosfet
KR100745769B1 (ko) * 2006-09-11 2007-08-02 삼성전자주식회사 나노와이어 전기기계 스위칭 소자 및 그 제조방법, 상기나노와이어 전기기계 소자를 이용한 전기기계 메모리 소자
US7999251B2 (en) 2006-09-11 2011-08-16 International Business Machines Corporation Nanowire MOSFET with doped epitaxial contacts for source and drain
US7893476B2 (en) 2006-09-15 2011-02-22 Imec Tunnel effect transistors based on silicon nanowires
EP1900681B1 (en) 2006-09-15 2017-03-15 Imec Tunnel Field-Effect Transistors based on silicon nanowires
KR100801063B1 (ko) 2006-10-02 2008-02-04 삼성전자주식회사 게이트 올 어라운드형 반도체 장치 및 그 제조 방법
JP5057739B2 (ja) * 2006-10-03 2012-10-24 株式会社東芝 半導体記憶装置
KR100757328B1 (ko) 2006-10-04 2007-09-11 삼성전자주식회사 단전자 트랜지스터 및 그 제조 방법
US7498265B2 (en) 2006-10-04 2009-03-03 Micron Technology, Inc. Epitaxial silicon growth
US20080128760A1 (en) 2006-12-04 2008-06-05 Electronics And Telecommunications Research Institute Schottky barrier nanowire field effect transistor and method for fabricating the same
US20080135949A1 (en) 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
KR100881185B1 (ko) 2006-12-20 2009-02-05 삼성전자주식회사 비휘발성 메모리 소자 및 그 동작 방법
US8049203B2 (en) 2006-12-22 2011-11-01 Qunano Ab Nanoelectronic structure and method of producing such
JP2008172082A (ja) * 2007-01-12 2008-07-24 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP5100137B2 (ja) 2007-01-26 2012-12-19 株式会社東芝 半導体装置の製造方法および半導体装置
US20090217216A1 (en) * 2007-02-28 2009-08-27 Motorola, Inc. Carbon nanotube circuits design methodology
JP2008252086A (ja) 2007-03-12 2008-10-16 Interuniv Micro Electronica Centrum Vzw ゲートトンネル障壁を持つトンネル電界効果トランジスタ
US7859036B2 (en) 2007-04-05 2010-12-28 Micron Technology, Inc. Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
US7871851B2 (en) 2007-05-25 2011-01-18 RF Nano Method for integrating nanotube devices with CMOS for RF/analog SoC applications
JP2009016418A (ja) * 2007-07-02 2009-01-22 Nec Electronics Corp 半導体装置
US7812370B2 (en) 2007-07-25 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling
US8154127B1 (en) 2007-07-30 2012-04-10 Hewlett-Packard Development Company, L.P. Optical device and method of making the same
US7534675B2 (en) 2007-09-05 2009-05-19 International Business Machiens Corporation Techniques for fabricating nanowire field-effect transistors
US7795677B2 (en) 2007-09-05 2010-09-14 International Business Machines Corporation Nanowire field-effect transistors
JP4966153B2 (ja) 2007-10-05 2012-07-04 株式会社東芝 電界効果トランジスタおよびその製造方法
KR20090044799A (ko) 2007-11-01 2009-05-07 삼성전자주식회사 액티브 핀의 제조 방법 및 이를 포함하는 트랜지스터
JP2009130167A (ja) 2007-11-26 2009-06-11 Renesas Technology Corp 半導体装置およびその製造方法
TWI373137B (en) * 2008-08-20 2012-09-21 Univ Nat Formosa Gas sensor made of field effect transistor based on zno nanowires
US7834345B2 (en) 2008-09-05 2010-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistors with superlattice channels
US8362604B2 (en) 2008-12-04 2013-01-29 Ecole Polytechnique Federale De Lausanne (Epfl) Ferroelectric tunnel FET switch and memory
US7884004B2 (en) 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
KR20100094192A (ko) * 2009-02-18 2010-08-26 삼성전자주식회사 탄소나노튜브 박막을 이용한 에스램
JP2011040524A (ja) * 2009-08-10 2011-02-24 Fujitsu Semiconductor Ltd 半導体装置の製造方法及び半導体装置
US8173993B2 (en) 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8129247B2 (en) 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8097515B2 (en) 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US20110147840A1 (en) 2009-12-23 2011-06-23 Cea Stephen M Wrap-around contacts for finfet and tri-gate devices
US8420455B2 (en) 2010-05-12 2013-04-16 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8338280B2 (en) 2010-07-08 2012-12-25 Globalfoundries Singapore Pte. Ltd. Method for fabricating nano devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit

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US8324940B2 (en) 2012-12-04

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