CN102842488A - Method of double-sided manufacturing device of substrate and substrate - Google Patents
Method of double-sided manufacturing device of substrate and substrate Download PDFInfo
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- CN102842488A CN102842488A CN2012103039061A CN201210303906A CN102842488A CN 102842488 A CN102842488 A CN 102842488A CN 2012103039061 A CN2012103039061 A CN 2012103039061A CN 201210303906 A CN201210303906 A CN 201210303906A CN 102842488 A CN102842488 A CN 102842488A
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- 239000000758 substrate Substances 0.000 title claims abstract description 145
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims description 40
- 238000005516 engineering process Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005336 cracking Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 10
- 230000005611 electricity Effects 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000002209 hydrophobic effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- -1 annealing Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
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Abstract
The invention provides a method of a double-sided manufacturing device of a substrate and a substrate. The method comprises following steps of providing a device substrate, wherein the device substrate is provided with a first surface and a second surface, which are opposite to each other, and the first surface is provided with a plurality of devices; providing a first supporting substrate, wherein the surface of the first supporting substrate is provided with a first insulation layer; adopting the first insulation layer as an intermediate layer, and bonding the first surface of the device substrate with a first supporting substrate; thinning the second surface of the device substrate; and producing a device on the exposed second surface of the device substrate. The method has advantages that the technical step for producing the device on the second surface is free from influencing the first surface, and the cracking problem can be avoided because the first supporting substrate is bonded as a supporting structure.
Description
Technical field
The present invention relates to IC chip and make the field, relate in particular to a kind of method and substrate of the two-sided manufacturing device at substrate.
Background technology
The IC chip manufacturing is the important step of whole IC industrial chain; The front-end process of chip manufacturing mainly comprises technologies such as photoetching, doping and corrosion; Main purpose is to produce pre-designed devices such as transistor at substrate surface, and produces the electricity line.
Along with the continuous development of integrated circuit technique, usually need there be the silicon chip back side of certain figure or doping to make device architectures such as circuit in the chip manufacturing proces, these structures are carried out PROCESS FOR TREATMENT to the initial graphics in former front after accomplishing again.
Normally directly make device architectures such as circuit in the prior art overleaf, and usually need be before making circuit with substrate thinning, and after the attenuate substrate will become be very easy to cracked, thereby have influence on the yield of chip; And make device at the back side of chip, and the back side makes and make in the process of device in the front again after finishing, cause the contamination of another side easily, thereby also can have influence on the product yield.
Therefore, need a kind of can the generation to stain and cracked process really, in order to the two-sided substrate that all has device of processing and manufacturing to substrate.
Summary of the invention
Technical problem to be solved by this invention is, a kind of method of the two-sided manufacturing device at substrate is provided, and can avoid in the technology of two-sided manufacturing device substrate caused staiing and cracked, thereby can be used for the two-sided substrate that all has device of processing and manufacturing.
In order to address the above problem, the invention provides a kind of method of the two-sided manufacturing device at substrate, comprise the steps: to provide device substrate, said device substrate has opposite first and second surface, and first surface has a plurality of devices; First support substrates is provided, and the said first support substrates surface has first insulating barrier; With first insulating barrier is the intermediate layer, with the same first support substrates bonding of the first surface of device substrate; The second surface of attenuate device substrate; On the second surface that exposes of device substrate, make device; Second support substrates is provided, and the said second support substrates surface has second insulating barrier; With second insulating barrier is the centre buried regions, with the same second support substrates bonding of the second surface of device substrate; Remove first support substrates and first insulating barrier.
Optional, said device substrate is made up of heavily doped layer and lightly-doped layer, and said lightly-doped layer comprises the first surface of device substrate, and said heavily doped layer comprises the second surface of device substrate, and said element manufacturing is in lightly-doped layer.
Optional, in the step of said attenuate device substrate second surface, further comprise the step of removing heavily doped layer through selective corrosion technology.
Optional, after removing heavily doped layer, further comprise the step on the surface of the lightly-doped layer that polishing exposes.
Optional, after removing first support substrates and first insulating barrier, further be included in the step that continues to make device on the first surface of the device substrate that exposes.
Optional, the material of said device substrate is a monocrystalline silicon.
Optional, the material of said first insulating barrier and second insulating barrier is selected from any one of silica, silicon nitride and silicon oxynitride.
The present invention further provides a kind of substrate that adopts said method to make; Comprise second support substrates; Second insulating barrier on said second support substrates surface and the device layer of second surface of insulating layer; Said device layer has the first surface and the second surface corresponding with first surface of exposure, all has a plurality of devices on said first surface and the second surface.
Optional, the material of said device layer is a monocrystalline silicon.
Optional, the material of said second insulating barrier is selected from any one of silica, silicon nitride and silicon oxynitride.
The invention has the advantages that; Make in the processing step of device at second surface; Because the first surface that has adopted bonding technology that device substrate has been made device before protects; So can not impact to it, and since bonding first support substrates as supporting construction, device substrate can be allowed to as far as possible attenuate and needn't worry problems such as cracked.
Description of drawings
It shown in the accompanying drawing 1 the implementation step sketch map of the specific embodiment of the invention.
Accompanying drawing 2A is to shown in the accompanying drawing 2I being the process schematic representation of the specific embodiment of the invention.
Accompanying drawing 3A is to shown in the accompanying drawing 3E being the process schematic representation of one embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the method for the two-sided manufacturing device at substrate provided by the invention and the embodiment of substrate are elaborated.
Be the implementation step sketch map of this embodiment shown in the accompanying drawing 1, comprise: step S100, device substrate is provided, said device substrate has opposite first and second surface, and first surface has a plurality of devices; Step S110 provides first support substrates, and the said first support substrates surface has first insulating barrier; Step S120 is the intermediate layer with first insulating barrier, with the same first support substrates bonding of the first surface of device substrate; Step S130, the second surface of attenuate device substrate; Step S140 makes device on the second surface that exposes of device substrate; Step S150 provides second support substrates, and the said second support substrates surface has second insulating barrier; Step S160 is the centre buried regions with second insulating barrier, with the same second support substrates bonding of the second surface of device substrate; Step S170 removes the support substrates and first insulating barrier; Step S180 continues to make device on the first surface of the device substrate that exposes.
Accompanying drawing 2A is to shown in the accompanying drawing 2I being the process schematic representation of this embodiment.
Shown in the accompanying drawing 2A, refer step S100 provides device substrate 200, and said device substrate 200 has opposite first and second surface, and first surface has a plurality of devices, and this embodiment is with device 291 and 292 expressions.In this embodiment; Said device substrate 200 is made up of heavily doped layer 202 and lightly-doped layer 201; Said lightly-doped layer 201 comprises the first surface of device substrate 200, and said heavily doped layer 202 comprises the second surface of device substrate 200, in lightly-doped layer 201, is manufactured with a plurality of devices.The material of said device substrate 200 can be to comprise any one of monocrystalline silicon, and for monocrystalline substrate, said light dope and heavy doping can be adopted the boron ion.Said device 291 and 292 can be any one the common semiconductor device that comprises electric capacity, resistance and transistor; This embodiment also can comprise the device of more or lesser number with two devices as an example in other embodiment.
Shown in the accompanying drawing 2B, refer step S102 provides first support substrates 210, and said first support substrates 210 surfaces have first insulating barrier 211.Because first support substrates 210 mainly plays a supporting role, thus the material of first support substrates 210 can but to be not limited to be monocrystalline silicon.The material of said first insulating barrier 211 can be to be selected from any one of silica, silicon nitride and silicon oxynitride.
Shown in the accompanying drawing 2C, refer step S120 is the intermediate layer with first insulating barrier 211, with same first support substrates, 210 bondings of the first surface of device substrate 200.Said bonding can adopt any one in the common technologies such as comprising hydrophilic bonding and hydrophobic bonding.
Shown in the accompanying drawing 2D, refer step S130, the second surface of attenuate device substrate 200.This embodiment can be to remove heavily doped layer 202 through selective corrosion technology, and polishes the surface of the lightly-doped layer 201 that exposes.If what choose among the step S100 is not to have substrate light, heavily doped layer, this step also can be directly to adopt grinding technics attenuate device substrate 200 to target thickness, perhaps selects different reduction process according to the design feature of device substrate 200.
Shown in the accompanying drawing 2E, refer step S140 makes device on the second surface that exposes of device substrate 200, and this embodiment is with device 293 expressions.Said device 293 can be any one the common semiconductor device that comprises electric capacity, resistance and transistor, also can be the device in optoelectronic areas such as lens or anti-reflection film or micromechanics field.In this step; Because the first surface that has adopted bonding technology that device substrate 200 has been made device before protects; So can not impact to it; And since bonding first support substrates 210 as supporting construction, device substrate 200 can be allowed to as far as possible attenuate and needn't worry problems such as cracked.
Continuation is with reference to shown in the accompanying drawing 2E; It is the substrat structure sketch map of first embodiment of substrate according to the invention; Comprise first support substrates 210; First insulating barrier 211 on said first support substrates 210 surfaces and the device substrate 200 (also can be regarded as device layer after being thinned) on first insulating barrier, 211 surfaces, said device layer has the second surface and the first surface corresponding with second surface of exposure, all has a plurality of devices on said first surface and the second surface.Because first surface does not come out; So need do metal inserting column (Via) through hole (not shown) that electricity draws in the device 291 and 292 on the first surface will accomplish enough deeply; Guarantee that attenuate device substrate 200 can make it expose, so that technologies such as the contact of the back metal of back, PAD wiring.For the device substrate 200 that comprises lightly-doped layer 201 and heavily doped layer 202; Lightly-doped layer 201 to the lightly-doped layer 201 that metal inserting column through hole will run through device substrate 200 and heavily doped layer 202 are at the interface; After removing heavily doped layer 202, it is exposed like this.
Still device need be on first surface, made as if follow-up, following optional step can be continued to implement.
Shown in the accompanying drawing 2F, refer step S150 provides second support substrates 220, and said second support substrates 220 surfaces have second insulating barrier 221.Because second support substrates 220 mainly plays a supporting role, thus the material of second support substrates 220 can but to be not limited to be monocrystalline silicon.The material of said second insulating barrier 221 can be to be selected from any one of silica, silicon nitride and silicon oxynitride.
Shown in the accompanying drawing 2G, refer step S160 is 221 centre buried regions with second insulating barrier, with same second support substrates, 220 bondings of the second surface of device substrate 200.Said bonding can adopt any one in the common technologies such as comprising hydrophilic bonding and hydrophobic bonding.
Shown in the accompanying drawing 2H, refer step S170 removes first support substrates 210 and first insulating barrier 211.The method of removing for example can adopt corrosion or grinding etc.
Shown in the accompanying drawing 2I, refer step S180 continues to make device on the first surface of the device substrate that exposes 200, and this embodiment is with device 294 expressions.This step is an optional step, if subsequent technique need not continue to make device, also can be directly on first surface plated film or deposition and encapsulate and wait postchannel process making metal wiring layer, with the formation final products.
Continuation is with reference to shown in the accompanying drawing 2H (or 2I); It is the substrat structure sketch map of second embodiment of substrate according to the invention; Comprise second support substrates 220; Second insulating barrier 221 on said second support substrates 220 surfaces and the device substrate 200 (also can be regarded as device layer after being thinned) on second insulating barrier, 221 surfaces, said device layer has the first surface and the second surface corresponding with first surface of exposure, all has a plurality of devices on said first surface and the second surface.
Different with first embodiment is; Because second surface does not come out; To accomplish to arrive device substrate 200 and first insulating barrier 211 at the interface so need do metal inserting column (Via) through hole (not shown) that electricity draws in the device 293 on the second surface; After guaranteeing to remove first support substrates 210 and first insulating barrier 211 it is exposed, so that technologies such as the contact of the back metal of back, PAD wiring.
Below provide the embodiment of said method on the back-illuminated type cmos image sensor, accompanying drawing 3A is to shown in the accompanying drawing 3E being the process schematic representation of present embodiment.
In the back illumination formula cmos image sensor technology, after chip technology is accomplished, need mix at the back side of Chip, technologies such as annealing, silicon through hole, lens, optical filtering plated film, can use this technology;
(1) epitaxial light is mixed device layer on the heavily doped substrate, and make transistor in the above, unit such as transducer;
(2) carry out metal line, and planarization, wherein part metals inserting column (Via) through hole will arrive the heavily doped substrate layer of p++, so that the back metal of back contacts, the PAD wiring;
(3) silicon chip with planarization carries out Cement Composite Treated by Plasma with another sheet bonding pad, carries out 300 ℃ of low-temperature bondings then;
(4) use spin etching from stopping technology, remove the heavily doped layer on the device sheet, only stay and gently mix layer and following bonding pad thereof;
(5) carry out technologies such as photoetching, ion injection, annealing, film deposition, form doped region, lenticule, filter coating, passivation layer, and structure such as PAD contact point.
In addition, the method for the invention can also be with being used in the wafer encapsulation, and low temperature plasma bonding technology and corrosion can guarantee that from stopping technology wafer performance to be packaged can not pass through high temperature (be lower than 400 ℃, be optimized for 300 ℃) and heavily stressed process.Can also be applied to MEMS technology, graphical SOI manufacturing etc.Especially during the BESOI wafer is made, adopt this technology can make multilayer SOI wafer, and corrosion can guarantee each layer SOI good homogeneous property from stopping technology.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (16)
1. the method at the two-sided manufacturing device of substrate is characterized in that, comprises the steps:
Device substrate is provided, and said device substrate has opposite first and second surface, and first surface has a plurality of devices;
First support substrates is provided, and the said first support substrates surface has first insulating barrier;
With first insulating barrier is the intermediate layer, with the same first support substrates bonding of the first surface of device substrate;
The second surface of attenuate device substrate;
On the second surface that exposes of device substrate, make device.
2. method according to claim 1; It is characterized in that said device substrate is made up of heavily doped layer and lightly-doped layer, said lightly-doped layer comprises the first surface of device substrate; Said heavily doped layer comprises the second surface of device substrate, and said element manufacturing is in lightly-doped layer.
3. method according to claim 2 is characterized in that, in the step of said attenuate device substrate second surface, further comprises the step of removing heavily doped layer through selective corrosion technology.
4. method according to claim 3 is characterized in that, after removing heavily doped layer, further comprises the step on the surface of the lightly-doped layer that polishing exposes.
5. method according to claim 1 is characterized in that, further comprises the steps:
Second support substrates is provided, and the said second support substrates surface has second insulating barrier;
With second insulating barrier is the centre buried regions, with the same second support substrates bonding of the second surface of device substrate;
Remove first support substrates and first insulating barrier.
6. method according to claim 5 is characterized in that, after removing first support substrates and first insulating barrier, further is included in the step that continues to make device on the first surface of the device substrate that exposes.
7. method according to claim 5 is characterized in that, the material of said first insulating barrier and second insulating barrier is selected from any one of silica, silicon nitride and silicon oxynitride.
8. method according to claim 1 is characterized in that the material of said device substrate is a monocrystalline silicon.
9. substrate that adopts the said method of claim 1 to make; It is characterized in that; Comprise first support substrates; First insulating barrier on said first support substrates surface and the device layer of first surface of insulating layer, said device layer has the second surface and the first surface corresponding with second surface of exposure, all has a plurality of devices on said first surface and the second surface.
10. substrate according to claim 9 is characterized in that the material of said device layer is a monocrystalline silicon.
11. substrate according to claim 9 is characterized in that, the material of said first insulating barrier is selected from any one of silica, silicon nitride and silicon oxynitride.
12. substrate according to claim 9 is characterized in that, the device on the said first surface contains the metal inserting column through hole that runs through said device layer.
13. substrate that adopts the said method of claim 5 to make; It is characterized in that; Comprise second support substrates; Second insulating barrier on said second support substrates surface and the device layer of second surface of insulating layer, said device layer has the first surface and the second surface corresponding with first surface of exposure, all has a plurality of devices on said first surface and the second surface.
14. substrate according to claim 13 is characterized in that, the material of said device layer is a monocrystalline silicon.
15. substrate according to claim 13 is characterized in that, the material of said second insulating barrier is selected from any one of silica, silicon nitride and silicon oxynitride.
16. substrate according to claim 13 is characterized in that, the device on the said second surface contains the metal inserting column through hole that runs through said device layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012103039061A CN102842488A (en) | 2012-08-24 | 2012-08-24 | Method of double-sided manufacturing device of substrate and substrate |
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| CN2012103039061A CN102842488A (en) | 2012-08-24 | 2012-08-24 | Method of double-sided manufacturing device of substrate and substrate |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579103A (en) * | 2013-11-22 | 2014-02-12 | 上海新傲科技股份有限公司 | Three-dimensional lamination packing method and production method of image sensor |
| CN104347364A (en) * | 2014-09-23 | 2015-02-11 | 武汉新芯集成电路制造有限公司 | Preparation method of three-dimensional stacked device |
| CN105140251A (en) * | 2015-07-03 | 2015-12-09 | 豪威科技(上海)有限公司 | Back-illuminated image sensor wafer, back-illuminated image sensor chip and manufacturing method thereof |
| CN106549030A (en) * | 2016-10-10 | 2017-03-29 | 上海集成电路研发中心有限公司 | A kind of imageing sensor and preparation method thereof |
| CN106683979A (en) * | 2016-12-27 | 2017-05-17 | 上海新傲科技股份有限公司 | Method for cleaning bonding surface before bonding |
| WO2024021356A1 (en) * | 2022-07-29 | 2024-02-01 | 武汉新芯集成电路制造有限公司 | Tsv electrical connection structure having high aspect ratio and manufacturing method therefor |
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| CN101783318A (en) * | 2009-01-21 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Method and structure for reducing cross-talk in image sensor devices |
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| US20070020915A1 (en) * | 2005-07-08 | 2007-01-25 | Raytheon Company | MMIC having back-side multi-layer signal routing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103579103A (en) * | 2013-11-22 | 2014-02-12 | 上海新傲科技股份有限公司 | Three-dimensional lamination packing method and production method of image sensor |
| CN104347364A (en) * | 2014-09-23 | 2015-02-11 | 武汉新芯集成电路制造有限公司 | Preparation method of three-dimensional stacked device |
| CN105140251A (en) * | 2015-07-03 | 2015-12-09 | 豪威科技(上海)有限公司 | Back-illuminated image sensor wafer, back-illuminated image sensor chip and manufacturing method thereof |
| CN106549030A (en) * | 2016-10-10 | 2017-03-29 | 上海集成电路研发中心有限公司 | A kind of imageing sensor and preparation method thereof |
| CN106549030B (en) * | 2016-10-10 | 2019-08-20 | 上海集成电路研发中心有限公司 | A kind of image sensor and preparation method thereof |
| CN106683979A (en) * | 2016-12-27 | 2017-05-17 | 上海新傲科技股份有限公司 | Method for cleaning bonding surface before bonding |
| CN106683979B (en) * | 2016-12-27 | 2019-07-19 | 上海新傲科技股份有限公司 | Methods for cleaning bonding surfaces before bonding |
| WO2024021356A1 (en) * | 2022-07-29 | 2024-02-01 | 武汉新芯集成电路制造有限公司 | Tsv electrical connection structure having high aspect ratio and manufacturing method therefor |
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Application publication date: 20121226 |