CN102830127A

CN102830127A - Discrete fourier transform (DFT) frequency sampling-based sliver spectrum analysis IP soft core and test method thereof

Info

Publication number: CN102830127A
Application number: CN2012102988153A
Authority: CN
Inventors: 朱磊; 宋晓梅; 智文霞
Original assignee: Xian Polytechnic University
Current assignee: Xian Polytechnic University
Priority date: 2012-08-21
Filing date: 2012-08-21
Publication date: 2012-12-19
Anticipated expiration: 2032-08-21
Also published as: CN102830127B

Abstract

The sliver spectrum analysis IP soft core based on DFT frequency sampling and its test method include a sliver spectrum analysis calculation unit, which includes FPGA device hardware, and the FPGA device hardware uses HDL language to perform frequency sampling based on DFT The sliver spectrum analysis algorithm is packaged as a 55-channel sliver spectrum analysis IP soft core, which includes 55 channels with different center frequencies and bandwidths. Each channel includes a set of DFT-based Frequency sampling IP sub-core, IP sub-core includes input module, state machine, multiplier, accumulator module and output module. The sliver spectrum analysis IP core based on DFT frequency sampling can be transplanted to the FPGA device hardware platform through simple configuration, and independently complete the spectrum analysis task of the digital sliver signal. It has strong versatility, good portability, and adopts parallel computing in real time. Sexual characteristics.

Description

Sliver Spectrum Analysis IP Soft Core Based on DFT Frequency Sampling and Its Testing Method

技术领域 technical field

本发明属于纺织品在线监测与信号处理设备技术领域，涉及一种纺织纱条均匀度在线检测系统，具体涉及一种基于DFT频率采样的纱条波谱分析IP软核，本发明还涉及上述纱条波谱分析IP软核的测试方法。The invention belongs to the technical field of textile on-line monitoring and signal processing equipment, and relates to an online detection system for textile yarn evenness, in particular to a yarn spectrum analysis IP soft core based on DFT frequency sampling, and the invention also relates to the above-mentioned yarn spectrum Analyze the test method of IP soft core.

背景技术 Background technique

纱条不匀是衡量纱线品质的主要指标之一，也是影响布面外观品质的决定性因素，纱条不匀的检测是纺纱生产中实施有效质量控制的重要手段。纺织工业中通常采用波谱分析法对纱条不匀进行检测，波谱分析的实质是频谱分析。Sliver unevenness is one of the main indicators to measure yarn quality, and it is also a decisive factor affecting the appearance quality of cloth surface. The detection of sliver unevenness is an important means to implement effective quality control in spinning production. In the textile industry, spectral analysis is usually used to detect yarn unevenness, and the essence of spectral analysis is spectrum analysis.

理论上，纱条不匀信号包含有无数的波长，连续分布在0～∞的区间，每一分量的振幅和相位都是随机的谐波分量。当因某种机械原因使纱条产生明显的周期性不匀，即出现叠加于连续波谱上的离散波长分量时，解决这一问题的理想方法是在无限长的区间构成包含从0～∞的所有波长的波谱图，然而所有波长的波谱图是无法得到的。由于生产实践中只关心某一特定范围内的波长，因此，生产中将波长限定在这一范围内，可以大大减少了数据的处理量。然而在所限定的波长范围内波谱图上仍具有无限多个点，还需对波长区间进行划分，将所限定的总波长范围分成若干组，称为波道（频道），每一波道的数值以波道内所含的一组波长分量的组中值代表，这样就构成阶梯形的波谱图。根据这些理论并结合实际，乌斯特公司最早提出了纱条波谱分析的间接方法对纱条进行质量检测，即将纱条信号主要波谱所对应的0～300Hz频段分成55个频道，这55个频道的频率值为一等比级数，其最低频道的上、下截止频率分别为0.168Hz和0.164Hz，最高频道的上、下截止频率为299.525Hz和292.393Hz，相邻两个频道间的谐振频率之比为

让纺织纱条信号同时通过55个带通滤波器，对每个滤波器的输出进行记录便可得到纱条信号的频谱分布图，再根据公式λ=υ/f将频率转换成波长，将纱条的频谱图转换成波谱图输出并显示。纱条波谱图（频谱图）是在频率域（波长域）里表征纱条粗细不匀的状态，可用来定量分析纱条条干的各种周期性不匀。目前纺织行业中均以乌斯特公司对纱条信号波长的限定范围及划分作为行业标准。Theoretically, the sliver uneven signal contains countless wavelengths, which are continuously distributed in the interval from 0 to ∞, and the amplitude and phase of each component are random harmonic components. When the sliver has obvious periodic unevenness due to some mechanical reason, that is, there are discrete wavelength components superimposed on the continuous wave spectrum, the ideal way to solve this problem is to form an infinitely long interval from 0 to ∞ Spectrograms for all wavelengths, however spectrograms for all wavelengths are not available. Since the production practice only cares about the wavelength within a specific range, limiting the wavelength within this range during production can greatly reduce the amount of data processing. However, there are still infinitely many points on the spectrogram within the limited wavelength range, and the wavelength range needs to be divided, and the limited total wavelength range is divided into several groups, which are called channels (channels). The value is represented by the group median value of a group of wavelength components contained in the channel, thus forming a ladder-shaped spectrogram. According to these theories and combined with reality, Uster Company first proposed the indirect method of yarn spectrum analysis to detect the quality of yarn, that is, the 0-300Hz frequency band corresponding to the main spectrum of yarn signal is divided into 55 channels, and these 55 channels The frequency value of the frequency value is a proportional series, the upper and lower cut-off frequencies of the lowest channel are 0.168Hz and 0.164Hz respectively, the upper and lower cut-off frequencies of the highest channel are 299.525Hz and 292.393Hz, the resonance between two adjacent channels The frequency ratio is

Let the textile yarn signal pass through 55 band-pass filters at the same time, and record the output of each filter to obtain the spectrum distribution diagram of the yarn signal, and then convert the frequency into a wavelength according to the formula λ=υ/f, and convert the yarn The spectrogram of the bar is converted into a spectrogram output and displayed. The sliver spectrogram (spectrogram) is used to characterize the uneven thickness of the sliver in the frequency domain (wavelength domain), and can be used to quantitatively analyze various periodic unevenness of the sliver. At present, in the textile industry, Uster's limited range and division of yarn signal wavelengths are used as industry standards.

传统波谱分析的方法有两种，第一种方法是Uster-ⅡB波谱仪的滤波分析方法，直接通过多组模拟滤波器对纱条传感器送入的模拟信号进行滤波，然后将滤波结果进行处理并以波谱图的形式输出。该方法需要多组模拟滤波器，由于多组模拟滤波器所需硬件复杂，故实现波谱分析的电路复杂、庞大，可靠性及稳定性很难保证。随着数字信号处理技术的不断发展，数字滤波器拥有模拟滤波器所无法代替的新特性，例如：数字滤波器无漂移，能处理低频信号，其频响特性可做到非常接近于理想滤波器的特性，因此数字滤波器已取代传统的模拟滤波器而广泛应用于波谱分析中。但无论是模拟滤波法还是数字滤波法，滤波法都是时域分析方法，是对信号频谱的间接获取。第二种方法是对纱条传感器送入的模拟信号采样后直接进行全频段傅里叶变换，得到纱条信号的频域幅值，组成频谱图，然后按照相应的公式将其转换为波谱图的形式输出。这种方法采用傅里叶变换得到纱条信号的全频道波谱图，然而波谱分析关心的只是0～300Hz这一频段范围内的部分通道的频谱，所以直接计算全频道的频谱就会存在较大一部分无用数据的计算，大大增加了计算的时间复杂度和空间复杂度。There are two traditional spectral analysis methods. The first method is the filter analysis method of the Uster-IIB spectrometer, which directly filters the analog signal sent by the sliver sensor through multiple sets of analog filters, and then processes the filtered results and Output as a spectrogram. This method requires multiple groups of analog filters. Since the hardware required by multiple groups of analog filters is complex, the circuit for spectrum analysis is complex and huge, and reliability and stability are difficult to guarantee. With the continuous development of digital signal processing technology, digital filters have new characteristics that cannot be replaced by analog filters, for example: digital filters have no drift, can handle low-frequency signals, and their frequency response characteristics can be very close to ideal filters Therefore, digital filters have replaced traditional analog filters and are widely used in spectrum analysis. However, whether it is an analog filtering method or a digital filtering method, the filtering method is a time-domain analysis method, which is an indirect acquisition of the signal spectrum. The second method is to directly perform full-band Fourier transform after sampling the analog signal sent by the sliver sensor to obtain the frequency domain amplitude of the sliver signal, form a spectrogram, and then convert it into a spectrogram according to the corresponding formula output in the form of . This method uses Fourier transform to obtain the full-channel spectrum of the sliver signal. However, the spectrum analysis is only concerned with the spectrum of some channels within the frequency range of 0-300 Hz, so directly calculating the spectrum of the full channel will have a large problem. The calculation of a part of useless data greatly increases the time complexity and space complexity of the calculation.

发明内容 Contents of the invention

本发明的目的是提供一种基于DFT频率采样的纱条波谱分析IP软核，该纱条波谱分析IP软核具有通用性强、实时性好以及开发简单的特点。The object of the present invention is to provide a sliver spectrum analysis IP soft core based on DFT frequency sampling. The sliver spectrum analysis IP soft core has the characteristics of strong versatility, good real-time performance and simple development.

本发明所采用的技术方案是，基于DFT频率采样的纱条波谱分析IP软核，包括有纱条波谱分析计算单元，纱条波谱分析计算单元包括有FPGA器件硬件，FPGA器件硬件内利用HDL语言将基于DFT频率采样的纱条波谱分析算法封装为55通道纱条波谱分析IP软核，55通道纱条波谱分析IP软核包括有中心频率不同且带宽大小不等的55个频道，每个频道包括有一套基于DFT频率采样的IP子核，IP子核包括有输入模块、状态机、两个乘法器、两个累加器模块以及输出模块，输入模块包括有xvalues模块、实部常系数avalues模块、虚部常系数bvalues模块，状态机内设置有state_m模块，乘法器内设置有mult模块，累加器模块包括有实部累加accax模块和虚部累加accbx模块，The technical solution adopted in the present invention is that the sliver spectrum analysis IP soft core based on DFT frequency sampling includes a sliver spectrum analysis calculation unit, and the sliver spectrum analysis calculation unit includes FPGA device hardware, and the HDL language is utilized in the FPGA device hardware The sliver spectrum analysis algorithm based on DFT frequency sampling is packaged into a 55-channel sliver spectrum analysis IP soft core. The 55-channel sliver spectrum analysis IP soft core includes 55 channels with different center frequencies and different bandwidths. Each channel It includes a set of IP sub-core based on DFT frequency sampling. The IP sub-core includes an input module, a state machine, two multipliers, two accumulator modules, and an output module. The input module includes an xvalues module and avalues module with real part constant coefficients , the imaginary part constant coefficient bvalues module, the state_m module is set in the state machine, the mult module is set in the multiplier, and the accumulator module includes a real part accumulating accax module and an imaginary part accumulating accbx module,

输入模块通过导线与状态机连接，状态机分别通过导线与xvalues模块、实部常系数avalues模块、虚部常系数bvalues模块连接，实部常系数avalues模块通过导线与一个乘法器中的mult模块、实部累加accax模块、一个触发器DFFE依次连接，虚部常系数bvalues模块通过导线与另一个乘法器中的mult模块、虚部累加accbx模块、另一个触发器DFFE依次连接，xvalues模块通过导线与两个乘法器分别连接。The input module is connected to the state machine through wires, and the state machine is respectively connected to the xvalues module, the real part constant coefficient avalues module, and the imaginary part constant coefficient bvalues module through wires, and the real part constant coefficient avalues module is connected to a mult module in a multiplier through wires, The real part accumulation accax module and a flip-flop DFFE are connected sequentially, the imaginary part constant coefficient bvalues module is connected with the mult module in another multiplier, the imaginary part accumulation accbx module, and another flip-flop DFFE through wires, and the xvalues module is connected with the The two multipliers are connected separately.

基于DFT频率采样的纱条波谱分析IP软核的检测方法，具体按照以下步骤实施：The detection method of sliver spectrum analysis IP soft core based on DFT frequency sampling is implemented according to the following steps:

这里以纱条波谱分析IP核的第一道波谱分析为例，其余54频道的波谱分析原理与实现过程均与第1频道相同；Here, the first spectrum analysis of the sliver spectrum analysis IP core is taken as an example, and the spectrum analysis principle and implementation process of the remaining 54 channels are the same as those of the first channel;

步骤1，获得数字纱条信号Step 1, get the digital sliver signal

纱条波谱分析IP软核中，In the sliver spectrum analysis IP soft core,

1）首先将纱条均匀度检测传感器获得的模拟纱条信号经A/D转换器转换，模拟纱条信号被转换为数字纱条信号；1) First, the analog sliver signal obtained by the sliver uniformity detection sensor is converted by the A/D converter, and the analog sliver signal is converted into a digital sliver signal;

2）将数字纱条信号送入输入模块，输入模块内的xvalues模块直接将输入的数字纱条信号即采样点值存到FPGA器件硬件内部的存储器中；2) Send the digital sliver signal to the input module, and the xvalues module in the input module directly stores the input digital sliver signal, that is, the sampling point value, into the internal memory of the FPGA device hardware;

步骤2，将数字纱条信号进行DFT变换Step 2, perform DFT transformation on the digital sliver signal

对步骤1中获取的数字纱条信号进行DFT变换Perform DFT transformation on the digital sliver signal obtained in step 1

1）进行一次DFT运算要用到6300个采样值，xvalues模块直接将采样值存到FPGA器件硬件内部的存储器中，输入模块中的xvalues模块、实部常系数avalues模块、虚部常系数bvalues模块都根据输入sel[12..0]的值进入不同的分支，输出不同的存储值；1) It takes 6300 sampling values to perform a DFT operation. The xvalues module directly stores the sampling values in the internal memory of the FPGA device hardware. The xvalues module, the real part constant coefficient avalues module, and the imaginary part constant coefficient bvalues module in the input module Both enter different branches according to the value of the input sel[12..0], and output different storage values;

2）根据DFT变换公式对数字纱条信号进行DFT变换，2) Perform DFT transformation on the digital yarn signal according to the DFT transformation formula,

DFT变换公式为：The DFT transformation formula is:

$X x ((k k)) = = DFT DFT [[x x ((n no))]] = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) {e e}^{- - j j \frac{22 π π}{P P} kn k n} = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) ((cos cos \frac{22 π π}{P P} kn k n - - j j sin sin \frac{22 π π}{P P} kn k n))$

DFT变换公式中，频域中有效频点与k的对应关系为：其中f表示频域中175个有效频点的频率值；In the DFT transformation formula, the corresponding relationship between effective frequency points and k in the frequency domain is: Where f represents the frequency values of 175 effective frequency points in the frequency domain;

令 $a_{k} (n) = \cos \frac{2 π}{P} kn,$ $b_{k} (n) = \sin \frac{2 π}{P} kn,$ make $a_{k} (no) = \cos \frac{2 π}{P} k n,$ $b_{k} (no) = \sin \frac{2 π}{P} k n,$

则DFT变换公式可写为：Then the DFT transformation formula can be written as:

$X x ((k k)) = = DFT DFT [[x x ((n no))]] = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) \times \times [[{a a}_{k k} ((n no)) - - j j {b b}_{k k} ((n no))]]$

当k值一定时，a_k(n)和b_k(n)是关于n的一组值，n的取值范围为[0，L-1]，a_k(n)和b_k(n)是对应于0≤n≤L-1的L个常量，将a_k(n)和b_k(n)计算好后预先存放到外部存储器内，当数字纱条信号输入时将a_k(n)和b_k(n)的值读入FPGA器件硬件内参与运算；When the k value is fixed, a _k (n) and b _k (n) are a set of values about n, and the value range of n is [0, L-1], a _k (n) and b _k (n) are L constants corresponding to 0≤n≤L-1, a _k (n) and b _k (n) are calculated and stored in the external memory in advance, when the digital yarn signal is input, a _k (n) and the value of b _k (n) is read into the FPGA device hardware to participate in the operation;

DFT运算主要是乘-累加运算，DFT运算与滤波器的实现相似且更简单，实现过程只需在乘-累加的基础上外加一个状态机来控制乘累加的时序；乘法器内设置有mult模块，输入乘数和被乘数分别对应于14位输入的数字纱条信号值、实部常系数avalues模块和虚部常系数bvalues模的14位常系数值，输出结果用28位二进制补码表示；累加模器块包括实部累加accax模块和虚部累加accbx模块，实部累加accax模块与虚部累加accbx模块的运算相同；实部累加accax模块由输入时钟信号clk、输出触发信号first_d、mult模块输出值同时又是累加器模块的输入值ax[27..0]以及累加器模块的实部累加结果值accax[36..0]组成，实部累加accax模块进行将输入的数字纱条信号值与实部系数a_k乘积的累加运算；将输入的6300个数字纱条信号即采样值进行DFT运算的实部和虚部计算的结果进行累加并输出，最终得到6300个采样值DFT的实部A_k和虚部B_k；The DFT operation is mainly a multiply-accumulate operation. The implementation of the DFT operation and the filter is similar and simpler. The implementation process only needs to add a state machine on the basis of the multiply-accumulate to control the timing of the multiply-accumulate; the multiplier is equipped with a mult module. , the input multiplier and multiplicand correspond to the 14-bit input digital sliver signal value, the 14-bit constant coefficient value of the real part constant coefficient avalues module and the imaginary part constant coefficient bvalues modulo, and the output result is represented by 28-bit two's complement ;The accumulation module block includes a real part accumulation accax module and an imaginary part accumulation accbx module. The output value of the module is also composed of the input value ax[27..0] of the accumulator module and the accumulative result value accax[36..0] of the real part of the accumulator module. The cumulative operation of the product of the signal value and the real part coefficient a _k ; the 6300 input digital sliver signals, that is, the sampled values, are accumulated and output for the real part and imaginary part of the DFT operation, and finally the 6300 sampled values of DFT are obtained. real part A _k and imaginary part B _k ;

在新一轮累加循环开始时将上一次的累加结果清零，状态机共有6303个状态，对应6302个sel信号和一个空闲状态，该空闲状态为idle状态与default状态，状态机在1状态到6302状态之间不断的进行循环，同时会向xvalues模块、实部常系数avalues模块、虚部常系数bvalues模块输出一个新的sel值，由于输入信号与常系数已经和sel信号一一对应，状态机每输出一个sel信号值，实部常系数avalues模块和虚部常系数bvalues模块都会输出一个相应的值，并送入乘法器内，从而使对应的输入信号值与常系数做乘法运算，最后将乘积结果送入累加器模块，状态机会在每个循环的开始和结束，分别将first信号与follow信号置1，当first信号为1时，累加器模块将会把上一轮循环的结果清零，开始新一轮累加计算；当follow信号为1时，触发器DEEF才开始输出，以此达到控制输出的目的。At the beginning of a new round of accumulation cycle, the previous accumulation result is cleared. The state machine has a total of 6303 states, corresponding to 6302 sel signals and an idle state. The idle state is idle state and default state. The state machine is in state 1 to The 6302 state is continuously cycled, and at the same time, a new sel value will be output to the xvalues module, the real part constant coefficient avalues module, and the imaginary part constant coefficient bvalues module. Since the input signal and the constant coefficient have one-to-one correspondence with the sel signal, the state Every time the machine outputs a sel signal value, the real part constant coefficient avalues module and the imaginary part constant coefficient bvalues module will output a corresponding value, and send it to the multiplier, so that the corresponding input signal value is multiplied by the constant coefficient, and finally Send the result of the product to the accumulator module, and the state machine will set the first signal and the follow signal to 1 at the beginning and end of each cycle. When the first signal is 1, the accumulator module will clear the result of the previous cycle. Zero, start a new round of cumulative calculation; when the follow signal is 1, the trigger DEEF will start to output, so as to achieve the purpose of controlling the output.

步骤3，计算波谱分析关心的幅值M_k Step 3, calculate the amplitude M _k concerned by spectral analysis

根据步骤2中计算出DFT的实部A_k和虚部B_k，进行均方根运算，公式如下，计算出波谱分析关心的幅值M_k；According to the real part A _k and imaginary part B _k of DFT calculated in step 2, carry out the root mean square calculation, the formula is as follows, and calculate the amplitude M _k concerned by the spectral analysis;

波谱分析关心的幅值M_k的计算公式如下:The calculation formula of the amplitude _Mk concerned by spectrum analysis is as follows:

${M m}_{k k} = = \sqrt[22]{{A A}_{k k}^{22} + + {B B}_{}^{k k}}$

根据波谱分析IP软核的6300个采样值，计算出175个频点的幅值M_k；According to the 6300 sampling values of the spectrum analysis IP soft core, the amplitude M _k of 175 frequency points is calculated;

步骤4，获得纱条信号全频段波谱Step 4, obtain the full-band spectrum of the sliver signal

纱条波谱分析的全频段55个频道中，每个频道内都包含1个或多个频点的幅值M_k，频带带宽越宽频道内的频点数就越多，55个频道中每个频道的最终输出波谱为每个频道内所有频点幅值M_k的均值，而55个频道波谱的组合即为全频段纱条信号波谱。Among the 55 channels in the full frequency band of yarn spectrum analysis, each channel contains the amplitude M _k of one or more frequency points. The wider the frequency band bandwidth, the more frequency points in the channel. Each of the 55 channels The final output spectrum of is the mean value of the amplitude M _k of all frequency points in each channel, and the combination of 55 channel spectra is the full-band yarn signal spectrum.

本发明的有益效果是，The beneficial effect of the present invention is,

1）采用DFT频率采样新算法代替传统波谱分析方法中所采用的带通滤波方式，实现对纱条波谱的分析计算，可有效减少波谱分析的计算量；1) The new algorithm of DFT frequency sampling is used to replace the band-pass filtering method used in the traditional spectrum analysis method to realize the analysis and calculation of the yarn spectrum, which can effectively reduce the calculation amount of spectrum analysis;

2）在基于DFT频率采样的新算法中，采用非等间距采样方式，可减少DFT计算点数，进一步减少计算量；2) In the new algorithm based on DFT frequency sampling, the non-equidistant sampling method can reduce the number of DFT calculation points and further reduce the calculation amount;

3）在纱条波谱分析的全频段55个频道中，每个频道分别采用DFT频域采样的纱条波谱分析新算法实现各频道的波谱分析，而各频道之间的波谱分析算法采用并行组织结构，并行实现各频道的波谱分析计算，从而再次提升全波段波谱分析计算速度，有效提高全波段波谱分析计算的实时性；3) Among the 55 channels in the full frequency band of sliver spectrum analysis, each channel adopts the new sliver spectrum analysis algorithm of DFT frequency domain sampling to realize the spectrum analysis of each channel, and the spectrum analysis algorithm between channels adopts parallel organization The structure realizes the spectrum analysis and calculation of each channel in parallel, thereby further improving the calculation speed of the full-band spectrum analysis and effectively improving the real-time performance of the full-band spectrum analysis and calculation;

4）通过HDL硬件描述语言，将并行组织的各频道DFT频域采样的纱条波谱分析新算法封装为能独立完成全频段纱条信号波谱分析的IP软核，从而方便将IP软核配置并下载到FPGA硬件平台，完成波谱分析的实时计算。4) Through the HDL hardware description language, the new algorithm for sliver spectrum analysis of DFT frequency domain sampling of each channel organized in parallel is packaged into an IP soft core that can independently complete the spectrum analysis of the full-band sliver signal, so that it is convenient to configure the IP soft core and Download to the FPGA hardware platform to complete the real-time calculation of spectrum analysis.

附图说明 Description of drawings

图1是本发明中FPGA硬件平台下基于DFT频域采样算法实现纱条信号55通道波谱分析的原理框图；Fig. 1 is the functional block diagram based on the DFT frequency domain sampling algorithm to realize yarn signal 55 channel spectrum analysis under the FPGA hardware platform in the present invention;

图2是本发明中基于DFT频域采样的纱条波谱分析IP核内55通道中一个通道内的纱条信号波谱分析原理框图；Fig. 2 is the sliver signal spectrum analysis principle block diagram in a passage in 55 passages in the sliver spectrum analysis IP core based on DFT frequency domain sampling among the present invention;

图3是本发明中纱条波谱分析IP核内55通道中一个通道内的纱条信号波谱分析的HDL语言与原理图混合输入顶层原理图；Fig. 3 is that the HDL language of the sliver signal spectrum analysis in the sliver signal spectrum analysis in a passage in 55 passages of IP kernel among the present invention mixes input top-level schematic diagram;

图中，1.xvalues模块，2.实部常系数avalues模块，3.虚部常系数bvalues模块，4.state m模块，5.mult模块，6.实部累加accax模块，7.虚部累加accbx模块，8.FPGA器件硬件，9.55通道纱条波谱分析IP软核，10.IP子核，11.输入模块，12.状态机，13.乘法器，14.累加器模块，15输出模块。In the figure, 1. xvalues module, 2. real part constant coefficient avalues module, 3. imaginary part constant coefficient bvalues module, 4. state m module, 5. mult module, 6. real part accumulation accax module, 7. imaginary part accumulation accbx module, 8.FPGA device hardware, 9.55 channel sliver spectrum analysis IP soft core, 10. IP sub-core, 11. input module, 12. state machine, 13. multiplier, 14. accumulator module, 15 output module.

具体实施方式 Detailed ways

下面结合附图和具体实施方式对本发明进行详细说明。The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

基于DFT频率采样的纱条波谱分析IP软核，内部结构如图1及图2所示，包括有纱条波谱分析计算单元，纱条波谱分析计算单元包括有FPGA器件硬件8，FPGA器件硬件8内利用HDL语言将基于DFT频率采样的纱条波谱分析算法封装为55通道纱条波谱分析IP软核9，55通道纱条波谱分析IP软核9包括有中心频率不同且带宽大小不等的55个频道，每个频道包括有一套基于DFT频率采样的IP子核10，IP子核10包括有输入模块11、状态机12、两个乘法器13、两个累加器模块14以及输出模块15，输入模块11包括有xvalues模块1、实部常系数avalues模块2、虚部常系数bvalues模块3，状态机12内设置有state_m模块4，乘法器13内设置有mult模块5，累加器模块14包括有实部累加accax模块6和虚部累加accbx模块7，The sliver spectrum analysis IP soft core based on DFT frequency sampling, the internal structure is shown in Figure 1 and Figure 2, including the sliver spectrum analysis calculation unit, the sliver spectrum analysis calculation unit includes FPGA device hardware 8, FPGA device hardware 8 The sliver spectrum analysis algorithm based on DFT frequency sampling is packaged into a 55-channel sliver spectrum analysis IP soft core 9 by using HDL language. The 55-channel sliver spectrum analysis IP soft core 9 includes 55 channels with different center frequencies and different bandwidths. channels, each channel includes a set of IP sub-core 10 based on DFT frequency sampling, the IP sub-core 10 includes an input module 11, a state machine 12, two multipliers 13, two accumulator modules 14 and an output module 15, Input module 11 includes xvalues module 1, real part constant coefficient avalues module 2, imaginary part constant coefficient bvalues module 3, state_m module 4 is arranged in state machine 12, mult module 5 is arranged in multiplier 13, accumulator module 14 includes There are accumulative accax module 6 for real part and accbx module 7 for imaginary part accumulative,

输入模块11通过导线与状态机12连接，状态机12分别通过导线与xvalues模块1、实部常系数avalues模块2、虚部常系数bvalues模块3连接，实部常系数avalues模块2通过导线与一个乘法器13中的mult模块5、实部累加accax模块6、一个触发器DFFE依次连接，虚部常系数bvalues模块3通过导线与另一个乘法器13中的mult模块5、虚部累加accbx模块7、另一个触发器DFFE依次连接，xvalues模块1通过导线与两个乘法器13分别连接。The input module 11 is connected to the state machine 12 through wires, and the state machine 12 is connected to the xvalues module 1, the real part constant coefficient avalues module 2, and the imaginary part constant coefficient bvalues module 3 respectively through wires, and the real part constant coefficient avalues module 2 is connected to a The mult module 5 in the multiplier 13, the real part accumulation accax module 6, and a flip-flop DFFE are connected in sequence, and the imaginary part constant coefficient bvalues module 3 is connected with the mult module 5 and the imaginary part accumulation accbx module 7 in another multiplier 13 through wires , another flip-flop DFFE is connected in sequence, and the xvalues module 1 is connected to two multipliers 13 respectively through wires.

基于DFT频率采样的纱条波谱分析IP软核的检测方法，如图2及图3所示，具体按照以下步骤实施：The detection method of the sliver spectrum analysis IP soft core based on DFT frequency sampling, as shown in Figure 2 and Figure 3, is implemented according to the following steps:

步骤1，获得数字纱条信号Step 1, get the digital sliver signal

纱条波谱分析IP软核中，如图1所示，In the sliver spectrum analysis IP soft core, as shown in Figure 1,

2）将数字纱条信号送入输入模块11，输入模块11内的xvalues模块1直接将输入的数字纱条信号即采样点值存到FPGA器件硬件8内部的存储器中；2) The digital sliver signal is sent to the input module 11, and the xvalues module 1 in the input module 11 directly stores the input digital sliver signal, that is, the sampling point value, in the internal memory of the FPGA device hardware 8;

1）进行一次DFT运算要用到6300个采样值，xvalues模块1直接将采样值存到FPGA器件硬件8内部的存储器中，输入模块11中的xvalues模块1、实部常系数avalues模块2、虚部常系数bvalues模块3都根据输入sel[12..0]的值进入不同的分支，输出不同的存储值；1) It takes 6300 sampling values to perform a DFT operation. The xvalues module 1 directly stores the sampling values in the internal memory of the FPGA device hardware 8. The xvalues module 1 in the input module 11, the real part constant coefficient avalues module 2, and the imaginary Partial constant coefficient bvalues module 3 enters different branches according to the value of input sel[12..0], and outputs different storage values;

DFT变换公式为：The DFT transformation formula is:

DFT变换公式中，频域中有效频点与k的对应关系为：

其中f表示频域中175个有效频点的频率值；In the DFT transformation formula, the corresponding relationship between effective frequency points and k in the frequency domain is:

Where f represents the frequency values of 175 effective frequency points in the frequency domain;

当k值一定时，a_k(n)和b_k(n)是关于n的一组值，n的取值范围为[0，L-1]，a_k(n)和b_k(n)是对应于0≤n≤L-1的L个常量，将a_k(n)和b_k(n)计算好后预先存放到外部存储器内，当数字纱条信号输入时将a_k(n)和b_k(n)的值读入FPGA器件硬件8内参与运算；When the k value is fixed, a _k (n) and b _k (n) are a set of values about n, and the value range of n is [0, L-1], a _k (n) and b _k (n) are L constants corresponding to 0≤n≤L-1, a _k (n) and b _k (n) are calculated and stored in the external memory in advance, when the digital yarn signal is input, a _k (n) and the value of b _k (n) is read into the FPGA device hardware 8 to participate in the calculation;

DFT运算主要是乘-累加运算，DFT运算与滤波器的实现相似且更简单，实现过程只需在乘-累加的基础上外加一个状态机12来控制乘累加的时序；乘法器13内设置有mult模块5，输入乘数和被乘数分别对应于14位输入的数字纱条信号值、实部常系数avalues模块6和虚部常系数bvalues模块7的14位常系数值，输出结果用28位二进制补码表示；累加模器块14包括实部累加accax模块6和虚部累加accbx模块7，实部累加accax模块6与虚部累加accbx模块7的运算相同；实部累加accax模块6由输入时钟信号clk、输出触发信号first_d、mult模块5输出值同时又是累加器模块14的输入值ax[27..0]以及累加器模块14的实部累加结果值accax[36..0]组成，实部累加accax模块6进行将输入的数字纱条信号值与实部系数a_k乘积的累加运算；将输入的6300个数字纱条信号即采样值进行DFT运算的实部和虚部计算的结果进行累加并输出，最终得到6300个采样值DFT的实部A_k和虚部B_k；The DFT operation is mainly a multiplication-accumulation operation, and the realization of the DFT operation and the filter is similar and simpler. The realization process only needs to add a state machine 12 on the basis of the multiplication-accumulation to control the timing of the multiplication-accumulation; the multiplier 13 is provided with mult module 5, the input multiplier and the multiplicand correspond to the 14-bit input digital yarn signal value, the 14-bit constant coefficient value of the real part constant coefficient avalues module 6 and the imaginary part constant coefficient bvalues module 7, and the output result is 28 Bit two's complement representation; accumulation module block 14 comprises real part accumulating accax module 6 and imaginary part accumulating accbx module 7, and the computing of real part accumulating accax module 6 and imaginary part accumulating accbx module 7 is identical; real part accumulating accax module 6 is composed of The input clock signal clk, the output trigger signal first_d, and the output value of the mult module 5 are also the input value ax[27..0] of the accumulator module 14 and the real part accumulation result value accax[36..0] of the accumulator module 14. Composition, the real part accumulating accax module 6 carries out the cumulative operation of multiplying the input digital sliver signal value and the real part coefficient a _k ; the real part and imaginary part calculation of the 6300 digital sliver signals that are input, that is, the sampled values, of the DFT operation The results are accumulated and output, and finally the real part A _k and the imaginary part B _k of the DFT of 6300 sampled values are obtained;

在新一轮累加循环开始时将上一次的累加结果清零，状态机12共有6303个状态，对应6302个sel信号和一个空闲状态，该空闲状态为idle状态与default状态，状态机12在1状态到6302状态之间不断的进行循环，同时会向xvalues模块1、实部常系数avalues模块2、虚部常系数bvalues模块3输出一个新的sel值，由于输入信号与常系数已经和sel信号一一对应，状态机12每输出一个sel信号值，实部常系数avalues模块2和虚部常系数bvalues模块3都会输出一个相应的值，并送入乘法器13内，从而使对应的输入信号值与常系数做乘法运算，最后将乘积结果送入累加器模块14，状态机12会在每个循环的开始和结束，分别将first信号与follow信号置1，当first信号为1时，累加器模块14将会把上一轮循环的结果清零，开始新一轮累加计算；当follow信号为1时，触发器DEEF才开始输出，以此达到控制输出的目的。At the beginning of a new accumulation cycle, the last accumulation result is cleared. The state machine 12 has 6303 states, corresponding to 6302 sel signals and an idle state. The idle state is idle state and default state. The state machine 12 is in 1 State to 6302 state is continuously cycled, and at the same time, a new sel value will be output to xvalues module 1, real part constant coefficient avalues module 2, imaginary part constant coefficient bvalues module 3, because the input signal and the constant coefficient have been combined with the sel signal One-to-one correspondence, every time the state machine 12 outputs a sel signal value, the real part constant coefficient avalues module 2 and the imaginary part constant coefficient bvalues module 3 will output a corresponding value, and send it into the multiplier 13, so that the corresponding input signal Value and constant coefficient are multiplied, and finally the multiplication result is sent to the accumulator module 14. The state machine 12 will set the first signal and the follow signal to 1 respectively at the beginning and end of each cycle. When the first signal is 1, the accumulated The controller module 14 will clear the result of the previous cycle and start a new round of cumulative calculation; when the follow signal is 1, the trigger DEEF will start to output, so as to achieve the purpose of controlling the output.

${M m}_{k k} = = \sqrt[22]{{A A}_{k k}^{22} + + {B B}_{}^{k k}}$

由于纱条波谱分析IP软核的整个运算以乘-累加为主，可能会造成最终结果或中间过程数值的溢出，为防止运算结果数值溢出，同时又尽可能的在保证计算精度的情况下缩减参与运算参量的字长，经过MATLAB数学软件仿真验证，本发明中确定输入信号x(n)，常系数a_k和b_k均用14位二进制码表示，而乘-累加结果A_k和B_k用37位二进制补码表示；Since the entire operation of the sliver spectrum analysis IP soft core is mainly multiplication-accumulation, it may cause the overflow of the final result or the value of the intermediate process. Participate in the word length of operation parameter, through MATLAB mathematical software emulation verification, determine input signal x(n) among the present invention, constant coefficient a _k and b _k all represent with 14 binary codes, and multiplication-accumulation result A _k and B _k Represented by 37-bit two's complement;

纱条波谱分析IP核内55通道中的一个通道内的纱条信号波谱分析的HDL语言与原理图混合输入顶层原理图如图3所示。Yarn Spectrum Analysis The HDL language and schematic diagram of the yarn signal spectrum analysis in one of the 55 channels in the IP core are mixed and input as shown in Figure 3.

状态机12内的state_m模块4由输入clk、reset和输出follow、first、sel[12..0]组成，主要负责整个频率采样DFT运算的流程控制，是运算的核心部分；其中输出sel[12..0]控制着输入的三个模块的输入时序；输出follow控制最后结果的输出；输出first是累加器模块14的控制信号，在新一轮累加循环开始时将上一次的累加结果清零，状态机12是核心组成部分，在本发明中状态机共有6303个状态。The state_m module 4 in the state machine 12 is composed of input clk, reset and output follow, first, sel[12..0], mainly responsible for the flow control of the entire frequency sampling DFT operation, which is the core part of the operation; wherein the output sel[12 ..0] controls the input timing of the three input modules; the output follow controls the output of the final result; the output first is the control signal of the accumulator module 14, and the previous accumulation result is cleared at the beginning of a new accumulation cycle , the state machine 12 is a core component, and the state machine has a total of 6303 states in the present invention.

纱条波谱分析计算单元为纱条波谱分析仪的核心部件，本发明的IP软核实现方案利用DFT频率采用方法，根据乌斯特公司对波谱频道的划分有选择的计算出波谱分析所关心的那部分频道的频谱，并将基于DFT频域采样的纱条波谱分析算法利用HDL语言移植到可执行并行运算的FPAG器件硬件8上，设计出可独立完成纱条波谱分析工作的IP软核；与传统纱条波谱分析方法相比，本发明方法占用的硬件资源大大减少，实时分析计算能力得到显著提升，本发明的核心部件纱条波谱分析计算单元，只需要将IP软核配置到选择的FPAG硬件器件8上即可，很大程度简化了设计难度，降低了开发时间与成本。The sliver spectrum analysis calculation unit is the core component of the sliver spectrum analyzer. The IP soft-core implementation scheme of the present invention uses the DFT frequency adoption method to selectively calculate the spectrum analysis concerned according to the division of spectrum channels by Uster. The frequency spectrum of that part of the channel, and the sliver spectrum analysis algorithm based on DFT frequency domain sampling is transplanted to the FPAG device hardware 8 that can perform parallel operations using HDL language, and an IP soft core that can independently complete the sliver spectrum analysis work is designed; Compared with the traditional sliver spectrum analysis method, the hardware resource occupied by the method of the present invention is greatly reduced, and the real-time analysis and calculation ability is significantly improved. The core component of the present invention is the sliver spectrum analysis calculation unit, which only needs to configure the IP soft core to the selected 8 on the FPAG hardware device, which greatly simplifies the design difficulty and reduces the development time and cost.

纱条信号波谱图是由纱条信号频谱图经过一定的处理而得来的，所以在实际中研究纱条信号的波谱图时应首先计算纱条信号的频谱，然后再根据相应的公式将频谱图转换为波谱图显示即可。具体来讲，波谱分析得到的波谱图是由55个频道内有效频点所对应的幅值组成，55个频道包含了175个有效频点，每个有效频点的计算过程均相同。IP软核与FPGA器件硬件8结合，可对传感器输出的纱条模拟信号在A/D采样之后，完成对纱条信号的傅里叶变换与频谱分析计算，以柱状波谱图形式输出。The spectrogram of the yarn signal is obtained by certain processing of the spectrum diagram of the yarn signal, so when studying the spectrum diagram of the yarn signal in practice, the spectrum of the yarn signal should be calculated first, and then the spectrum should be calculated according to the corresponding formula The graph can be converted to a spectrogram for display. Specifically, the spectrogram obtained by spectrum analysis is composed of the amplitudes corresponding to the effective frequency points in 55 channels. The 55 channels contain 175 effective frequency points, and the calculation process of each effective frequency point is the same. The combination of IP soft core and FPGA device hardware 8 can complete the Fourier transform and spectrum analysis and calculation of the sliver signal after the A/D sampling of the sliver analog signal output by the sensor, and output it in the form of a histogram.

本发明采用DFT频率采样新算法代替传统波谱分析方式实现对纱条波谱的分析计算，基于DFT频率采样的新算法与滤波法及全频段频率分析方法相比，对纱条信号进行波谱分析时只计算所关心频段内频点的幅值，并对其进行一定的处理，最终得到与乌斯特仪波谱图一致的波谱图。因此，该方法降低了波谱分析的复杂度，减少了运算量，提高了分析运算的实时性。The present invention uses a new DFT frequency sampling algorithm to replace the traditional spectrum analysis method to realize the analysis and calculation of the sliver spectrum. Compared with the filtering method and the full-band frequency analysis method, the new algorithm based on DFT frequency sampling only needs to analyze the spectrum of the yarn signal. Calculate the amplitude of the frequency points in the frequency band of interest, and perform certain processing on it, and finally get the spectrogram consistent with the spectrogram of the Uster instrument. Therefore, this method reduces the complexity of spectral analysis, reduces the amount of calculation, and improves the real-time performance of analysis and calculation.

在基于DFT频率采样的新算法中，采用非等间距采样方式。选择性的抽取每个频道内某些特定频点进行DFT计算，不对两个有效频段之间的保护频带内的任何频点计算DFT，同时由于每个频道带宽大小不一，因此频域采样点数也不一样，带宽较窄的低频道频率采样点数较少，带宽较宽的高频道频率采样点数较多，但是每个频道都选择最大的几个DFT值做平均后输出。这样的不规则非等间距采样方式大大减少了采样点个数，算法计算量大为降低，同时也防止了采样点过少而引起的频率输出值畸变，使得采用频率采样法输出的纱条信号波谱与传统波谱分析方法的输出结果基本一致。In the new algorithm based on DFT frequency sampling, non-equidistant sampling method is adopted. Selectively extract some specific frequency points in each channel for DFT calculation, and do not calculate DFT for any frequency point in the guard band between two effective frequency bands. At the same time, because the bandwidth of each channel is different, the number of frequency domain sampling points It is also different, the low frequency channel with narrow bandwidth has fewer sampling points, and the high frequency channel with wider bandwidth has more sampling points, but each channel selects the largest several DFT values for output after averaging. Such an irregular non-equidistant sampling method greatly reduces the number of sampling points, greatly reduces the amount of calculation of the algorithm, and also prevents the distortion of the frequency output value caused by too few sampling points, so that the sliver signal output by the frequency sampling method The output results of the spectrum are basically consistent with those of the traditional spectrum analysis method.

通过HDL硬件描述语言将DFT频域采样的纱条波谱分析新算法封装为能独立完成纱条信号波谱分析的IP软核。通过HDL硬件描述语言将DFT频域采样的纱条波谱分析新算法移植到FPGA器件硬件8上，形成可独立完成纱条信号波谱分析的IP软核。与纱条波谱分析的DSP器件硬件平台方案比本发明方案具有：通用性强、可移植性好、采用并行计算实时性高等优势。Through the HDL hardware description language, the new algorithm of sliver spectrum analysis of DFT frequency domain sampling is packaged into an IP soft core that can independently complete the spectrum analysis of sliver signals. Through the HDL hardware description language, the new algorithm of sliver spectrum analysis of DFT frequency domain sampling is transplanted to the FPGA device hardware 8, forming an IP soft core that can independently complete the spectrum analysis of sliver signals. Compared with the solution of the present invention, the DSP device hardware platform solution for sliver spectral analysis has the advantages of strong versatility, good portability, and high real-time performance by using parallel computing.

Claims

1. The sliver spectrum analysis IP soft core based on DFT frequency sampling is characterized in that it includes a sliver spectrum analysis calculation unit, and the sliver spectrum analysis calculation unit includes FPGA device hardware (8), and the FPGA device hardware (8) Using HDL language, the sliver spectrum analysis algorithm based on DFT frequency sampling is packaged into a 55-channel sliver spectrum analysis IP soft core (9). The 55-channel sliver spectrum analysis IP soft core (9) includes different center frequencies and different bandwidths. 55 channels, each channel includes a set of IP sub-core (10) based on DFT frequency sampling, IP sub-core (10) includes an input module (11), a state machine (12), two multipliers (13 ), two accumulator modules (14) and an output module (15), the input module (11) includes xvalues module (1), real part constant coefficient avalues module (2), imaginary part constant coefficient bvalues module (3), The state machine (12) is provided with a state_m module (4), the multiplier (13) is provided with a mult module (5), and the accumulator module (14) includes a real part accumulation accax module (6) and an imaginary part accumulation accbx module (7),

The input module (11) is connected to the state machine (12) through wires, and the state machine (12) is respectively connected to the xvalues module (1), real part constant coefficient avalues module (2), and imaginary part constant coefficient bvalues module (3) through wires , the real part constant coefficient avalues module (2) is sequentially connected to the mult module (5) in a multiplier 13, the real part accumulation accax module (6), and a flip-flop DFFE through wires, and the imaginary part constant coefficient bvalues module (3) The mult module (5), imaginary part accumulation accbx module (7) and another trigger DFFE in another multiplier (13) are connected in sequence through wires, and the xvalues module (1) is connected with two multipliers (13) through wires Connect separately.

2. the detection method of the sliver spectrum analysis IP soft core based on DFT frequency sampling, it is characterized in that, based on the sliver spectrum analysis IP soft core of claim 1, specifically implement according to the following steps:

Step 1, get the digital sliver signal:

In the sliver spectrum analysis IP soft core,

1) First, the analog sliver signal obtained by the sliver uniformity detection sensor is converted by the A/D converter, and the analog sliver signal is converted into a digital sliver signal;

2) Send the digital sliver signal to the input module (11), and the xvalues module (1) in the input module (11) directly stores the input digital sliver signal, that is, the sampling point value, into the internal memory of the FPGA device hardware (8) middle;

Step 2, digital sliver signal undergoes DFT transformation:

Carry out DFT transformation to the digital sliver signal obtained in step 1

1) It takes 6300 sampling values to perform a DFT operation. The xvalues module (1) directly stores the sampling values in the memory inside the FPGA device hardware (8). The xvalues module (1) in the input module (11), the real Partial constant coefficient avalues module (2) and imaginary part constant coefficient bvalues module (3) enter different branches according to the input value of sel[12..0], and output different storage values;

2) Perform DFT transformation on the digital yarn signal according to the DFT transformation formula,

The DFT transformation formula is:

X x ((k k)) = = DFT DFT [[x x ((n no))]] = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) {e e}^{- - j j \frac{22 π π}{P P} kn k n} = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) ((cos cos \frac{22 π π}{P P} kn k n - - j j sin sin \frac{22 π π}{P P} kn k n))

In the DFT transformation formula, the corresponding relationship between effective frequency points and k in the frequency domain is:

make

a_{k} (no) = \cos \frac{2 π}{P} k n,

b_{k} (no) = \sin \frac{2 π}{P} k n,

Then the DFT transformation formula can be written as:

X x ((k k)) = = DFT DFT [[x x ((n no))]] = = {Σ Σ}_{n no = = 00}^{L L - - 11} x x ((n no)) \times \times [[{a a}_{k k} ((n no)) - - j j {b b}_{k k} ((n no))]]

When the k value is fixed, a _k (n) and b _k (n) are a set of values about n, and the value range of n is [0, L-1], a _k (n) and b _k (n) are L constants corresponding to 0≤n≤L-1, a _k (n) and b _k (n) are calculated and stored in the external memory in advance, when the digital yarn signal is input, a _k (n) and the values of b _k (n) are read into the FPGA device hardware (8) to participate in the operation;

The DFT operation is mainly a multiplication-accumulation operation, and only a state machine (12) is added on the basis of the multiplication-accumulation to control the timing of the multiplication-accumulation; the multiplier (13) is provided with a mult module (5), and the input multiplier and The multiplicand corresponds to the 14-bit input signal value, the 14-bit constant coefficient value of the real part constant coefficient avalues module (6) and the imaginary part constant coefficient bvalues module (7), and the output result is represented by 28-bit two’s complement; Device block (14) comprises real part accumulating accax module (6) and imaginary part accumulating accbx module (7), and the calculation of real part accumulating accax module (6) and imaginary part accumulating accbx module (7) is identical; Real part accumulating accax module (6) The output value of the input clock signal clk, output trigger signal first_d, mult module (5) is also the input value ax[27..0] of the accumulator module (14) and the real part of the accumulator module (14) The accumulative result value is composed of accax[36..0], and the real part accumulative accax module (6) performs the cumulative operation of multiplying the input signal value and the real part coefficient a _k ; performs the real part sum of the DFT operation on the 6300 input sample values The results of the imaginary part calculation are accumulated and output, and finally the real part A _k and the imaginary part B _k of the DFT of 6300 sampled values are obtained;

At the beginning of a new accumulation cycle, the previous accumulation result is cleared. The state machine (12) has 6303 states in total, corresponding to 6302 sel signals and an idle state. The idle state is the idle state and the default state, and the state machine ( 12) Continuously cycle between state 1 and state 6302, and at the same time output a new sel value to xvalues module (1), real part constant coefficient avalues module (2), imaginary part constant coefficient bvalues module (3), Since the input signal and the constant coefficient have one-to-one correspondence with the sel signal, each time the state machine 12 outputs a sel signal value, the real part constant coefficient avalues module (2) and the imaginary part constant coefficient bvalues module (3) will output a corresponding value, and sent to the multiplier (13), so that the corresponding input signal value is multiplied by the constant coefficient, and finally the product result is sent to the accumulator module (14), and the state machine (12) will start and End, respectively set the first signal and the follow signal to 1, when the first signal is 1, the accumulator module (14) will clear the result of the previous cycle, and start a new round of cumulative calculation; when the follow signal is 1 , the trigger DEEF starts to output, so as to achieve the purpose of controlling the output;

Step 3, calculate the amplitude M _k concerned by the spectrum analysis:

According to the real part A _k and imaginary part B _k of DFT calculated in step 2, carry out the root mean square calculation, the formula is as follows, and calculate the amplitude M _k concerned by the spectral analysis;

The calculation formula of the amplitude _Mk concerned by spectrum analysis is as follows:

{M m}_{k k} = = \sqrt[22]{{A A}_{k k}^{22} + + {B B}_{k k}^{22}};;

According to the 6300 sampling values of the spectrum analysis IP soft core, the amplitude M _k of 175 frequency points is calculated;

Step 4, obtain the full-band spectrum of the sliver signal:

For every 6300 sampling values of the IP soft core of the spectrum analysis, the amplitude M _k of 175 frequency points is calculated, and in the 55 channels of the full frequency band of the yarn spectrum analysis, each channel contains one or more frequency points The amplitude M _k of the frequency band is wider, the more the number of frequency points in the channel, the final output spectrum of each channel in the 55 channels is the mean value of the amplitude M _k of all frequency points in each channel, and the spectrum of the 55 channels The combination is the full-band sliver signal spectrum.

3. the detection method of the sliver spectrum analysis IP soft core based on DFT frequency sampling according to claim 3, is characterized in that, described input signal x (n), real part constant coefficient a _k , imaginary part constant coefficient Both b _k are represented by 14-bit binary code, while the multiplication-accumulation results A _k and B _k are represented by 37-bit two’s complement code, the time-domain sampling frequency fs is 1KHz, the number of segmented sampling points L is 6300, and the number of calculation points of segmented DFT P is set to 256000, and uneven sampling is performed in the frequency domain, and only the DFT values of 175 frequency points need to be calculated.