CN102810558A - Thin film transistor, array substrate and preparation methods of thin film transistor and array substrate, and liquid crystal display - Google Patents
Thin film transistor, array substrate and preparation methods of thin film transistor and array substrate, and liquid crystal display Download PDFInfo
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- CN102810558A CN102810558A CN201210279838XA CN201210279838A CN102810558A CN 102810558 A CN102810558 A CN 102810558A CN 201210279838X A CN201210279838X A CN 201210279838XA CN 201210279838 A CN201210279838 A CN 201210279838A CN 102810558 A CN102810558 A CN 102810558A
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Abstract
The embodiment of the invention provides a thin film transistor, an array substrate and preparation methods of the thin film transistor and the array substrate, and a liquid crystal display, and relates to the field of manufacture of a liquid crystal panel. The thickness of the thin film transistor can be reduced. The thin film transistor comprises a substrate, and a gate insulating layer for covering a gate; the gate is formed on the substrate; a semiconductor active layer, a pixel electrode layer, a source and a drain are formed on the gate insulating layer; the pixel electrode layer is below the source and the drain and contacts the source and the drain; the source and a laminating layer of the pixel electrode layer below the source, the drain and the laminating layer of the pixel electrode layer below the drain are on the same layer of the semiconductor active layer; the source and the laminating layer of the pixel electrode layer below the source, the drain and the laminating layer of the pixel electrode layer below the drain are cut off by the semiconductor active layer, and passivation layers are formed on the source, the drain, the pixel electrode layer and the semiconductor active layer. The embodiment of the invention is used for manufacturing the liquid crystal display.
Description
Technical field
The present invention relates to field of liquid crystal display, relate in particular to a kind of thin-film transistor, array base palte and preparation method thereof and LCD.
Background technology
In flat panel display; TFT-LCD (Thin Film Transistor-Liquid Crystal Display; Thin Film Transistor-LCD) has characteristics low in energy consumption, that manufacturing cost is relatively low and radiationless, therefore occupied leading position in flat panel display market.TFT-LCD is become box-like with color membrane substrates by TFT (thin-film transistor) array base palte.
Present non-crystalline silicon tft array base palte 5-Mask (5-mask) technology of main flow, technology all comprises deposition, exposure, development, etching, peels off etc. each time.Be patterned at through each time and form grid line, gate insulation layer, semiconductor active layer, data wire and source, drain electrode, passivation layer and pixel electrode layer on the substrate successively.
In present tft array substrate, because TFT is the longitudinal layer stack structure mostly, so box is thick, has reduced liquid crystal response speed.
Summary of the invention
Embodiments of the invention provide a kind of thin-film transistor, array base palte and preparation method thereof and LCD, have reduced the thickness of thin film field-effect pipe.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, a kind of thin-film transistor is provided, has comprised:
Substrate;
On said substrate, be formed with grid;
Cover the gate insulation layer of said grid;
On said gate insulation layer, be formed with semiconductor active layer, pixel electrode layer, source electrode and drain electrode; Wherein, said pixel electrode layer is positioned at said source electrode and drain electrode below, contacts with said source electrode and drain electrode; And the lamination of the pixel electrode layer of said source electrode and below thereof, drain electrode and and the lamination of the pixel electrode layer of below be positioned at same one deck of said semiconductor active layer; The lamination of the pixel electrode layer of the lamination of the pixel electrode layer of said source electrode and below thereof, said drain electrode and below thereof is broken off by said semiconductor active layer;
On said source electrode, drain electrode, pixel electrode layer and semiconductor active layer, be formed with passivation layer.
The thickness of the lamination of the pixel electrode layer of the thickness of the lamination of the pixel electrode layer of said source electrode and below thereof, said drain electrode and below thereof is identical with the thickness of said semiconductor active layer.
On the one hand, a kind of array base palte is provided, comprises the grid line, data wire and the storage capacitance hearth electrode that intersect in length and breadth, said grid line and data wire surround pixel cell, and said pixel cell comprises above-mentioned thin-film transistor.
Overlapping place between said storage capacitance hearth electrode and said data wire is formed with the dottle pin semiconductor layer;
And/or the overlapping place between said grid line and said data wire is formed with the dottle pin semiconductor layer.
Also comprise: be positioned at said pixel cell edge and said storage capacitance hearth electrode and said grid line shield bars with layer.
Said data wire below is formed with said pixel electrode layer.
On the one hand, a kind of LCD is provided, comprises above-mentioned arbitrary array base palte.
On the one hand, a kind of manufacture method of thin-film transistor is provided, comprises:
On substrate, form the layer of metal film and form grid through composition technology;
On said substrate, form gate insulation layer;
Form active layer on the said gate insulation layer and obtaining being positioned at the semiconductor active layer above the said grid through the composition PROCESS FOR TREATMENT;
On said substrate, successively form one deck pixel electrode layer and layer of metal film;
Form source electrode and drain electrode and remove the said pixel electrode layer and the metallic film of said semiconductor active layer top through a composition technology;
On the said whole base plate that obtains with this, form passivation layer.
On the one hand, a kind of manufacture method of array base palte is provided, comprises:
On substrate, form the layer of metal film, form grid line, grid, storage capacitance hearth electrode through composition technology;
On said substrate, form gate insulation layer;
Form active layer on the said gate insulation layer and obtaining being positioned at the semiconductor active layer above the said grid through the composition PROCESS FOR TREATMENT;
On said substrate, successively form one deck pixel electrode layer and layer of metal film;
Obtain data wire, source electrode, drain electrode and pixel electrode and remove the said pixel electrode layer and the metallic film of said semiconductor active layer top through the composition PROCESS FOR TREATMENT;
On the said whole base plate that obtains with this, form passivation layer.
Form shield bars simultaneously through forming said grid line, grid, storage capacitance hearth electrode composition technology.
The composition technology of the semiconductor active layer through forming said grid top forms the dottle pin semiconductor layer at the overlapping place between said storage capacitance hearth electrode and said data wire simultaneously, and/or the dottle pin semiconductor layer at the overlapping place between said grid line and said data wire.
Thin-film transistor provided by the invention, array base palte and manufacturing approach thereof and LCD; Wherein the source electrode of thin-film transistor, drain electrode are positioned on the pixel electrode layer; And broken off by semiconductor active layer; Source electrode, drain electrode with and following pixel electrode layer and semiconductor active layer be positioned at layer, and thickness is identical; Like this, compare the thin-film transistor of stepped construction in the prior art, the thin-film transistor that the embodiment of the invention provides is thinner, therefore adopt the array base palte of this thin-film transistor thinner, and then the panel box of making is thick thinner, thereby has improved liquid crystal response speed.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously; Accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, can also obtain other accompanying drawing according to these accompanying drawings.
The thin-film transistor structure sketch map that Fig. 1 provides for the embodiment of the invention;
The thin-film transistor manufacture method schematic flow sheet that Fig. 2 provides for the embodiment of the invention;
Fig. 3 is the structural representation one in the thin-film transistor manufacturing process of making the embodiment of the invention and providing;
Fig. 4 is the structural representation two in the thin-film transistor manufacturing process of making the embodiment of the invention and providing;
Fig. 5 is the structural representation three in the thin-film transistor manufacturing process of making the embodiment of the invention and providing;
Fig. 6 is the structural representation four in the thin-film transistor manufacturing process of making the embodiment of the invention and providing;
Fig. 7 is the structural representation five in the thin-film transistor manufacturing process of making the embodiment of the invention and providing;
The film transistor array base plate structure sketch map that Fig. 8 provides for the embodiment of the invention;
Fig. 9 is that the AA of Fig. 8 is to sectional view;
The manufacture method of a kind of array base palte that Figure 10 provides for embodiments of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.
Embodiments of the invention provide a kind of thin-film transistor, and are as shown in Figure 1, comprising: substrate 201; On substrate 201, be formed with grid 202; The gate insulation layer 203 of cover gate 202; On gate insulation layer 203, be formed with semiconductor active layer 207, pixel electrode layer 204, source electrode 208 and drain 206; Wherein, pixel electrode layer 204 is positioned at source electrode 208 and drain electrode 206 belows, contacts with source electrode 208 and drain electrode 206; And the lamination of the pixel electrode layer 204 of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is positioned at same one deck of semiconductor active layer 207; The lamination of the pixel electrode layer 204 of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is broken off by semiconductor active layer 207; On source electrode 208, drain electrode 206, pixel electrode layer 204 and semiconductor active layer 207, be formed with passivation layer 209.
Preferably, the thickness of the lamination of the pixel electrode layer 204 of the thickness of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is identical with the thickness of semiconductor active layer 207.
The source electrode of thin-film transistor provided by the invention, drain electrode are positioned on the pixel electrode layer, and are broken off by semiconductor active layer, source electrode, drain electrode with and pixel electrode layer down and semiconductor active layer be positioned at layer, and thickness is identical; Like this, compare the thin-film transistor of stepped construction in the prior art, the thin-film transistor that the embodiment of the invention provides is thinner, therefore adopt the array base palte of this thin-film transistor thinner, and then the panel box of making is thick thinner, thereby has improved liquid crystal response speed.
Embodiments of the invention also provide a kind of method of manufacturing thin film transistor, shown in Fig. 2～7, may further comprise the steps:
S101, as shown in Figure 3 forms the layer of metal film on substrate 201, form grid 202 through the composition PROCESS FOR TREATMENT.
Can use magnetically controlled sputter method, preparation one layer thickness is at
metallic film to
on substrate.The metal material of making metallic film can adopt molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper etc. usually, also can use the combining structure of above-mentioned different materials film.Then, with mask through exposure, development, etching, PROCESS FOR TREATMENT such as peel off, on certain zone of substrate, form grid 202; Wherein, grid 202 film forming are that the film build method of metallic film specifically can be plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method.
S102, as shown in Figure 4 forms gate insulator 203 on substrate 201.
You can then use chemical vapor deposition method continuously deposited on a substrate thickness of
to
thin gate insulation layer; material of the gate insulating layer is typically silicon nitride, silicon oxide can also be used such as silicon oxide, silicon and nitrogen, forming a gate insulating layer method can be used deposition method, spin coating or roll coating method.
S103, as shown in Figure 5 is forming active layer and is obtaining being positioned at the semiconductor active layer 207 above the grid 202 through the composition PROCESS FOR TREATMENT on the gate insulator 203.
Can on gate insulation layer, utilize amorphous silicon membrane and the n+ amorphous silicon membrane of chemical vapor deposition method deposit thickness for
to
, also can be depositing metal oxide semiconductive thin film on the gate insulation layer film; Mask with active layer makes public to amorphous silicon membrane, afterwards this amorphous silicon membrane is carried out dry etching, above grid, forms active layer.In addition; If the depositing metal oxide semiconductive thin film is as active layer on the gate insulation layer film; Then metal-oxide film is carried out a composition technology and can form active layer; Promptly after photoresist applies, with common mask to substrate make public, development, etching formation semiconductor active layer get final product.
S104, as shown in Figure 6 successively forms one deck pixel electrode layer 30 and layer of metal film 40 on substrate.
S105, as shown in Figure 7 forms source electrode 208, drain electrode 206 simultaneously through composition technology, gets rid of the pixel electrode layer 30 and metallic film 40 of semiconductor active layer 207 tops.Make the lamination of lamination, drain electrode 206 and the pixel electrode layer 204 of below thereof of pixel electrode layer 204 of source electrode 208 and below thereof broken off by semiconductor active layer 207.
At this moment; The lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 with and under the lamination of pixel electrode layer 204 be positioned at same one deck of semiconductor active layer 207; Preferably, the thickness of the lamination of the pixel electrode layer 204 of the thickness of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is identical with the thickness of semiconductor active layer 207.
Can adopt and the similar technology of manufacturing grid, priority deposit transparent pixel electrode layer and 30 layer of metal films 40 on substrate are removed the pixel electrode layer 30 and metallic film 40 of semiconductor active layer 207 tops through etching.
S106, on whole base plate 201, form passivation layer 209, as shown in Figure 1.
On the figure in established source electrode, drain electrode, semiconductor active layer zone, adopt chemical vapour deposition (CVD) (PECVD) or other film build methods, deposit thickness does
Protective layer, protective layer can be selected oxide, nitride or oxynitrides for use, corresponding reacting gas can be SiH
4, NH
3, N
2Mist or SiH
2Cl
2, NH
3, N
2Mist.
Method for fabricating thin film transistor provided by the invention makes source electrode, drain electrode be positioned on the pixel electrode layer, and is broken off by semiconductor active layer, source electrode, drain electrode with and pixel electrode layer down and semiconductor active layer be positioned at layer, and thickness is identical; Like this; Compare the thin-film transistor of stepped construction in the prior art; The thin-film transistor that the method for fabricating thin film transistor that adopts the embodiment of the invention to provide is made is thinner; Therefore adopt the array base palte of this thin-film transistor thinner, and then the panel box of making is thick thinner, thereby has improved liquid crystal response speed.
Shown in Fig. 8 and 9, the array base palte that the embodiment of the invention provided is described.This array base palte comprises grid line 11, data wire 14 and the storage capacitance hearth electrode 13 that intersects in length and breadth, and grid line 11 surrounds pixel cell with data wire 14, and pixel cell comprises the TFT that the foregoing description provides.This concrete array base palte comprises: substrate 201; On substrate 201, be formed with grid line 11, grid 202 and storage capacitance hearth electrode 13; On grid line 11, grid 202, storage capacitance hearth electrode 13 and substrate 201, be formed with gate insulation layer 203; On gate insulation layer 203, be formed with semiconductor active layer 207, pixel electrode layer 204 and data wire 14, source electrode 208, drain electrode 206.
Preferably, this array base palte can also comprise the shield bars 12 that is positioned at pixel cell edge and storage capacitance hearth electrode and the same layer of grid line, in case the optical crosstalk phenomenon between leak-stopping light and adjacent pixel unit takes place.
In the present embodiment, as shown in Figure 9, pixel electrode layer 204 is arranged in data wire (Fig. 9 does not represent), source electrode 208, drain electrode 206 belows, contacts with data wire, source electrode 208, drain electrode 206.In TFT regions; The pixel electrode layer 204 of source electrode 208, drain electrode 206 and below thereof is positioned at same one deck of semiconductor active layer 207; Preferably; The thickness of the lamination of the pixel electrode layer 204 of the thickness of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is identical with the thickness of semiconductor active layer 207, and the lamination of the pixel electrode layer 204 of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 and below thereof is broken off by semiconductor active layer 207.
Array base palte provided by the invention; In the TFT regions of array base palte, source electrode, drain electrode are positioned on the pixel electrode layer, and are broken off by semiconductor active layer; Source electrode, drain electrode with and following pixel electrode layer and semiconductor active layer be positioned at layer, and thickness is identical.Like this, compare the thin-film transistor of stepped construction in the prior art, the thin-film transistor that the embodiment of the invention provides is thinner, so this thin-film transistor array base-plate is thinner, and then the panel box of making is thick thinner, thereby has improved liquid crystal response speed.
Further, as shown in Figure 8, in the present embodiment, when forming semiconductor active layer 207, can be formed with dottle pin semiconductor layer 2071 at the overlapping place between grid line 11 and the data wire 14; And/or the overlapping place between storage capacitance hearth electrode 13 and data wire 14 forms dottle pin semiconductor layer 2072.
So, increased the overlapping place of data wire and grid line, the floor height at the overlapping place of data wire and storage capacitance hearth electrode has been avoided the generation of the excessive liquid crystal rotation anomaly that causes of end difference between the metal line layer at overlapping place.Simultaneously, reduced between grid line and data wire electrostatic breakdown takes place, and the probability of fracture takes place in data wire.In addition, when fracture takes place the storage capacitance hearth electrode, can the storage capacitance hearth electrode be connected with pixel electrode, transmit common electrode signal, need simultaneously this pixel is become dim spot through pixel electrode with laser.Because the existence of active layer makes that connecting area strengthens, and has higher success rate.
The method of manufacturing thin film transistor the present invention who provides in conjunction with embodiments of the invention goes back the concrete manufacture method that present embodiment provides array base palte, with reference to shown in Figure 10, comprises following flow process:
S201, on substrate 201, form the layer of metal film, form grid line, grid 202, storage capacitance hearth electrode 13 through the composition PROCESS FOR TREATMENT.
Certainly, optional can also form shield bars 12 in this step.
S202, on substrate 201, form gate insulator 203.
S203, forming active layer above the gate insulator 203 and obtaining being positioned at the semiconductor active layer 207 above the grid 202 through the composition PROCESS FOR TREATMENT.
The optional dottle pin semiconductor layer 2072 that in this step, can also form the overlapping place between storage capacitance hearth electrode 13 and data wire 14 simultaneously, and/or the dottle pin semiconductor layer 2071 at the overlapping place between grid line 11 and data wire 14.
S204, on substrate, successively form one deck pixel electrode layer and 30 layer of metal films 40.
S205, obtain data wire, source electrode 208, drain electrode 206 and pixel electrode 204, simultaneously, get rid of the pixel electrode layer 30 and metallic film 40 of semiconductor active layer 207 tops through the composition PROCESS FOR TREATMENT.Make pixel electrode layer 204, drain electrode 206 and the pixel electrode layer 204 of below thereof of source electrode 208 and below thereof broken off by semiconductor active layer 207.
At this moment; Source electrode 208, the drain electrode 206 with and under pixel electrode layer 204 be positioned at semiconductor active layer 207 same one decks; Preferably, the thickness of the lamination of the pixel electrode layer 204 of source electrode 208 and below thereof, drain electrode 206 with and under the thickness of lamination of pixel electrode layer 204 identical with semiconductor active layer 207 thickness.
The pixel electrode that is used for controlling liquid crystal deflection like this in the pixel cell can form with the pixel electrode layer of thin-film transistor source electrode and drain electrode below and directly be electrically connected with drain electrode simultaneously, compares with the mode that is connected pixel electrode and drain electrode through via hole in the prior art and can reduce manufacture craft saving cost.
S206, on whole base plate 201, form passivation layer 209.
Wherein, the concrete making flow process in the above step can repeat no more with reference to the making flow process of thin-film transistor here.
The manufacturing approach of array base palte provided by the invention; In the TFT regions of array base palte, source electrode, drain electrode are positioned on the pixel electrode layer, and are broken off by semiconductor active layer; Source electrode, drain electrode with and following pixel electrode layer and semiconductor active layer be positioned at layer, and thickness is identical.Like this, compare the thin-film transistor of stepped construction in the prior art, the thin-film transistor that the embodiment of the invention provides is thinner, so this thin-film transistor array base-plate is thinner, and then the panel box of making is thick thinner, thereby has improved liquid crystal response speed.
LCD provided by the invention can be for adopting above-mentioned array base palte, and the structure of its substrate is identical with a last embodiment, repeats no more at this.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (11)
1. a thin-film transistor is characterized in that, comprising:
Substrate;
On said substrate, be formed with grid;
Cover the gate insulation layer of said grid;
On said gate insulation layer, be formed with semiconductor active layer, pixel electrode layer, source electrode and drain electrode; Wherein, said pixel electrode layer is positioned at said source electrode and drain electrode below, contacts with said source electrode and drain electrode; And the lamination of the pixel electrode layer of said source electrode and below thereof, drain electrode and and the lamination of the pixel electrode layer of below be positioned at same one deck of said semiconductor active layer; The lamination of the pixel electrode layer of the lamination of the pixel electrode layer of said source electrode and below thereof, said drain electrode and below thereof is broken off by said semiconductor active layer;
On said source electrode, drain electrode, pixel electrode layer and semiconductor active layer, be formed with passivation layer.
2. thin-film transistor according to claim 1 is characterized in that, the thickness of the lamination of the pixel electrode layer of the thickness of the lamination of the pixel electrode layer of said source electrode and below thereof, said drain electrode and below thereof is identical with the thickness of said semiconductor active layer.
3. an array base palte comprises the grid line, the data wire that intersect in length and breadth, and the storage capacitance hearth electrode, and said grid line and data wire surround pixel cell, it is characterized in that, said pixel cell comprises claim 1 or 2 described thin-film transistors.
4. array base palte according to claim 3 is characterized in that, the overlapping place between said storage capacitance hearth electrode and said data wire is formed with the dottle pin semiconductor layer;
And/or the overlapping place between said grid line and said data wire is formed with the dottle pin semiconductor layer.
5. array base palte according to claim 3 is characterized in that, also comprises: be positioned at said pixel cell edge with said storage capacitance hearth electrode and said grid line shield bars with layer.
6. array base palte according to claim 3 is characterized in that, said data wire below is formed with said pixel electrode layer.
7. a LCD is characterized in that, comprises the described arbitrary array base palte of claim 3～6.
8. the manufacture method of a thin-film transistor is characterized in that, comprising:
On substrate, form the layer of metal film and form grid through composition technology;
On said substrate, form gate insulation layer;
Form active layer on the said gate insulation layer and obtaining being positioned at the semiconductor active layer above the said grid through the composition PROCESS FOR TREATMENT;
On said substrate, successively form one deck pixel electrode layer and layer of metal film;
Form source electrode and drain electrode and remove the said pixel electrode layer and the metallic film of said semiconductor active layer top through a composition technology;
On the said whole base plate that obtains with this, form passivation layer.
9. the manufacture method of an array base palte is characterized in that, comprising:
On substrate, form the layer of metal film, form grid line, grid, storage capacitance hearth electrode through composition technology;
On said substrate, form gate insulation layer;
Form active layer on the said gate insulation layer and obtaining being positioned at the semiconductor active layer above the said grid through the composition PROCESS FOR TREATMENT;
On said substrate, successively form one deck pixel electrode layer and layer of metal film;
Obtain data wire, source electrode, drain electrode and pixel electrode and remove the said pixel electrode layer and the metallic film of said semiconductor active layer top through the composition PROCESS FOR TREATMENT;
On the said whole base plate that obtains with this, form passivation layer.
10. method according to claim 9 is characterized in that, also comprises:
Composition technology through forming said grid line, grid, storage capacitance hearth electrode forms shield bars simultaneously.
11. according to claim 9 or 10 described methods, it is characterized in that, also comprise:
The composition technology of the semiconductor active layer through forming said grid top forms the dottle pin semiconductor layer at the overlapping place between said storage capacitance hearth electrode and said data wire simultaneously, and/or the dottle pin semiconductor layer at the overlapping place between said grid line and said data wire.
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| WO2016045241A1 (en) * | 2014-09-25 | 2016-03-31 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN107579083A (en) * | 2017-09-30 | 2018-01-12 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| CN109585303A (en) * | 2018-11-23 | 2019-04-05 | 合肥鑫晟光电科技有限公司 | Display panel, array substrate, thin film transistor (TFT) and its manufacturing method |
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| CN109585303B (en) * | 2018-11-23 | 2023-03-10 | 合肥鑫晟光电科技有限公司 | Display panel, array substrate, thin film transistor and manufacturing method thereof |
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| CN102810558B (en) | 2014-10-15 |
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