CN102800700A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN102800700A CN102800700A CN2011101394416A CN201110139441A CN102800700A CN 102800700 A CN102800700 A CN 102800700A CN 2011101394416 A CN2011101394416 A CN 2011101394416A CN 201110139441 A CN201110139441 A CN 201110139441A CN 102800700 A CN102800700 A CN 102800700A
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Abstract
The invention provides a transistor comprising a semiconductor substrate, a grid electrode structure located on the surface of the semiconductor substrate, and ditch grooves located in the semiconductor substrates on the two sides of the grid electrode structure, wherein the ditch grooves comprise a first ditch groove located on the two sides of the grid electrode structure and in contact with the grid electrode structure, a second ditch groove located on the bottom part of the first ditch groove and in contact with the first ditch groove, and a third ditch groove located on the bottom part of the second ditch groove and in contact with the second ditch groove, and the second ditch groove protrudes towards one side of the grid electrode structure; and stress layers located in the ditch grooves. The stress of the ditch region of the transistor provided by the embodiment of the invention is increased, the migration rate of charge carriers is improved, and the performance of the transistor is reinforced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistor and forming method thereof.
Background technology
Develop rapidly along with semiconductor fabrication; Semiconductor device is in order to reach higher arithmetic speed, bigger memory data output and more function; Semiconductor device develops towards higher component density, higher integrated level direction; Therefore, (Complementary Metal Oxide Semiconductor, CMOS) transistorized grid becomes more and more thinner and length becomes shorter than in the past complementary metal oxide semiconductors (CMOS).In order to obtain electric property preferably, need improve performance of semiconductor device through the control carrier mobility usually.A key element of this technology is the stress in the oxide-semiconductor control transistors raceway groove.Such as suitable proof stress, improved charge carrier (electronics in the n-channel transistor, the hole in the p-channel transistor) mobility, just can improve drive current.Thereby stress can greatly improve transistorized performance.
The stress liner technology forms tensile stress laying (tensile stress liner) on nmos pass transistor; On the PMOS transistor, form compression laying (compressive stress liner); Thereby increased the drive current of PMOS transistor and nmos pass transistor, improved the response speed of circuit.Certificate research, the integrated circuit of the two stress liners technology of use can bring 24% speed lifting.
Because silicon, germanium have identical lattice structure; I.e. " diamond " structure, at room temperature, the lattice constant of germanium is greater than the lattice constant of silicon; So in the transistorized source of PMOS, the drain region forms SiGe (SiGe); Can introduce the compression that lattice mismatch forms between silicon and the germanium silicon, further improve compression, improve the transistorized performance of PMOS.Correspondingly, form carbon silicon (CSi) in source, the drain region of nmos pass transistor and can introduce the tension stress that lattice mismatch forms between silicon and the carbon silicon, further improve tension stress, improve the performance of nmos pass transistor.
In the prior art, transistorized formation method is:
Please refer to Fig. 1; Semiconductor substrate 100 is provided; In said Semiconductor substrate 100, form shallow channel isolation area 103; Formation is positioned at said Semiconductor substrate 100 surperficial gate insulation layers 105, form to cover the gate electrode layer 107 of said gate insulation layer 105, forms on said Semiconductor substrate 100 surfaces and the side wall 109 that is positioned at said gate insulation layer 105, gate electrode layer 107 both sides and is in contact with it;
Please refer to Fig. 2, is that mask forms opening 111 in said Semiconductor substrate 100 with said side wall 109;
Please refer to Fig. 3, in said opening 111, fill full SiGe, formation source/drain region 113.
Prior art is limited at the stress of the method formation of transistorized source and drain areas formation germanium silicon then, and the raising of mobility of charge carrier rate is less, and transistorized performance improves limited.
Much more more see that about transistor and forming method thereof publication number is the application documents of " CN101789447A ".
Summary of the invention
The problem that the present invention solves is transistor that improves the mobility of charge carrier rate and forming method thereof.
For addressing the above problem, embodiments of the invention provide a kind of transistor, comprising:
Semiconductor substrate;
Be positioned at the grid structure of said semiconductor substrate surface;
Be positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprises the 3rd groove that is positioned at said grid structure both sides and first groove that contacts with said grid structure, the bottom that is positioned at said first groove and second groove that contacts with first groove, is positioned at said second channel bottom and contacts with said second groove; Wherein, said second groove side-prominent to said grid structure;
Be positioned at the stressor layers of said groove.
Alternatively, said second groove is to a side-prominent 10nm～40nm of said grid structure, and the degree of depth of said the 3rd groove is 30nm～100nm.
Alternatively, the material of said strained layer is a SiGe, comprises 20%～35% germanium atom in the said SiGe.
Alternatively, the crystal orientation of said Semiconductor substrate is < 110>or < 100 >.
Alternatively, said grid structure comprises the gate dielectric layer that is positioned at said semiconductor substrate surface, the gate electrode layer that is positioned at said gate dielectric layer surface, and the side wall that is positioned at the semiconductor substrate surface of said gate dielectric layer and gate electrode layer both sides.
A kind of transistorized formation method also is provided in the embodiments of the invention, has comprised:
Semiconductor substrate is provided;
Formation is positioned at said semiconductor substrate surface grid structure;
Formation is positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprises the 3rd groove that is positioned at said grid structure both sides and first groove that contacts with said grid structure, the bottom that is positioned at said first groove and second groove that contacts with first groove, is positioned at said second channel bottom and contacts with said second groove; Wherein, said second groove side-prominent to said grid structure;
Formation is positioned at the stressor layers of said groove.
Alternatively, the formation step of said groove is: form the hard mask layer that covers said Semiconductor substrate and grid structure, said hard mask layer has the opening that is positioned at the grid structure both sides; With said hard mask layer is that the said Semiconductor substrate of mask etching forms first groove; Etching first channel bottom and near the Semiconductor substrate of a side of said grid structure forms second groove; The Semiconductor substrate of said second channel bottom of etching forms the 3rd groove.
Alternatively, the formation technology of said first groove and the 3rd groove is dry etching; The formation technology of said second groove is wet etching.
Alternatively, the formation step of said stressor layers is: adopt epitaxial growth technology in groove, to form the monocrystalline silicon thin film that thickness is 3nm～10nm; In comprising the atmosphere of 20%～35% germanium atom, adopt epitaxial growth technology to form germanium-silicon film on the monocrystalline silicon thin film surface; Be under 800 ℃～1100 ℃ the process conditions in temperature, adopt cure or rapid thermal anneal process to said germanium-silicon film heating 10s～30min, form the stressor layers that flushes with said semiconductor substrate surface.
Alternatively, the formation step of said stressor layers is: adopting depositing operation in said groove, to form thickness is the polysilicon membrane of 3nm～10nm; Adopt depositing operation to form the stressor layers that flushes with said semiconductor substrate surface on said polysilicon membrane surface.
Compared with prior art, the present invention has the following advantages:
The transistor of the embodiment of the invention; In the Semiconductor substrate of said grid structure both sides, be formed with groove; Said groove comprises bottom that is positioned at said first groove and second groove that contacts with first groove; Said second groove is one side-prominent to said grid structure, and transistorized stress increases, and can improve the mobility of charge carrier rate; The groove of the embodiment of the invention also comprises the 3rd groove that is positioned at second channel bottom and contacts with said second groove; The degree of depth of said groove increases; The stressor layers of follow-up formation increases; Further increase transistorized stress, made transistorized channel region mobility of charge carrier rate further improve enhance transistor performance.
Description of drawings
Fig. 1～Fig. 3 is the process sketch map of cross-section structure of the transistorized formation method of prior art;
Fig. 4 is the schematic flow sheet of the transistorized formation method of the embodiment of the invention;
Fig. 5～Fig. 9 is the process sketch map of cross-section structure of the transistorized formation method of the embodiment of the invention.
Embodiment
Can know by background technology, existing transistorized formation method in the source, the drain region forms SiGe and improves the comparatively limited of mobility of charge carrier rate, cause transistorized drive current less, thereby make transistorized poor-performing.
The inventor of the embodiment of the invention finds, the transistorized formation method of prior art adopts the method for dry etching to form groove in the grid structure both sides, in said groove, fills the method existing problems that silicon germanium material forms stressor layers then.The inventor of the embodiment of the invention is through further research back discovery; The stress intensity in the transistor channel and the shape of groove are closely related; When said groove when grid structure one is side-prominent, said slot trough reduces from the length of channel region, in the stressor layers that forms in such cases; Stress in the transistor channel is bigger, helps improving the mobility of charge carrier rate.Further, the inventor of the embodiment of the invention finds, the degree of depth of groove also with transistor channel in stress intensity relevant, the degree of depth that can increase groove improves the stress in the transistor channel, thereby improves the mobility of charge carrier rate.
In order to make those skilled in the art better understand the present invention, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.
Need to prove; Transistor formation method provided by the present invention both can be used to form the PMOS transistor; Also can be used to form nmos pass transistor; In the technology that forms PMOS transistor and formation nmos pass transistor, difference is that the material of stressor layers is different, and is also different through the material of the formed protective layer of oxidation technology.In the present embodiment, be example exemplarily to form the PMOS transistor, the present invention is set forth.
The inventor of the embodiment of the invention provides a kind of transistorized formation method, please refer to Fig. 4, comprising:
Step S201 provides Semiconductor substrate;
Step S203, formation is positioned at said semiconductor substrate surface grid structure;
Step S205; Formation is positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprises first groove that contacts with said grid structure, the bottom that is positioned at said first groove and second groove that contacts with first groove, the 3rd groove that is positioned at said second channel bottom and contacts with said second groove; Wherein, said second groove side-prominent to said grid structure;
Step S207 forms the stressor layers that is positioned at said groove.
Execution in step S201 please refer to Fig. 5, and Semiconductor substrate 300 is provided.
The material of said Semiconductor substrate 300 is a monocrystalline silicon, is formed with fleet plough groove isolation structure 303 in the said Semiconductor substrate 300, is used for isolated transistor.
In an embodiment of the present invention, the crystal orientation of said Semiconductor substrate 300 is < 110>or < 100 >.
Need to prove that in other embodiments of the invention, said Semiconductor substrate 300 also can be other crystal orientation, for example < 101 >, < 001 >, < 010>etc.
Execution in step S203 please continue with reference to figure 5, forms to be positioned at said Semiconductor substrate 300 surface gate structure (not indicating).
Said grid structure comprises the gate dielectric layer 305 that is positioned at Semiconductor substrate 300 surface, is positioned at the gate electrode layer 307 on said gate dielectric layer 305 surfaces and is positioned at said gate dielectric layer 305 and the side wall 309 on gate electrode layer 307 both sides and Semiconductor substrate 300 surfaces that are in contact with it.
In an embodiment of the present invention, the formation step of said grid structure is: adopt depositing operation to form gate dielectric layer 305 on said Semiconductor substrate 300 surfaces; Adopt depositing operation to form gate electrode layer 307 on said gate dielectric layer 305 surfaces; Adopt deposition, etching technics to form side wall on Semiconductor substrate 300 surfaces of said gate dielectric layer 305 and gate electrode layer 307 both sides.
Wherein, the material of said gate dielectric layer is a silicon dioxide, and the material of said gate electrode layer is polysilicon or metal, and the material of said side wall is a silicon dioxide.
Execution in step S205; Please refer to Fig. 6～Fig. 8; Formation is positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprise be positioned at said grid structure both sides and first groove 311 that contacts with said grid structure, be positioned at the bottom of said first groove 311 and second groove 312 that contacts with first groove 311, the 3rd groove 313 that is positioned at said second groove, 312 bottoms and contacts with said second groove 312; Wherein, said second groove 312 side-prominent to said grid structure.
Please refer to Fig. 6, form first groove 311 that is positioned at said grid structure both sides and contacts with said grid structure.
The formation step of said first groove 311 is: form to cover said Semiconductor substrate 300, the top of grid structure and the hard mask layer (not shown) of both sides, said hard mask layer has the opening (not shown) that is positioned at the grid structure both sides; With said hard mask layer is that the said Semiconductor substrate 300 of mask etching forms first groove 311.
In an embodiment of the present invention, the formation technology of said first groove 311 is dry etching, said first groove, 311 dark 30～60nm.
Please refer to Fig. 7, form and to be positioned at the bottom of said first groove 311 and second groove 312 that contacts with first groove 311, said second groove 312 is one side-prominent to said grid structure.
For the stressor layers that makes follow-up formation has bigger stress to transistorized channel region; Can consider to make said second groove 312 side-prominent to said grid structure; Make said slot trough reduce from the length of channel region; Make stressor layers have bigger stress, thereby improve transistorized mobility of charge carrier rate transistorized channel region.
Consider if second groove 312 to side-prominent too many of grid structure one, second groove 312 that then can cause said grid structure both sides is at a distance of too near, the length of short channel is too for a short time to cause electric leakage; If second groove 312 is to side-prominent too little of grid structure one, then the transistorized stress of follow-up formation increase limited, be difficult to improve the mobility of charge carrier rate.Said second groove 312 is to grid structure one side-prominent 10nm～40nm, and especially in 16nm～26nm scope, the transistorized stress of follow-up formation is maximum, and the mobility of charge carrier rate is the highest.
The inventor of the embodiment of the invention finds through the research back; Adopt anisotropic dry etch process; The said Semiconductor substrate 300 of etching is continued in bottom at said first groove 311; Form comparatively difficulty of second groove 312, adopt isotropic wet-etching technology can well solve the problem of formation to one of said grid structure side-prominent second groove 312.In an embodiment of the present invention; Is example with the crystal orientation for the Semiconductor substrate 300 of < 110>or < 100 >; The formation technology of said second groove 312 is wet etching; Chemical reagent in the said wet etching is along the crystal orientation < 110>or the said Semiconductor substrate 300 of < 100>corrosion of monocrystalline silicon, and promptly fast along crystal orientation < 110>or < 100>corrosion rate of monocrystalline silicon, then corrosion rate is slower to be different from the crystal orientation < 110>of said monocrystalline silicon or other directions of < 100 >.Therefore, second groove 312 that adopts wet-etching technology to form is side-prominent to grid structure one.
Please refer to Fig. 8, form the 3rd groove 313 that is positioned at said second groove, 312 bottoms and contacts with said second groove 312.
Consider that only to make second groove 312 limited to the stress that a side-prominent transistor of grid structure increases; The inventor of the embodiment of the invention finds through the research back; Increase the degree of depth of groove, make and follow-uply can fill more SiGes and form strained layers, thereby make that transistorized stress is bigger; Increase the mobility of charge carrier rate, improve transistor performance.Therefore, after forming second groove 312, continue the Semiconductor substrate 300 of etching second groove 312 bottoms, form the 3rd groove 313.
In an embodiment of the present invention, the formation technology of said the 3rd groove 313 is dry etching, and the degree of depth of said the 3rd groove is 30nm～100nm.
After above-mentioned steps is accomplished, the completing of groove, said groove is used for follow-up filling SiGe and forms stressor layers.
Execution in step S207 please refer to Fig. 9, forms the stressor layers 315 that is positioned at said groove.
The material of said stressor layers 315 is a SiGe, is used to make the stress of transistor channel region to increase, and improves the mobility of charge carrier rate, enhance transistor performance.
In an embodiment of the present invention, the formation step of said stressor layers 315 is: adopting epitaxial growth technology in said groove, to form thickness is the monocrystalline silicon thin film of 3nm～10nm, is used to make that the stress distribution of transistor channel region of follow-up formation is more even; In comprising the atmosphere of 20%～35% germanium atom, adopt epitaxial growth technology to form germanium-silicon film on the monocrystalline silicon thin film surface; Be under 800 ℃～1100 ℃ the process conditions in temperature, adopt cure or rapid thermal anneal process to said germanium-silicon film heating 10s～30min, form the stressor layers 315 that flushes with said semiconductor substrate surface.
In another embodiment of the present invention, the formation step of said stressor layers 315 is: adopting depositing operation in said groove, to form thickness is the polysilicon membrane of 3nm～10nm, is used to make that the stress distribution of transistor channel region of follow-up formation is more even; Adopt depositing operation to form the stressor layers 315 that flushes with said semiconductor substrate surface on said polysilicon membrane surface.
Need to prove, in the PMOS transistor, all right doped with boron in the said strained layer 315, perhaps Doping Phosphorus in nmos pass transistor is used to reduce transistorized resistance.
Accordingly, the inventor of the embodiment of the invention also provides a kind of transistor, please combine to comprise with reference to figure 8 and Fig. 9:
Be positioned at the grid structure on said Semiconductor substrate 300 surfaces;
Be positioned at the groove of the said Semiconductor substrate 300 of said grid structure both sides; Said groove comprise be positioned at said grid structure both sides and first groove 311 that contacts with said grid structure, be positioned at the bottom of said first groove 311 and second groove 312 that contacts with first groove 311, the 3rd groove 313 that is positioned at said second groove, 312 bottoms and contacts with said second groove 312; Wherein, said second groove 312 side-prominent to said grid structure;
Be positioned at the stressor layers 315 of said groove.
Wherein, the crystal orientation of said Semiconductor substrate 300 is < 110>or < 100 >; Said grid structure comprises the gate dielectric layer 305 that is positioned at said semiconductor substrate surface, the gate electrode layer 307 that is positioned at said gate dielectric layer 305 surfaces, and the side wall 309 that is positioned at Semiconductor substrate 300 surfaces of said gate dielectric layer 305 and gate electrode layer 307 both sides; Said second groove 312 is to a side-prominent 10nm～40nm of said grid structure, and the degree of depth of said the 3rd groove 313 is 30nm～100nm; The material of said strained layer 315 is a SiGe, comprises 20%～35% germanium atom in the said SiGe.
To sum up; The transistor of the embodiment of the invention; In the Semiconductor substrate of said grid structure both sides, be formed with groove, said groove comprises bottom that is positioned at said first groove and second groove that contacts with first groove, and said second groove is one side-prominent to said grid structure; Transistorized stress increases, and can improve the mobility of charge carrier rate; The groove of the embodiment of the invention also comprises the 3rd groove that is positioned at second channel bottom and contacts with said second groove; The degree of depth of said groove increases; The stressor layers of follow-up formation increases; Further increase transistorized stress, made transistorized channel region mobility of charge carrier rate further improve enhance transistor performance.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. transistor comprises:
Semiconductor substrate;
Be positioned at the grid structure of said semiconductor substrate surface;
It is characterized in that, also comprise:
Be positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprises the 3rd groove that is positioned at said grid structure both sides and first groove that contacts with said grid structure, the bottom that is positioned at said first groove and second groove that contacts with first groove, is positioned at said second channel bottom and contacts with said second groove; Wherein, said second groove side-prominent to said grid structure;
Fill the stressor layers of said groove.
2. transistor as claimed in claim 1 is characterized in that, said second groove is to a side-prominent 10nm～40nm of said grid structure, and the degree of depth of said the 3rd groove is 30nm～100nm.
3. transistor as claimed in claim 1 is characterized in that, the material of said strained layer is a SiGe, comprises 20%～35% germanium atom in the said SiGe.
4. transistor as claimed in claim 1 is characterized in that, the crystal orientation of said Semiconductor substrate is < 110>or < 100 >.
5. transistor as claimed in claim 1; It is characterized in that; Said grid structure comprises the gate dielectric layer that is positioned at said semiconductor substrate surface, the gate electrode layer that is positioned at said gate dielectric layer surface, and the side wall that is positioned at the semiconductor substrate surface of said gate dielectric layer and gate electrode layer both sides.
6. transistorized formation method comprises:
Semiconductor substrate is provided;
Formation is positioned at said semiconductor substrate surface grid structure;
It is characterized in that, also comprise:
Formation is positioned at the groove of the said Semiconductor substrate of said grid structure both sides; Said groove comprises the 3rd groove that is positioned at said grid structure both sides and first groove that contacts with said grid structure, the bottom that is positioned at said first groove and second groove that contacts with first groove, is positioned at said second channel bottom and contacts with said second groove; Wherein, said second groove side-prominent to said grid structure;
Form the stressor layers of filling said groove.
7. transistorized formation method as claimed in claim 6 is characterized in that, the formation step of said groove is: form the hard mask layer that covers said Semiconductor substrate and grid structure, said hard mask layer has the opening that is positioned at the grid structure both sides; With said hard mask layer is that the said Semiconductor substrate of mask etching forms first groove; Etching first channel bottom and near the Semiconductor substrate of a side of said grid structure forms second groove; The Semiconductor substrate of said second channel bottom of etching forms the 3rd groove.
8. transistorized formation method as claimed in claim 7 is characterized in that the formation technology of said first groove and the 3rd groove is dry etching; The formation technology of said second groove is wet etching.
9. transistorized formation method as claimed in claim 6 is characterized in that, the formation step of said stressor layers is: adopting epitaxial growth technology in said groove, to form thickness is the monocrystalline silicon thin film of 3nm～10nm; In comprising the atmosphere of 20%～35% germanium atom, adopt epitaxial growth technology to form germanium-silicon film on the monocrystalline silicon thin film surface; Be under 800 ℃～1100 ℃ the process conditions in temperature, adopt cure or rapid thermal anneal process to said germanium-silicon film heating 10s～30min, form the stressor layers that flushes with said semiconductor substrate surface.
10. transistorized formation method as claimed in claim 6 is characterized in that, the formation step of said stressor layers is: adopting depositing operation in said groove, to form thickness is the polysilicon membrane of 3nm～10nm; Adopt depositing operation to form the stressor layers that flushes with said semiconductor substrate surface on said polysilicon membrane surface.
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| Publication number | Publication date |
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| CN102800700B (en) | 2015-04-29 |
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