CN102799131A - Ground penetrating radar lower computer control system based on field programmable gate array (FPGA) - Google Patents

Abstract

The FPGA-based ground penetrating radar lower computer control system of the present invention relates to the field of ground penetrating radar control. The system uses FPGA as the main control unit, cooperates with the transmitter pulse control unit, data sampling control unit, sampling data receiving unit and data communication unit to realize Control the functions of ultra-narrow pulse ground penetrating radar pulse transmission, data reception and transmission, etc. The FPGA first triggers the transmitter to emit a narrow pulse through the transmitter pulse control unit; then sends the sampling control signal through the data sampling control unit, and receives and stores the signal through the sampling data receiving unit; finally, after the ground penetrating radar completes a complete detection, The sampling data is sent to the host computer through the data communication unit for subsequent data processing. The ground penetrating radar system based on the invention can be used to detect the dielectric properties of underground media, soil water content, etc., and can be widely used in fields such as agriculture, geography and geological exploration.

Description

Control system of ground penetrating radar slave computer based on FPGA

technical field

The invention relates to the field of ground penetrating radar control, in particular to an FPGA-based ground penetrating radar lower computer control system.

Background technique

Ground Penetrating Radar (GPR) is a non-destructive detection instrument for detecting subsurface structures or buried objects. It utilizes the penetration ability of electromagnetic waves to the surface, emits a specific form of electromagnetic waves downward from the surface, and quantitatively measures the depth, For the structure and properties of the medium, on the basis of data processing, digital image restoration and reconstruction technology is applied to perform imaging processing on underground targets in order to achieve a true and intuitive reproduction of underground targets.

A typical shock pulse ground penetrating radar system consists of a host computer and a lower computer. The upper computer is responsible for data processing and radar imaging, and the lower computer is responsible for radar signal transmission and reception and data transmission. The lower computer system is composed of the main control unit, transmitter, receiver, data transmission unit and other parts. At present, most ground penetrating radars use processors such as CPU or MCU as the main control unit to complete the radar from transmitting pulses to data collection, transmission and other functions. Such as Chinese patent application CN99200610.4 (publication number CN2365679) discloses an integrated imaging ground penetrating radar, including a car, a transmitting antenna, a receiving antenna, a computer, a radar host, and a power supply, wherein the radar host consists of a transmitting source, a receiver, an amplifier , a signal processing and control circuit, a color display and an input and output socket, and is characterized in that it is also provided with a satellite positioning receiving device and a distance measuring wheel. The signal processing and control circuit in the radar host is composed of CPU board, hard disk, I/O board, A/D and D/A board, XY axis range selection board, VJA board, keyboard and keyboard decoder, etc. The machine uses the CPU in the computer as the core processor, and cooperates with the peripheral hardware to realize the detection function of the ground penetrating radar.

Chinese patent application CN201010195736.0 (publication number CN101872018A) discloses a wireless ground-penetrating radar system, including a wireless data acquisition subsystem and a ground-penetrating radar front-end subsystem. The GPR front-end subsystem includes batteries, power regulators, Ethernet controllers, ARM controllers, digital signal processors, analog-to-digital converters, digital controllers, timing systems, transmitters, transmitting antennas, receiving antennas and The receiver, that is, the lower computer of the ground penetrating radar, the ARM controller composed of MCU is used as the main control unit of the system to realize the coordination and control of the functions of various parts of the radar.

The existing ground penetrating radar lower computer system uses the processor as the main controller of the system, and controls the working process of the radar through software programs. The programming and debugging are simple and convenient, and the development cycle is short. The instruction or response interrupt will bring additional time overhead, it is difficult to achieve complete synchronization of timing and precise control of time.

Contents of the invention

In order to solve the problem that the existing technology cannot realize the precise control of the working sequence of the ground penetrating radar, the present invention proposes an FPGA-based ground penetrating radar slave computer control system, which uses the FPGA as the main control unit to control the transmitter, receiver and data The various parts of the communication work in coordination to ensure the synchronous operation of all parts of the radar system.

The technical solution adopted by the present invention to solve the technical problems is as follows:

FPGA-based ground penetrating radar lower computer control system, including data communication unit, FPGA main control unit, transmitter pulse control unit, data sampling control unit and sampling data receiving unit, the data communication unit communicates with the ground penetrating radar through the serial 485 bus The host computer communicates serially, and connects with the IO port of the FPGA main control unit in parallel; the FPGA main control unit is electrically connected with the transmitter pulse control unit, data sampling control unit, and sampling data receiving unit through the IO port, and the FPGA The main control unit completes the radar signal transmission and data collection by coordinating the working status of each unit; the transmitter pulse control unit is connected with the transmitter of the ground penetrating radar, which is responsible for buffering and transmitting the control signal of the transmission pulse to the transmitter. Control the transmitter circuit to generate high-power narrow pulses; the data sampling control unit is connected to the sampling circuit of the ground penetrating radar, which is responsible for generating sampling control signals with different delays, and controlling the sampling circuit to generate sampling pulses; the sampling data receiving unit is connected to the ground penetrating radar The preamplifier circuit of the receiver is connected, which is responsible for converting the analog signal into a digital signal and passing it to the FPGA main control unit.

The beneficial effects of the invention are: the system uses FPGA as the main control unit, has strong parallel computing capability, and can realize precise control of radar working sequence; the system has simple structure, is easy to realize, and has low cost. The system can be used to detect the dielectric properties of underground media, soil moisture content, etc., and can be widely used in agriculture, geography and geological exploration and other fields.

Description of drawings

Fig. 1 is the overall structural block diagram of the ground penetrating radar control system based on FPGA of the present invention;

In the figure: 1. Host computer, 2. Data communication unit, 3. FPGA main control unit, 4. Transmitter pulse control unit, 5. Data acquisition control unit, 6. Sampling data receiving unit, 7. Slow ramp generation circuit , 8. Sampling signal generation circuit, 9. Fast ramp wave generation circuit, 10. Transmitter, 11. Sampling circuit, 12. Preamplification circuit;

Fig. 2 is FPGA I/O pin configuration circuit principle diagram among the present invention, among the figure U1 is FPGA chip;

Fig. 3 is the configuration circuit schematic diagram of FPGA operating mode among the present invention, among the figure U1 is FPGA chip, and U2 is FPGA configuration PROM, and Y1 is FPGA external crystal oscillator, and JP1 is JTAG bus configuration file download interface;

Fig. 4 is the data communication unit circuit schematic diagram among the present invention, among the figure U3 is MCU microprocessor, and U4, U5 are 485 serial interface chips, and P1 is MCU program download interface, and JP2 is 485 bus interface;

Fig. 5 is the schematic diagram of the slow ramp wave generation circuit in the present invention, in which U7 is a D/A converter, D2 is an external input reference voltage, and U11 is an operational amplifier;

Fig. 6 is a schematic diagram of a fast ramp wave generation circuit in the present invention, in which U10 is an operational amplifier;

Fig. 7 is a schematic diagram of the sampling signal generating circuit in the present invention, and U8 is a comparator among the figures;

Fig. 8 is the schematic diagram of the circuit of the transmitter pulse control unit in the present invention, among which U9 is a CMOS inverter;

Fig. 9 is the schematic diagram of the sampling data receiving unit circuit in the present invention, among which U6 is an A/D converter;

Fig. 10 is the work flowchart of the ground penetrating radar control system based on FPGA of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

As shown in FIG. 1 , the FPGA-based GPR slave control system of the present invention includes: a data communication unit 2 , an FPGA main control unit 3 , a transmitter pulse control unit 4 , a data sampling control unit 5 and a sampling data receiving unit 6 . The upper computer 1 performs serial communication with the data communication unit 2 through the serial 485 bus, and the data communication unit 2 is connected with the IO port of the FPGA main control unit 3 in parallel, and the FPGA main control unit 3 communicates with the transmitter respectively through the on-chip IO ports. The machine pulse control unit 4, the data sampling control unit 5, and the sampling data receiving unit 6 are electrically connected, and the FPGA main control unit 3 completes the radar signal emission and data collection by coordinating the working status of each unit. The transmitter pulse control unit 4 is connected with the transmitter 10, and is responsible for buffering the control signal of the transmission pulse and delivering it to the transmitter 10, and controlling the transmitter circuit to generate a high-power narrow pulse; the data sampling control unit 5 is composed of a slow ramp generation circuit 7, The fast ramp wave generating circuit 9 and the sampling signal generating circuit 8 are composed, and are connected with the sampling circuit 11, and are responsible for generating sampling control signals with different time delays, and controlling the sampling circuit 11 to generate sampling pulses; the sampling data receiving unit 6 is connected with the front of the receiver It is connected with the amplifier circuit 12 and is responsible for converting the analog signal into a digital signal and transmitting it to the FPGA main control unit 3 .

Example 1:

The FPGA main control unit 3 is shown in Figure 2 and Figure 3, where U1 is the FPGA core chip, which adopts the XC3S250E of Xilinx Company, the core operating frequency is set by the external crystal oscillator Y1, and the frequency of Y1 is 50MHz; the FPGA adopts the power-on automatic configuration Working mode, U2 in Figure 3 is the PROM for storing FPGA configuration files, using the standard configuration chip XCF02SVO20C used by FPGAs of Xilinx Company, the PROM is connected to the PC through the JTAG bus JP1, and the configuration files are downloaded to the PROM through the PC for storage . When the system is initially powered on, the FPGA automatically reads the configuration file from the PROM and configures its own internal hardware. After the configuration is completed, the FPGA automatically enters the normal working mode, and the radar system starts to work.

The data communication unit 2 is shown in Figure 4. U3 in the figure is an independently working MCU processor, using ATmega8L-8PC single-chip microcomputer, the core operating frequency is set by the crystal oscillator Y2, the frequency of Y2 is 8MHz, and P1 is the MCU program download port; U4 and U5 A 485 bus interface is formed, and the single-chip microcomputer U3 communicates with the host computer (PC) 1 in a serial manner through U4 and U5. The MCU U3 and FPGA are connected in parallel. The IO ports PB1~PB5, PD2~PD5, and PC0~PC5 of the MCU U3 are respectively connected to the IO ports P53~P78 of the FPGA. The IO port PB1 of the MCU U3 (connected to the FPGA’s P53) is used to reset the FPGA globally, PB2 (P54 connected to FPGA) is used as a data transmission request port, PB3 (P57 connected to FPGA) is used as a data latch port of FPGA to notify the MCU that the data on the data bus is valid, PB4~PC5 (P58~P78 connected to FPGA) 12 IO ports form a 12-bit data bus to transmit 12-bit radar sampling data. When the upper computer 1 needs to perform data transmission, it sends a data transmission request command through the serial 485 bus, and the single-chip microcomputer U3 enables the port PB2 after receiving the command. After the FPGA completes the current complete data sampling, it detects the data transmission request through the P54 pin. Enter the data transmission working mode, load the data sequentially to the 12-bit data bus in parallel, and enable the P57 pin while loading the data. After the microcontroller receives the data from the FPGA, it sends the data to the upper computer 1 sequentially through the 485 bus.

The data sampling control unit 5 is composed of a slow ramp generation circuit 7 , a fast ramp generation circuit 9 and a sampling signal generation circuit 8 . Among them, the slow ramp wave generating circuit 7 is shown in Figure 5, U7 is a D/A converter MAX532, and the digital control input terminals are respectively connected to the P3~P5 and P9 pins of the FPGA, and output different comparisons under the control of the FPGA. Level, the analog slow ramp signal is output by VOUTA (pin 3) of MAX532, the slow ramp signal output by D/A is connected to U11 (LM124), U11 is an operational amplifier, connected as a voltage follower, and used to control D/A performs isolation and impedance transformation, and the output of U11 is connected to the comparator in the sampling signal generation circuit, as shown in Figure 7; the fast ramp wave generation circuit 9 is shown in Figure 6, and U10 (OP07) is a low-frequency operational amplifier , connected in the form of a follower, the function is to isolate the quiescent working current of Q2 and Q3, Q2 is a PNP switching transistor 2N4036, the function is to provide current for the switching circuit, Q3 is an NPN switching transistor 3DK4, used to control the integral capacitor C26 During the charging and discharging process, the fast ramp control signal is output by the P2 pin of the FPGA, and connected to the base of Q3 through the DC blocking capacitor C13 and the current limiting resistor R20. When the high level is high, Q3 is turned on, and C26 is discharged. Charge to form a fast ramp signal. The fast ramp signal is connected with the comparator U8 in the sampling signal generating circuit 8 through the DC blocking capacitor C28, as shown in Figure 7; the sampling signal generating circuit 8 is as shown in Figure 7, and U8 is a comparator LM319, slow, fast The ramp voltage is respectively connected to the comparator U8 from pins 4 and 5. When the fast ramp voltage exceeds the slow ramp voltage, it outputs a low level, and the switching transistors Q1 and Q4 (3DK4) are respectively responsible for controlling the comparator U8. The signal is reversed and current drive is provided for the signal output, and the sampling control signal is output from the emitter of Q4 through the DC blocking capacitor C24.

Transmitter pulse control unit 4 is shown in Figure 8. The pulse control signal is output from pin P23 of FPGA, connected to pin 1 of COMS inverter U9 (74HC04), and output from pin 2 after inversion. Since the input terminal of the transmitter 10 is an inductive load and the DC input impedance is low, the pulse control signal output by the FPGA is connected to the transmitter 10 through the inverter U9, and the function of the inverter U9 is to connect the IO port of the FPGA to the transmitter. The input terminal of the transmitter 10 is isolated to prevent the IO port of the FPGA from being burned by the high current at the input terminal of the transmitter 10.

The sampling data receiving unit 6 is shown in Figure 9, after the sampling data of the radar signal is amplified by the preamplifier circuit 12 of the receiver, it is connected to the A/D converter U6, and U6 converts the sampling analog signal into The digital signal is received by the FPGA in a serial manner. Specifically: 12-bit A/D converter U6 (AD7866) digital control terminal pins 11, 15, 18~20 are respectively connected to P91, P90, P86~P84 of the FPGA, and the sampling analog signal is connected to the A/D converter The VA1 input terminal (pin 7), the working mode of the A/D converter is selected as the input voltage range of 0~5V, and the internal reference voltage of the A/D is used. FPGA reads the data after A/D conversion into FPGA from the pin DoutA of A/D converter through serial mode and stores them.

The working process of the FPGA control system is shown in Figure 10. After power-on, the FPGA initializes the system, resets the internal registers, and then enters the normal working mode. FPGA has two working modes, which are the radar detection working mode (step 2 ) and data transmission working mode (step 3). After the radar is turned on, the working process continues in a loop, and switches between the two working states according to the instructions of the host computer. The specific working process is as follows:

Step 1. The FPGA first checks whether there is a sampling data request sent by the upper computer 1: if the upper computer 1 does not send a data request, it enters the radar detection working mode (actually, since the radar needs to be warmed up and stabilized after it is turned on, the upper computer 1 No data request will be sent at this time, so the radar will enter the radar detection working mode after it is turned on), that is, enter step 2; if the host computer 1 has a data request to send, it will enter the data transmission working mode, and the last radar sampling The result is sent to the host computer 1, that is, enter step 3;

Step 2: When the main control system is in the radar detection mode, the first step is to update the output of the D/A converter U7 to generate a slow ramp; the second step is to send a fast ramp trigger signal to generate a fast ramp. The ramp wave passes through the comparator U8 to generate sampling control signals with different delays; in the third step, the radar sends the transmitter pulse control signal to trigger the transmitter 10 to emit narrow pulses; in the fourth step, control the A/D converter U6 to sample the data Carry out analog-to-digital conversion; the fifth step, store the currently collected radar echo data in the internal memory; the sixth step, check whether all the sampling points on different time delays have been collected according to the system settings, if not After the completion, repeat steps 1 to 5. If the collection is complete, jump out of the detection mode, return to step 1, and re-detect whether there is a data request sent by the host computer 1;

Step 3. The main control system is in the data transmission working mode. The first step is to read the sampling data from the memory according to the current address sequence, and send it to the upper computer 1 through serial mode; the second step is to detect whether the current sampling data is All the data has been sent, if not, repeat the first step until the data of all sampling points are sent, the FPGA jumps out of the data transmission mode, returns to step 1, and re-checks whether the host computer 1 has a data request (Actually, since the host computer 1 cannot continuously send data transmission requests, the radar will enter the radar detection working mode at least once after completing a data transmission).

Claims (2)

1. FPGA-based ground penetrating radar lower computer control system, characterized in that the system includes a data communication unit (2), an FPGA main control unit (3), a transmitter pulse control unit (4), a data sampling control unit (5 ) and the sampling data receiving unit (6), the data communication unit (2) communicates serially with the upper computer (1) of the ground penetrating radar through the serial 485 bus, and communicates with the IO of the FPGA main control unit (3) in parallel connected to the ports; the FPGA main control unit (3) is electrically connected to the transmitter pulse control unit (4), the data sampling control unit (5), and the sampling data receiving unit (6) through the IO port, and the FPGA main control unit (3) By coordinating the working status of each unit, the radar signal emission and data acquisition work is completed; the transmitter pulse control unit (4) is connected with the transmitter (10) of the ground penetrating radar, which is responsible for buffering and transmitting the control signal of the emission pulse to the The transmitter (10) controls the transmitter circuit to generate high-power narrow pulses; the data sampling control unit (5) is connected to the sampling circuit (11) of the ground penetrating radar, which is responsible for generating sampling control signals with different delays, and controlling the sampling circuit ( 11) Generate sampling pulses; the sampling data receiving unit (6) is connected to the preamplifier circuit (12) of the ground penetrating radar receiver, which is responsible for converting analog signals into digital signals and transmitting them to the FPGA main control unit (3). 2. The FPGA-based ground penetrating radar slave computer control system according to claim 1, wherein the data sampling control unit (5) consists of a slow ramp generation circuit (7), a fast ramp generation circuit (9 ) and the sampling signal generation circuit (8), the slow ramp generation circuit (7), the fast ramp generation circuit (9) are connected to the sampling signal generation circuit (8), the slow ramp generation circuit (7) generates slow ramp wave, the fast ramp wave generating circuit (9) generates a fast ramp wave; the sampling signal generating circuit (8) is connected to the sampling circuit (11), which outputs sampling control signals with different delays by comparing the slow ramp wave and the fast ramp wave, Driving the sampling circuit (11) to generate sampling pulses.

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