CN102789762B - Driving circuit, array base palte and display device - Google Patents
Driving circuit, array base palte and display device Download PDFInfo
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- CN102789762B CN102789762B CN201210279328.2A CN201210279328A CN102789762B CN 102789762 B CN102789762 B CN 102789762B CN 201210279328 A CN201210279328 A CN 201210279328A CN 102789762 B CN102789762 B CN 102789762B
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Abstract
The invention provides a kind of driving circuit, array base palte and display device, this driving circuit comprises: time schedule controller and multiple gate drivers, wherein, the described time schedule controller first grid driver nearest with time schedule controller described in the distance in described multiple gate drivers is directly connected by timing control signal transmission line, and described time schedule controller is also directly connected by timing control signal transmission line with at least one the second grid driver except described first grid driver in described multiple gate drivers.In the present invention, time schedule controller is directly connected by timing control signal transmission line with gate drivers, the timing control signal that time schedule controller can be transferred to gate drivers carries out differential control, thus can effectively avoid the face glass impedance because of liquid crystal array substrate too large, the problem that the control signal causing gate drivers to receive is delayed.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of driving circuit, array base palte and display device.
Background technology
Be illustrated in figure 1 the structural representation of the driving circuit for array base palte of the prior art, this driving circuit comprises: time schedule controller (TCON) 101 and two gate drivers (Gate driver) (gate drivers 102a and gate drivers 102b), wherein, time schedule controller 101 can export the control signal for control gate driver 102a and gate drivers 102b such as STV signal (frame start signal), OE signal (output enable signal) and CPV signal (clock signal).
As can be seen from Figure 1, in prior art, all by time schedule controller 101 for transmitting the signal transmssion line (103a, 103b, 103c, 103d) of STV signal, OE signal and CPV signal, the face glass entering array base palte is inner, then the gate drivers 102a near time schedule controller 101 is entered, entered the glass substrate inside of array base palte again by gate drivers 102a, finally enter the gate drivers 102b away from time schedule controller 101.That is, gate drivers 102a and gate drivers 102b is serially connected.In Fig. 1, signal transmssion line 103a, 103b, 103c, 103d are respectively used to transmission STV2, STV1, OE and CPV signal.
There is following problem in above-mentioned driving circuit: because gate drivers 102a and gate drivers 102b are that tandem is connected, control signal needs after gate drivers 102a, just can enter and be positioned at gate drivers 102b, thus when the base plate glass impedance of array base palte is too large, the control signal that gate drivers 102a and gate drivers 102b can be caused to receive is delayed, thus the output waveform in proper order (G on) that gate drivers 102a and gate drivers 102b is exported produces unmatched problem.
Summary of the invention
In view of this, the invention provides a kind of driving circuit, array base palte and display device, the base plate glass impedance that can solve due to array base palte in prior art is too large, the control signal causing the gate drivers of multiple series connection to receive is delayed, thus the output waveform in proper order causing different gate drivers to export produces unmatched problem.
For solving the problem, the invention provides a kind of driving circuit, comprise: time schedule controller and multiple gate drivers, wherein, the described time schedule controller first grid driver nearest with time schedule controller described in the distance in described multiple gate drivers is directly connected by timing control signal transmission line, and described time schedule controller is also directly connected by timing control signal transmission line with at least one the second grid driver except described first grid driver in described multiple gate drivers.
Preferably, described time schedule controller is all directly connected by timing control signal transmission line with all second grid drivers except described first grid driver in described multiple gate drivers.
Preferably, described time schedule controller comprises: corresponding with described timing control signal transmission line, exports the working storage of described timing control signal transmission line for Control timing sequence control signal to.
Preferably, described driving circuit also comprises:
Frame start signal for being exported by described time schedule controller is transferred to the frame start signal transmission line of described gate drivers.
Preferably, described frame start signal transmission line comprises:
First frame start signal transmission line, described time schedule controller is directly connected respectively by described first frame start signal transmission line with described first grid driver and described second grid driver.
Preferably, described frame start signal transmission line also comprises:
Second frame start signal transmission line, described second frame start signal transmission line is connected with described time schedule controller, and is connected in series by described multiple gate drivers successively.
Preferably, described frame start signal transmission line also comprises:
3rd frame start signal transmission line, one end of described 3rd frame start signal transmission line is connected with described time schedule controller, and the other end is directly connected with time schedule controller gate drivers farthest described in the distance in described multiple gate drivers.
Preferably, connect respectively by described timing control signal transmission line between adjacent described gate drivers.
Preferably, described timing control signal transmission line comprises: for transmitting the timing control signal transmission line of OE signal and the timing control signal transmission line for transmitting CPV signal.
The present invention also provides a kind of array base palte, comprises above-mentioned driving circuit.
The present invention also provides a kind of display device, comprises above-mentioned array base palte.
The present invention has following beneficial effect:
Time schedule controller is directly connected by timing control signal transmission line with gate drivers, the timing control signal that time schedule controller can be transferred to gate drivers carries out differential control, thus can effectively avoid the substrate impedance because of array base palte too large, the problem that the control signal causing gate drivers to receive is delayed.
Accompanying drawing explanation
Fig. 1 is the structural representation of driving circuit of the prior art;
Fig. 2 is the structural representation of the driving circuit of embodiments of the invention one;
Fig. 3 is the structural representation of the driving circuit of embodiments of the invention two;
Fig. 4 is the structural representation of the driving circuit of embodiments of the invention three;
Fig. 5 is the structural representation of the driving circuit of embodiments of the invention four;
Fig. 6 is the structural representation of the driving circuit of embodiments of the invention five;
Fig. 7 is the structural representation of the driving circuit of embodiments of the invention six.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
Embodiment one:
Be illustrated in figure 2 the structural representation of the driving circuit of embodiments of the invention one, this driving circuit is applied to array basal plate, this driving circuit comprises: time schedule controller 201 and two gate drivers (gate drivers 202a and gate drivers 202b), described time schedule controller 201 is directly connected by timing control signal transmission line 203a and timing control signal transmission line 203b with between the gate drivers 202a of described time schedule controller 201, directly be connected by timing control signal transmission line 203c and timing control signal transmission line 203d between described time schedule controller 201 with the gate drivers 202b away from described time schedule controller 201, namely be directly connected respectively by timing control signal transmission line between time schedule controller 201 with two gate drivers.In this embodiment, gate drivers 202a is first grid driver, and gate drivers 202b is second grid driver
As can be seen from Figure 2, the timing control signal transmission line be connected with gate drivers is all by described time schedule controller 201, and the substrate entering array base palte is inner, is then directly connected to corresponding described gate drivers.
In the present embodiment, comprise two gate drivers for driving circuit to be described, certainly, in other embodiments of the invention, driving circuit also can comprise more gate drivers, when driving circuit comprises the gate drivers more than two, the time schedule controller in driving circuit is same with between the plurality of gate drivers directly can be connected respectively by timing control signal transmission line.
By the driving circuit that above-described embodiment provides, time schedule controller is all directly connected by timing control signal transmission line with all gate drivers, but not all gate drivers are together in series, thus the timing control signal that time schedule controller can be transferred to each gate drivers carries out differential control, the glass substrate impedance that effectively prevent because of array base palte is too large, the control signal causing gate drivers under tandem to receive is delayed, and then the output waveform in proper order causing different gate drivers to export produces unmatched problem.Certainly, array base palte can select the substrate of unlike material as required, as glass substrate, quartz base plate or plastics etc., also can adopt the driving circuit of the present embodiment.
Embodiment two:
Be illustrated in figure 3 the structural representation of the driving circuit of embodiments of the invention two, this driving circuit is applied to array basal plate, this driving circuit comprises: time schedule controller 201 and three gate drivers (gate drivers 202a, gate drivers 202b and gate drivers 202c), described time schedule controller 201 with near the gate drivers 202a(of described time schedule controller 201 and first grid driver) between be directly connected by timing control signal transmission line 203a and timing control signal transmission line 203b, described time schedule controller 201 is directly connected by timing control signal transmission line 203c and timing control signal transmission line 203d with between described time schedule controller 201 gate drivers 202b farthest, the gate drivers 202c mediated is connected by timing control signal transmission line 203e and timing control signal transmission line 203f with described gate drivers 202a, gate drivers 202b and gate drivers 202c is second grid driver.
In the present embodiment, time schedule controller 201 is all directly connected by timing control signal transmission line with the gate drivers 202a nearest apart from this time schedule controller 201 and apart from this time schedule controller gate drivers 202b farthest, but not all gate drivers are together in series, thus the timing control signal that time schedule controller can be transferred to gate drivers 202a and gate drivers 202b carries out differential control, avoid the control signal received apart from time schedule controller 201 gate drivers 202b farthest and be delayed.
In the present embodiment, also can be together in series by one group of timing control signal transmission line between gate drivers 202b and gate drivers 202c.When gate drivers 202b is both direct-connected with time schedule controller 201, when connecting with adjacent gate drivers again, gate drivers 202b likely can receive the identical timing control signal of two set types simultaneously, when gate drivers 202b receives the identical timing control signal of two set types, one group of timing control signal in these two groups can be selected according to specific needs to use.
In above-described embodiment, when driving circuit has multiple gate drivers, time schedule controller, except except the first grid driver nearest apart from this time schedule controller is directly connected by timing control signal transmission line, also with apart from this time schedule controller gate drivers is farthest directly connected by timing control signal transmission line.In addition, in other embodiments of the invention, when driving circuit has multiple gate drivers, time schedule controller, except except the gate drivers nearest apart from this time schedule controller is directly connected by timing control signal transmission line, directly can also be connected by timing control signal transmission line with any one or more second grid drivers except this first grid driver in the plurality of gate drivers.
In above-described embodiment for connecting time schedule controller and gate drivers, or include two timing control signal transmission lines for the one group of timing control signal transmission line connecting adjacent gate drivers: one is the timing control signal transmission line for transmitting OE signal, and another is the timing control signal transmission line for transmitting CPV signal.
Certainly, in other embodiments of the invention, for connecting time schedule controller and gate drivers, or for connect adjacent gate drivers one group of timing control signal transmission line in also can comprise one or more timing control signal transmission lines (more than two).
Time schedule controller is except except gate drivers output timing control signal, also for gate drivers output frame start signal (STV signal), thus, in the present embodiment, between time schedule controller and gate drivers, also need the STV signal transmssion line be connected with for transmitting STV signal.STV signal transmssion line can adopt set-up mode of the prior art, and the set-up mode of STV signal transmssion line also can be identical with above-mentioned clock signal transmission line.
Embodiment three:
The set-up mode of STV signal transmssion line can be identical with above-mentioned clock signal transmission line.
Be illustrated in figure 4 the structural representation of the driving circuit of the embodiment of the present invention three, the difference of the driving circuit in the driving circuit in the present embodiment and the embodiment shown in Fig. 2 one is, also comprise: the first frame start signal line, described first frame start signal line comprises STV signal transmssion line 204a and STV signal transmssion line 204b, except passing through timing control signal line 203a between time schedule controller 201 and gate drivers 202a, outside 203b directly connects, also directly connected by STV signal transmssion line 204a, except passing through timing control signal line 203c between time schedule controller 201 and gate drivers 202b, outside 203d directly connects, also directly connected by STV signal transmssion line 204b.
In embodiment three, comprise two gate drivers for driving circuit to be described, certainly, in other embodiments of the invention, driving circuit can also comprise the gate drivers more than two, when driving circuit comprises the gate drivers more than two, all directly can be connected by the first frame start signal transmission line between time schedule controller with multiple gate drivers.
Embodiment four:
STV signal transmssion line also can adopt set-up mode of the prior art.
Be illustrated in figure 5 the structural representation of the driving circuit of the embodiment of the present invention four, the difference of the driving circuit in the driving circuit in the present embodiment and the embodiment shown in Fig. 2 one is, also comprise: STV signal transmssion line 205, described STV signal transmssion line 205 is connected with described time schedule controller 201, and is connected in series by gate drivers 202a and gate drivers 202b successively.For the ease of difference, in this embodiment, STV signal transmssion line can be called the second frame start signal transmission line.
In embodiment four, comprise two gate drivers for driving circuit to be described, certainly, in other embodiments of the invention, driving circuit can also comprise the gate drivers more than two, when driving circuit comprises the gate drivers more than two, can be connected in series by the second frame start signal transmission line between time schedule controller and multiple gate drivers.
Embodiment five:
When STV signal transmssion line adopts the method to set up shown in Fig. 5, because first STV signal demand is transferred to the gate drivers 202a being positioned at bottom, thus only can scan the grid line corresponding from the gate drivers 202a being positioned at bottom.And in some cases, also may need to scan from the grid line that the gate drivers 202b being positioned at the top is corresponding, thus, for meeting this demand, as shown in Figure 6, on the basis of the embodiment shown in Fig. 5, described driving circuit can also comprise: STV signal transmssion line 206, one end of described STV signal transmssion line 206 is connected with described time schedule controller 201, and the other end is directly connected with apart from described time schedule controller 201 gate drivers 202b farthest.For the ease of difference, in this embodiment, STV signal transmssion line can be called the 3rd frame start signal transmission line.
Embodiment six:
When the delay of the control signal that multiple gate drivers receives is less, also can retain design of the prior art, be connected in series between the multiple gate drivers in driving circuit by timing control signal transmission line.
Be illustrated in figure 7 the structural representation of the driving circuit of embodiments of the invention six, the difference compared with the driving circuit of the embodiment five shown in Fig. 6 of driving circuit in the present embodiment is, is connected between adjacent gate drivers 202a and gate drivers 202b respectively by timing control signal transmission line 203g with timing control signal transmission line 203h.
When between gate drivers 202a and gate drivers 202b, timing control signal transmission line connects, gate drivers 202b likely can receive the identical timing control signal of two set types simultaneously, wherein, one group of timing control signal is by timing control signal transmission line 203c direct-connected between time schedule controller 201 and gate drivers 202b, 203d transmits, another group timing control signal is transferred to the gate drivers 202a being positioned at bottom by time schedule controller 201, and then by being positioned at the gate drivers 202a of bottom by timing control signal transmission line 203g, 203h transmits.When gate drivers 202b receives the identical timing control signal of two set types, one group of timing control signal in these two groups can be selected according to specific needs to use.
Time schedule controller in each embodiment above-mentioned all can comprise: one is corresponding with described timing control signal transmission line, exports the working storage of described timing control signal transmission line for Control timing sequence control signal to.
Certainly, in other embodiments of the present invention, described time schedule controller is not got rid of the output of other modes of employing to timing control signal yet and is controlled.
The embodiment of the present invention also provides a kind of array base palte, and this array base palte comprises the driving circuit in above-mentioned any embodiment.Array base palte can select the substrate of unlike material as required, as glass substrate, quartz base plate or plastics etc.
The embodiment of the present invention provides a kind of display device, has the array base palte of the arbitrary characteristics described by above-described embodiment.This display device can be liquid crystal indicator, comprises the array base palte that the color membrane substrates of opposing parallel setting and above-described embodiment propose, and is filled in the liquid crystal between described color membrane substrates and array base palte; This display device can be also OLED display, comprises the array base palte that above-described embodiment proposes, and the luminous organic material of evaporation on this array base palte and encapsulation cover plate.
The liquid crystal indicator that the embodiment of the present invention provides, described liquid crystal indicator can have the product of Presentation Function for liquid crystal display, LCD TV, digital album (digital photo frame), mobile phone, panel computer etc. or portion the present invention does not limit.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (11)
1. a driving circuit, comprise: be applied to the time schedule controller in array basal plate and multiple gate drivers, wherein, the described time schedule controller first grid driver nearest with time schedule controller described in the distance in described multiple gate drivers is directly connected by timing control signal transmission line, it is characterized in that, described time schedule controller is also directly connected by timing control signal transmission line with at least one the second grid driver except described first grid driver in described multiple gate drivers, described timing control signal transmission line is arranged on described array base palte,
Described time schedule controller comprises: corresponding with described timing control signal transmission line, exports the module of described timing control signal transmission line for Control timing sequence control signal to.
2. driving circuit as claimed in claim 1, it is characterized in that, described time schedule controller is all directly connected by timing control signal transmission line with all second grid drivers except described first grid driver in described multiple gate drivers.
3. driving circuit as claimed in claim 1 or 2, is characterized in that, the described module exporting described timing control signal transmission line to for Control timing sequence control signal is working storage.
4. driving circuit as claimed in claim 1 or 2, is characterized in that, also comprise:
Frame start signal for being exported by described time schedule controller is transferred to the frame start signal transmission line of described gate drivers.
5. driving circuit as claimed in claim 4, it is characterized in that, described frame start signal transmission line comprises:
First frame start signal transmission line, described time schedule controller is directly connected respectively by described first frame start signal transmission line with described first grid driver and described second grid driver.
6. driving circuit as claimed in claim 4, it is characterized in that, described frame start signal transmission line also comprises:
Second frame start signal transmission line, described second frame start signal transmission line is connected with described time schedule controller, and is connected in series by described multiple gate drivers successively.
7. driving circuit as claimed in claim 6, it is characterized in that, described frame start signal transmission line also comprises:
3rd frame start signal transmission line, one end of described 3rd frame start signal transmission line is connected with described time schedule controller, and the other end is directly connected with time schedule controller gate drivers farthest described in the distance in described multiple gate drivers.
8. driving circuit as claimed in claim 1 or 2, is characterized in that, connects between adjacent described gate drivers respectively by described timing control signal transmission line.
9. driving circuit as claimed in claim 1 or 2, it is characterized in that, described timing control signal transmission line comprises: for transmitting the timing control signal transmission line of OE signal and the timing control signal transmission line for transmitting CPV signal.
10. an array base palte, is characterized in that, comprises the driving circuit described in any one of claim 1-9.
11. 1 kinds of display device, is characterized in that, comprise array base palte according to claim 10.
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| CN201210279328.2A CN102789762B (en) | 2012-08-07 | 2012-08-07 | Driving circuit, array base palte and display device |
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| CN201210279328.2A CN102789762B (en) | 2012-08-07 | 2012-08-07 | Driving circuit, array base palte and display device |
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| CN102789762A CN102789762A (en) | 2012-11-21 |
| CN102789762B true CN102789762B (en) | 2015-09-02 |
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| CN103531169B (en) * | 2013-10-30 | 2015-09-09 | 京东方科技集团股份有限公司 | A kind of display driver circuit and driving method, display device |
| US10950194B1 (en) * | 2019-10-04 | 2021-03-16 | Solomon Systech (Shenzhen) Limited | Display panel with distributed driver network |
| CN110942724A (en) * | 2019-12-19 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | Folding display panel and display device |
| CN113936603B (en) * | 2021-10-28 | 2023-04-11 | 京东方科技集团股份有限公司 | Display device, data transmission method, apparatus, and storage medium |
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| CN101783117A (en) * | 2009-01-20 | 2010-07-21 | 联咏科技股份有限公司 | Gate driver and display driver using it |
| CN102103294A (en) * | 2009-12-17 | 2011-06-22 | 联咏科技股份有限公司 | Gate drive circuit and relevant liquid crystal display |
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| CN101345030B (en) * | 2007-07-11 | 2011-07-27 | 联詠科技股份有限公司 | Display device and method for driving display panel thereof |
| JP2010091612A (en) * | 2008-10-03 | 2010-04-22 | Seiko Epson Corp | Electrophoretic display device, electronic apparatus, and method of driving electrophoretic display device |
| CN102592516B (en) * | 2012-02-29 | 2013-12-25 | 信利半导体有限公司 | Large size display screen |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783117A (en) * | 2009-01-20 | 2010-07-21 | 联咏科技股份有限公司 | Gate driver and display driver using it |
| CN102103294A (en) * | 2009-12-17 | 2011-06-22 | 联咏科技股份有限公司 | Gate drive circuit and relevant liquid crystal display |
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