CN102779745A - Method for controlling thickness of trench transistor gate dielectric layer - Google Patents
Method for controlling thickness of trench transistor gate dielectric layer Download PDFInfo
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- CN102779745A CN102779745A CN2012102566772A CN201210256677A CN102779745A CN 102779745 A CN102779745 A CN 102779745A CN 2012102566772 A CN2012102566772 A CN 2012102566772A CN 201210256677 A CN201210256677 A CN 201210256677A CN 102779745 A CN102779745 A CN 102779745A
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Abstract
A method for controlling the thickness of a trench transistor gate dielectric layer includes: providing a test substrate which comprises device areas and cut passages between each two adjacent device areas; forming first trenches in the device areas of the test substrate, and forming second trenches in the cut passages of the test substrate, wherein the crystal orientation of the side wall of the each second trench deflects by a 45-degree angle relative to each first trench; forming a first oxide layer and a second oxide layer in each first trench and each second trench respectively by means of the thermal oxidation technology; acquiring technical parameters of forming the second oxide layers in preset thickness; providing an epitaxial substrate with device areas, wherein the crystal orientation of the side wall of a wafer notch of the epitaxial substrate forms a 45-degree angle relative to a wafer notch of the test substrate; forming third trenches in the device areas of the epitaxial substrate according to the positions of the first trenches and the technical parameters; and forming third oxide layers in the third trenches by means of the thermal oxidation technology with technical parameters identical to those of forming the second oxide layers in the preset thickness. The thickness of the gate dielectric layer in the epitaxial substrate device areas is easy to control.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of method of controlling trench transistor gate dielectric layer thickness.
Background technology
At present, transistor is widely used as a kind of basic semiconductor device.And in various transistors, trench metal-oxide-semiconductor field effect transistor (Trench Metal-Oxide-Silicon Transistors, Trench MOS) is extensively applied in integrated circuit and the discrete device circuit as a kind of power device.
The cross-sectional view of the forming process of existing trench transistor, comprising to shown in Figure 4 like Fig. 1:
Please refer to Fig. 1; Semiconductor substrate 100 is provided; Said Semiconductor substrate 100 comprises: the epitaxial loayer of silicon substrate and above-mentioned surface of silicon has groove 101, the sidewall of said groove 101 and Semiconductor substrate 100 Surface Vertical in the epitaxial loayer of said Semiconductor substrate 100.
Please refer to Fig. 2, at the sidewall and the lower surface formation gate dielectric layer 102 of said groove 101 (like Fig. 1), the material of said gate dielectric layer 102 is a silica, and the formation technology of said gate dielectric layer 102 is thermal oxidation technology; Form the gate electrode layer 103 of filling full said groove 101 on said gate dielectric layer 102 surfaces.
Please refer to Fig. 3, after forming gate electrode layer 103, form mask layer 104 on said Semiconductor substrate 100 surfaces, said mask layer 104 exposes gate electrode layer 103 and part semiconductor substrate 100 surfaces;
Please refer to Fig. 4, is mask with said mask layer 104, and ion injects and forms tagma 107 in said Semiconductor substrate 100;
Please refer to Fig. 5, after forming tagma 107, form mask layer 106 on said gate electrode layer 103 and gate dielectric layer 102 surfaces; Is mask with mask layer 104 with mask layer 106, and ion injects and forms source region 105 in Semiconductor substrate 100.
Yet the thickness of the gate dielectric layer in the existing trench transistor can't accurately be controlled, and causes the parameter such as cut-in voltage and the designing requirement of formed trench metal-oxide-semiconductor field effect transistor that deviation is arranged.
More trench transistors please refer to the Chinese patent file that publication number is CN 102110687A.
Summary of the invention
The problem that the present invention solves provides a kind of method of controlling trench transistor gate dielectric layer thickness, and the gate medium Thickness Control that makes formed epitaxial substrate device region and adjustment can be more accurately, cost is lower, and the device performance of formation is better.
For addressing the above problem; The present invention provides a kind of method of controlling trench transistor gate dielectric layer thickness, comprising: test substrate is provided, and said test substrate has some device regions; Said adjacent devices has the Cutting Road district between the district, and the edge of said test substrate has the wafer notch; In the device region of said test substrate, form some first grooves that are parallel to each other; In the Cutting Road district of said test substrate, form some second grooves that are parallel to each other simultaneously; The crystal orientation of said second trenched side-wall is with respect to the crystal orientation deflection miter angle of said first trenched side-wall; When the shape of said first groove reaches preset shape, obtain the technological parameter that forms said first groove; Adopt thermal oxidation technology to form first oxide layer in the sidewall and the lower surface of said first groove; Sidewall and lower surface at said second groove form second oxide layer simultaneously; When said second thickness of oxide layer reaches preset thickness, obtain the formation technological parameter of said second oxide layer; Epitaxial substrate is provided, and said epitaxial substrate has some device regions, and the edge of said epitaxial substrate has the wafer notch, and the crystal orientation of said epitaxial substrate wafer notch becomes miter angle with respect to the crystal orientation of test substrate wafer notch; Adopt the technological parameter of said first groove, in the device region of said epitaxial substrate, form some the 3rd grooves that are parallel to each other; Adopt thermal oxidation technology to form the 3rd oxide layer in the sidewall and the lower surface of said the 3rd groove, the parameter of said thermal oxidation technology is identical with the technological parameter of second oxide layer that forms preset thickness.
Alternatively, be 100 dusts ~ 1000 dusts in said preset thickness.
Alternatively, the preset shape of said first groove comprises: the degree of depth of said first groove is 0.8 ~ 2 micron, and the bottom of said first groove is slick and sly to test substrate sunken inside and surface.
Alternatively, the formation step of said first groove and second groove is: with first mask blank, form first photoresist layer on the test substrate surface; With said first photoresist layer is mask, adopts etching technics in the device region of said test substrate, to form some first grooves that are parallel to each other simultaneously, in the Cutting Road district of said test substrate, forms some second grooves that are parallel to each other.
Alternatively, the step of said the 3rd groove is: with first mask blank, form second photoresist layer at the extension substrate surface; With said second photoresist layer is mask, adopts etching technics in the device region of said epitaxial substrate, to form some the 3rd grooves that are parallel to each other; When forming said the 3rd groove, in the Cutting Road district of said epitaxial substrate, form some the 4th grooves that are parallel to each other.
Alternatively, the technological parameter of said first groove comprises: the position of etching gas, etch period, etching bias voltage and said first groove.
Alternatively, the technological parameter of second oxide layer of said formation preset thickness comprises: reacting gas, reaction time and reaction temperature.
Alternatively, the step of obtaining said second oxidated layer thickness is: said second oxide layer is cut into slices; Section to said second oxide layer section is measured, and obtains said second thickness of oxide layer.
Alternatively, also comprise: after forming first oxide layer and second oxide layer, in said first groove, form the first grid electrode layer of filling full said first groove, in said second groove, form second gate electrode layer of filling full said second groove; Obtain forming the technological parameter of the said first grid electrode layer and second gate electrode layer.
Alternatively, to form the technological parameter of the said first grid electrode layer and second gate electrode layer, in said the 3rd groove, form the 3rd gate electrode layer of filling full said the 3rd groove.
Alternatively, the material of said first grid electrode layer, second gate electrode layer and the 3rd gate electrode layer is a polysilicon.
Alternatively, said epitaxial substrate also comprises: the Cutting Road district between the adjacent devices district.
Alternatively, said epitaxial substrate comprises: silicon substrate and the epitaxial loayer that is positioned at said surface of silicon.
Alternatively, said test substrate is a silicon substrate.
Alternatively, the crystal orientation of the wafer notch of said test substrate or epitaxial substrate is identical with the direction of diameter wafer through said wafer notch.
Alternatively, the notch crystal orientation of said epitaxial substrate is < 100 >.
Alternatively, the notch crystal orientation of said test substrate is < 110 >.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the Cutting Road district of test substrate, form second groove, adopt thermal oxidation technology to form second oxide layer in the sidewall and the lower surface of said second groove, and when said second thickness of oxide layer reaches preset thickness, the recording process parameter; And in the 3rd groove, forming the 3rd oxide layer with said technological parameter, said the 3rd channel shaped is formed in the device region of epitaxial substrate, and position and shape are identical with position and the shape of first groove in the device region of test substrate; Because the crystal orientation of said epitaxial substrate wafer notch becomes miter angle with respect to the crystal orientation of test substrate wafer notch, therefore the crystal face of the 3rd trenched side-wall becomes miter angle with respect to the crystal face of said first trenched side-wall; When the crystal orientation of said second trenched side-wall during with respect to the crystal orientation deflection miter angle of said first trenched side-wall; The sidewall of said second groove is identical with the indices of crystallographic plane of the 3rd groove with the indices of crystallographic plane of lower surface; The covalent bond density of the sidewall of said second groove and the lower surface also covalent bond density with the sidewall of said the 3rd groove and lower surface is identical, and second oxide layer that therefore adopts identical thermal oxidation technology to form is identical with the 3rd oxidated layer thickness; When formation in second groove in test substrate reaches second oxide layer of preset thickness; Record thermal oxidation technology parameter at that time; And in the 3rd groove, forming the 3rd oxide layer with identical thermal oxidation technology, formed the 3rd oxide layer can reach preset thickness too; When the gate medium Thickness Control of said the 3rd oxide layer formed epitaxial substrate device region during and adjustment as the gate dielectric layer of trench transistor can be more accurately, cost is lower, the device performance of formation is better.
Description of drawings
Fig. 1 to Fig. 5 is the cross-sectional view of the forming process of existing trench transistor;
Fig. 6 is the structural representation of (110) crystal face and (100) crystal face;
Fig. 7 is the schematic flow sheet of method of the control trench transistor gate dielectric layer thickness of the embodiment of the invention;
Fig. 8 to Figure 10, Figure 13 to 15 are plan structure sketch mapes of process of the control trench transistor gate dielectric layer thickness of the embodiment of the invention;
Figure 11 is the cross-sectional view of Figure 10 on AA ' direction;
Figure 12 is the cross-sectional view of Figure 10 on BB ' direction;
Figure 16 is the cross-sectional view of Figure 15 on CC ' direction;
Figure 17 is the cross-sectional view of Figure 15 on DD ' direction.
Embodiment
Of background technology, the thickness of the gate dielectric layer in the existing trench transistor can't accurately be controlled, and causes the parameters such as cut-in voltage of formed trench metal-oxide-semiconductor field effect transistor that deviation is arranged.
Whether prior art can at first form the trench transistor of required formation on test substrate when forming trench transistor, suitable with the technological process parameter of confirming the said trench transistor of formation; Afterwards, with fixed technological process, on epitaxial substrate, form trench transistor, thereby avoid the waste of epitaxial substrate, practice thrift cost.
Because said test substrate is usually used in providing the usefulness of the test of the various devices of integrated circuit,, unifiedly usually use comparatively cheap silicon chip therefore in order to practice thrift cost; The crystal face of said silicon chip surface all identical (like (100) crystal face); And said silicon chip has the crystal orientation of identical wafer notch, < 110>crystal orientation for example, wherein; Said wafer notch be used for each technical process confirm wafer side to usefulness, and the crystal orientation of said wafer notch is consistent with diameter wafer direction through said notch; Yet need the formal epitaxial substrate that forms trench transistor, its wafer notch crystal orientation can be according to requirement on devices and difference, for example < 100>crystal orientation; Because the crystal orientation of the trenched side-wall of the trench transistor of required formation is parallel to each other with the crystal orientation of said wafer notch or is vertical, and identical with shape in the test substrate with the interior groove position of epitaxial substrate; Particularly; When the wafer notch crystal orientation of silicon chip is < 110 >; When the wafer notch crystal orientation of epitaxial substrate is < 100 >; And when the crystal orientation of trenched side-wall was parallel with the crystal orientation of wafer notch, the crystal face that is positioned at the trenched side-wall of test substrate was (110), and the crystal face of the trenched side-wall in epitaxial substrate is (100); Please refer to Fig. 6,, can know that the crystal face of the trenched side-wall in the said epitaxial substrate becomes miter angle with respect to the crystal face of the trenched side-wall in the said test substrate for the structural representation of (110) crystal face and (100) crystal face by Fig. 6.
Inventor of the present invention is through discovering; Because the trenched side-wall crystal face of said test substrate is different with the trenched side-wall crystal face of said epitaxial substrate; When respectively when the same position of test substrate and epitaxial substrate forms the identical groove of shape, the covalent bond density of its sidewall and lower surface is different; When adopting identical thermal oxidation technology, when trenched side-wall in test substrate and outer substrate and lower surface formed gate dielectric layer respectively, the thickness of formed gate dielectric layer was different; Concrete, obtain through inventor's repeatedly test, in the groove of test substrate formed gate dielectric layer than groove in epitaxial substrate in formed gate medium bed thickness.
Please refer to table 1,, be formed at the thickness of the gate dielectric layer of trenched side-wall and lower surface in the test substrate for adopting identical thermal oxidation technology, and the test result table of comparisons of thickness that is formed at the gate dielectric layer of interior trenched side-wall of epitaxial substrate and lower surface.
Table 1
| Substrate | Test 1 (dust) | Test 2 (dusts) | Test 3 (dusts) |
| Test substrate | 937 | 937 | 937 |
| Epitaxial substrate | 714 | 718 | 716 |
Can know by table 1; If be employed in the technological parameter that forms gate dielectric layer in the test substrate, in the groove of outer substrate, form gate dielectric layer, can cause the thickness of formed gate dielectric layer thin excessively; Can't reach technical indicator, thereby formed transistor yield is descended.
In order to address the above problem; Inventor of the present invention is through further research; Form second groove in the Cutting Road district between the test substrate device region; And the crystal orientation of said second trenched side-wall is with respect to the crystal orientation deflection miter angle of test substrate device region internal channel sidewall, and the sidewall of formed second groove and the crystal face of bottom are identical with the crystal face of sidewall and bottom of groove in being formed at the epitaxial substrate device region, thus the covalent bond density of the sidewall of formed second groove and lower surface; With the groove that is formed in the epitaxial substrate device region, the covalent bond density of its sidewall and lower surface is identical; Therefore the technology that in said second groove, forms oxide layer can be applied in the device region groove of epitaxial substrate, form oxide layer, and the oxidated layer thickness that is formed in the epitaxial substrate device region groove is consistent with the oxidated layer thickness in second groove; The said oxide layer that is formed in the epitaxial substrate device region groove is used for the gate dielectric layer as trench transistor, can reach the purpose of accurate control trench transistor gate dielectric layer, makes the stable performance of formed trench transistor.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 7 is the schematic flow sheet of method of the control trench transistor gate dielectric layer thickness of the embodiment of the invention, comprises step:
Step S101 provides test substrate, and said test substrate has some device regions, and said adjacent devices has the Cutting Road district between the district, and the edge of said test substrate has the wafer notch, and said test substrate surface has first photoresist layer;
Step S102; With said first photoresist layer is the said test substrate of mask etching; In the device region of said test substrate, form some first grooves that are parallel to each other, in the Cutting Road of said test substrate, form some second grooves that are parallel to each other, the crystal orientation of said second trenched side-wall is with respect to the crystal orientation deflection miter angle of said first trenched side-wall; When the shape of said first groove reaches preset shape, obtain the technological parameter that forms said first groove and second groove;
Step S103 adopts thermal oxidation technology to form first oxide layer in the sidewall and the lower surface of said first groove, forms second oxide layer simultaneously in the sidewall and the lower surface of said second groove; Test said second thickness of oxide layer, when said second thickness of oxide layer reaches preset thickness, obtain the formation technological parameter of said second oxide layer;
Step S104; Epitaxial substrate is provided, and the edge of said epitaxial substrate has the wafer notch, and the crystal orientation of said epitaxial substrate wafer notch becomes miter angle with respect to the crystal orientation of test substrate wafer notch; Said epitaxial substrate has some device regions; Said adjacent devices has the Cutting Road district between the district, and said epitaxial substrate surface has second photoresist layer, and the shape of said second photoresist layer is identical with the shape of said first photoresist layer;
Step S105; Adopt the technological parameter that forms said first groove and second groove; With said second photoresist layer is the said epitaxial substrate of mask etching; In the device region of said epitaxial substrate, form some the 3rd grooves that are parallel to each other, in the Cutting Road district of said epitaxial substrate, form some the 4th grooves that are parallel to each other;
Step S106; Adopt thermal oxidation technology to form the 3rd oxide layer in the sidewall and the lower surface of said the 3rd groove; Sidewall and lower surface at said the 4th groove form the 4th oxide layer, and the parameter of said thermal oxidation technology is identical with the technological parameter of second oxide layer that forms preset thickness.
Below will combine accompanying drawing that the method for the control trench transistor gate dielectric layer thickness of the embodiment of the invention is described; Fig. 8 to Figure 10, Figure 13 to 15 are plan structure sketch mapes of process of the control trench transistor gate dielectric layer thickness of the embodiment of the invention; Figure 11 is the cross-sectional view of Figure 10 on AA ' direction; Figure 12 is the cross-sectional view of Figure 10 on BB ' direction; Figure 16 is the cross-sectional view of Figure 15 on CC ' direction, and Figure 17 is the cross-sectional view of Figure 15 on DD ' direction.
Please refer to Fig. 8; Test substrate 200 is provided, and said test substrate 200 has some device regions 201, has Cutting Road district 202 between the said adjacent devices district 201; Said test substrate 200 has wafer notch (not shown), and said test substrate 200 surfaces have first photoresist layer 203.
Said test substrate 200 is used to simulate the follow-up technological process that on epitaxial substrate, forms trench transistor; On said test substrate 200, form trench transistor and can reflect whether the technological process of being adopted is reasonable, and whether the shape of formed trench transistor, position and performance satisfy design standard; When after having formed the trench transistor that meets design standard on the said test substrate 200; With resulting technological process formal trench transistor that forms on epitaxial substrate; Thereby avoided the waste of epitaxial substrate, and improved the yield of formed trench transistor; Said device region 201 is used to form trench transistor and other semiconductor device, and said Cutting Road district 202 is used to divide device region 201, and the zone of after the manufacturing of accomplishing semiconductor device, cutting.
In the present embodiment, the material of said test substrate 200 is a silicon, and the crystal face on said test substrate 200 surfaces is (100); Said crystal face is that the silicon materials test substrate 200 of (100) is comparatively cheap, thereby can practice thrift cost; The crystal orientation of the wafer notch of said test substrate 200 is < 110 >; Because follow-up needs formally form the wafer notch crystal orientation of the epitaxial substrate of trench transistor, according to concrete technological requirement and different with said test substrate 200; In the present embodiment; The wafer notch crystal orientation of the epitaxial substrate of following adopted is < 100 >; Cause the crystal orientation deflection miter angle of the wafer notch direction of said test substrate 200 with respect to the wafer notch of said epitaxial substrate; Thereby make the follow-up crystal orientation that is formed at identical shaped its sidewall surfaces of groove of same position in test substrate 200 and the epitaxial substrate different, finally influence the result that said test substrate is used for the simulation process flow process.
The wafer notch of said test substrate 200 is to be positioned at said test substrate 200 edges; And cutting mouth perpendicular to said test substrate 200 surfaces; Be used for confirming the direction of said test substrate 200, and said test substrate can't be moved arbitrarily in each road technological process; In the present embodiment, the crystal orientation of said wafer notch is identical with the direction of diameter through said wafer notch.
Said first photoresist layer 203 exposes follow-up first groove of formation and the position of second groove of needing, and the formation technology of said first photoresist layer 203 is: at said test substrate 200 surface coated photoresist films, and dry said photoresist film; With first mask blank, said photoresist film is made public, make said photoresist film expose the follow-up correspondence position that is formed at first groove of device region 201, and the correspondence position that is formed at second groove in Cutting Road district 202.
When the figure of formed first photoresist layer 203 meets design standard, obtain being used to form the lithography layout of said first photoresist layer 203, and said lithography layout, uses in follow-up formation when being positioned at second photoresist layer on epitaxial substrate surface.
Please refer to Fig. 9; With said first photoresist layer 203 (like Fig. 7) is the said test substrate 200 of mask etching; In the device region 201 of said test substrate 200, form some first grooves 204 that are parallel to each other; In the Cutting Road district 202 of said test substrate 200, form some second grooves 205 that are parallel to each other; The crystal orientation of said second groove, 205 sidewalls when the shape of said first groove 204 reaches preset shape, obtains the technological parameter that forms said first groove 204 and second groove 205 with respect to the crystal orientation deflection miter angle of said first groove, 204 sidewalls.
Said preset shape is the shape of said first groove 204 when adhering to specification, and said preset shape is had nothing in common with each other according to the difference of designing requirement; In the present embodiment, when said first groove 204 met preset proterties, said first groove, 204 depth boundses were 0.8 ~ 2 micron, and the bottom of said first groove 204 is to the test substrate sunken inside, and the surface is slick and sly; When employing reaches the channel shaped that meets preset shape and becomes trench transistor, functional, and leakage current is less; In other embodiments, said first groove 204 can be adjusted the degree of depth according to concrete technology, and the shape of sidewall and bottom.
In the present embodiment, said etching technics is anisotropic dry etching, and said anisotropic dry etching, etching gas are the mist of chlorine, hydrogen bromide or chlorine and hydrogen bromide; Said each comprise to the dry etch process parameter: the flow of hydrogen bromide is 200 ~ 800sccm, and the flow of chlorine is 20 ~ 100sccm, and the flow of inert gas is 50 ~ 1000sccm, and the pressure of etching cavity is 2 ~ 200mTorr, and etch period is 15 ~ 60 seconds.
After the dry etch process of said anisotropic; Lower surface to formed first groove 204 and second groove 205 is carried out isotropic dry etch process; The bottom that makes said first groove 204 and second groove 205 is to test substrate 200 sunken insides, and the surface is slick and sly; Avoid the drift angle of formed first groove 204 and second groove, 205 bottoms to produce point effect and produce leakage current.
Write down when formed first groove 204 meets preset shape technological parameters such as the etching gas kind of said anisotropic dry etch process and isotropic dry etch process, each gas flow, etching cavity pressure and etch period; Use during the 3rd groove and the 4th groove of resulting technological parameter on follow-up formation epitaxial substrate.
Said second groove 205 is formed in the Cutting Road district 202; After forming four groove identical with shape in the Cutting Road district of subsequent technique in epitaxial substrate with said second groove 205 positions; Said the 4th groove can be in the scribing process of accomplishing after semiconductor device is made; Cutting Road district with epitaxial substrate is excised, and therefore can not influence device performance.
In the present embodiment, the crystal orientation of said first groove, 204 sidewalls is parallel with the wafer notch crystal orientation of said test substrate 200, and therefore the crystal face of said first groove, 204 sidewall surfaces is (110); And follow-up the 3rd groove position that is formed in the epitaxial substrate device region is identical with said first groove 204 with shape, and therefore the crystal orientation of said the 3rd trenched side-wall is parallel with the wafer notch crystal orientation of epitaxial substrate, and the crystal orientation of its sidewall surfaces is (100); Cause the crystal face deflection miter angle of the crystal face of said test substrate 200 sidewalls with respect to said epitaxial substrate sidewall.
Because the crystal face of formed the 3rd trenched side-wall of subsequent technique; Crystal face deflection miter angle with respect to the sidewall of said test substrate 200 first grooves 204; When the sidewall crystal face of said second groove 205 during with respect to said first groove 204 also deflection miter angle; The sidewall of said second groove 205 and the crystal face of bottom are identical with the follow-up crystal face that is formed at the 3rd trenched side-wall and bottom in the substrate of outer; The surperficial covalent bond density of trenched side-wall and bottom is also identical, and wherein, the shape of said the 3rd groove is consistent with said first groove 204 with the position; Therefore; The oxidated layer thickness that adopts identical thermal oxidation technology in said second groove 205 and the 3rd groove, to form is identical; Thereby the follow-up technology that in said second groove 205, forms second oxide layer reach design standard thickness can be applied to follow-uply in the 3rd groove, form oxide layer.
Please refer to Figure 10, Figure 11 and Figure 12; Figure 11 is the cross-sectional view of Figure 10 on AA ' direction; Figure 12 is the cross-sectional view of Figure 10 on BB ' direction; Adopt thermal oxidation technology to form first oxide layer 206, form second oxide layer 207 in the sidewall and the lower surface of said second groove 205 in the sidewall and the lower surface of said first groove 204; Test the thickness of said second oxide layer 207, when the thickness of said second oxide layer 207 reaches preset thickness, obtain the formation technological parameter of said second oxide layer 207.
Said first oxide layer 206 is as the gate dielectric layer of the trench transistor that in said test substrate 200, forms, and said second oxide layer 207 is used to simulate the follow-up technology that in the 3rd groove of epitaxial substrate, forms the 3rd oxide layer.
Because the crystal face of said second groove, 205 sidewalls is with respect to the crystal face deflection miter angle of said first groove, 204 sidewalls; Therefore the atomic density of the sidewall of said second groove 205 and lower surface is different with said first groove 204; When adopting thermal oxidation technology to form first oxide layer 206 and second oxide layer 207; Said first oxide layer 206 is different with the oxidation rate of second oxide layer 207, and the oxidated layer thickness that the identical time forms is different.
Shown in figure 11, be the cross-sectional view that is positioned at said first groove 204 of device region 201, shown in figure 12, be the cross-sectional view that is positioned at said second groove 205 in Cutting Road district 202; In the present embodiment; Since the sidewall crystal face of said second groove 205 with respect to 204 deflections of said first groove miter angle, therefore the covalent bond density of said first groove, 204 sidewalls (110) crystal face is greater than the covalent bond density of said second groove, 205 sidewalls (100) crystal face; When first oxide layer 206 that adopts thermal oxidation technology to form simultaneously and second oxide layer 207; (110) speed of growth of the thermal oxide layer of crystal face is greater than (100) crystal face; Therefore; When adopting identical technological parameter to carry out the growth of gate oxide, the thickness of said first oxide layer 206 is greater than the thickness of said second oxide layer 207.
Because said second groove, 205 sidewalls and the bottom indices of crystallographic plane are identical with the follow-up indices of crystallographic plane that are formed at the 3rd interior trenched side-wall of epitaxial substrate and lower surface, so adopt identical thermal oxidation technology formed oxidated layer thickness in said second groove 205 and the 3rd groove identical; When said second oxide layer 207 meets the design standard thickness of gate dielectric layer; The parameters of resulting thermal oxidation technology is applied to the oxide layer in follow-up formation the 3rd groove; Formed oxide layer also can meet the thickness of design standard; Thereby guarantee the gate dielectric layer controllable thickness of trench transistor, the stable performance of formed trench transistor.
After forming said second oxide layer 207, test the thickness of said second oxide layer 207, the step of said test thickness is: said second oxide layer 207 is cut into slices; Section to 207 sections of said second oxide layer is measured, and obtains the thickness of said second oxide layer 207.
Said preset thickness is a trench transistor gate dielectric layer design standard thickness, and its thickness range is that 100 dusts are to 1000 dusts; The parameter of said thermal oxidation technology comprises: reacting gas, reaction time and reaction temperature; When the thickness of said second oxide layer 207 reaches said preset thickness, the parameters of the thermal oxidation technology that adopted at that time of record, and use during the oxide layer in subsequent technique forms the 3rd groove.
Need to prove; After forming said first oxide layer 206 and second oxide layer 207; In said first groove 204, form the first grid electrode layer (not shown) of filling full said first groove 204, in said second groove 205, form the second gate electrode layer (not shown) of filling full said second groove 205; The material of the said first grid electrode layer and second gate electrode layer is a polysilicon, obtains the technological parameter that forms the said first grid electrode layer and second gate electrode layer.
So far, the trench transistor that is formed at test substrate 200 completes, and has obtained in follow-up outer substrate, forming the complete process flow of the trench transistor that meets design standard.
Please refer to Figure 13; Epitaxial substrate 300 is provided; The edge of said epitaxial substrate 300 has wafer notch (not shown); The crystal orientation of the wafer notch of said epitaxial substrate 300 becomes miter angle with respect to the crystal orientation of test substrate 200 wafer notches, and said epitaxial substrate 300 has some device regions 301, has Cutting Road district 302 between the said adjacent devices district 301; Said epitaxial substrate 300 surfaces have second photoresist layer 303, and the shape of said second photoresist layer 303 is identical with the shape of said first photoresist layer 203.
Said outer substrate 300 is used to form trench transistor, the epitaxial loayer that said epitaxial substrate 300 comprises silicon substrate and is positioned at said surface of silicon; The formation method of said epitaxial substrate 300 is: adopt epitaxial deposition process to form epitaxial loayer in surface of silicon; Hence one can see that, and said epitaxial substrate 300 is comparatively expensive, is inappropriate in the technological process of simulation formation trench transistor and uses; In the present embodiment; The crystal orientation of epitaxial substrate 300 wafer notches becomes miter angle degree angle with respect to the crystal orientation of test substrate 200 wafer notches; Be < 100 >, thereby the 3rd trenched side-wall crystal face in the epitaxial substrate of follow-up formation 300 also becomes miter angle with respect to the sidewall crystal face of the first interior groove 204 of test substrate.
The wafer notch of said epitaxial substrate 300 is to be positioned at said epitaxial substrate 300 edges; And cutting mouth perpendicular to said epitaxial substrate 300 surfaces; Be used for confirming the direction of said epitaxial substrate 300, and said epitaxial substrate 300 can't be moved arbitrarily in each road technological process; The crystal orientation of said wafer notch is identical with diameter wafer direction through said wafer notch.
The formation technology of said second photoresist layer 303 is identical when forming said first photoresist layer 203; When said second photoresist layer 303 is made public; First mask blank when adopt forming said first photoresist layer 203; Thereby the correspondence position of the 3rd groove is identical with first groove 204 in the device region that said second photoresist layer 303 is exposed 301, and the position of the 4th groove is identical with said second groove 205 in the Cutting Road district 302 that is exposed.
Please refer to Figure 14; Adopt the technological parameter that forms said first groove 204 and second groove 205; With said second photoresist layer 303 is the said epitaxial substrate 300 of mask etching; In the device region 301 of said epitaxial substrate 300, form some the 3rd grooves 304 that are parallel to each other, 302 form some the 4th grooves 305 that are parallel to each other in the Cutting Road district of said epitaxial substrate 300.
The position of said the 3rd groove 304 and the 4th groove 305 and formation technology are identical with second groove 205 with said first groove 204; In the present embodiment, be mask with said second photoresist layer 303, adopt the said epitaxial substrate 300 of anisotropic dry etching, form said the 3rd groove 304 and the 4th groove 305; Isotropic dry etch process is being carried out in the bottom of said the 3rd groove 304 and the 4th groove 305, make the bottom to epitaxial substrate 300 sunken insides, and the surface is being slick and sly.
Said the 3rd groove 304 is used to form trench transistor; Said the 4th groove 305 is formed at Cutting Road district 302; And said Cutting Road district 302 is after the manufacturing of follow-up completion semiconductor device; Can in scribing process, be excised, therefore said the 4th groove 305 can be removed with Cutting Road district 302, thereby can the semiconductor device of final formation not impacted.
Please refer to Figure 15, Figure 16 and Figure 17; Figure 16 is the cross-sectional view of Figure 15 on CC ' direction; Figure 17 is the cross-sectional view of Figure 15 on DD ' direction; Adopt thermal oxidation technology to form the 3rd oxide layer 306 in sidewall and the lower surface of said the 3rd groove 304, form the 4th oxide layer 307 in the sidewall and the lower surface of said the 4th groove 305, the parameter of said thermal oxidation technology is identical with the technological parameter of second oxide layer 207 of formation preset thickness.
The thermal oxidation technology of said formation the 3rd oxide layer 306 and the 4th oxide layer 307 is identical with the technology of second oxide layer 207 that forms preset thickness; The thickness of formed the 3rd oxide layer 306 is preset thickness, therefore meets the designing requirement of the gate dielectric layer of trench transistor.
When the crystal orientation of said epitaxial substrate 300 wafer notches becomes miter angle with respect to the crystal orientation of said test substrate 200 wafer notches; And the crystal orientation of second groove, 205 sidewalls that is formed at test substrate 200 is during with respect to said first groove 204 also deflection miter angle; Because said the 3rd groove 304 is positioned at the position of said epitaxial substrate 300; And the position that is positioned at test substrate 200 with said first groove 204 is identical; Therefore the crystal orientation of said second groove, 205 sidewalls and lower surface is identical with the crystal orientation of said the 3rd groove 304 sidewalls and lower surface; Therefore, adopt second oxide layer, 207 thickness that identical thermal oxidation technology forms in said second groove 205 identical with the 3rd oxide layer 306 in the 3rd groove 304.
Because known thermal oxidation technology parameter when second groove 205 in, forming preset thickness, adopting the thickness of the 3rd oxide layer 306 that said technological parameter forms also is preset thickness; And said preset thickness meets the design standard of gate dielectric layer; Formed the 3rd oxide layer 306 is as the gate dielectric layer of trench transistor; Therefore the thickness of the final trench transistor gate dielectric layer that forms meets design standard, makes the stable performance of formed trench transistor.
Need to prove, after forming the 3rd oxide layer 306 and the 4th oxide layer 307, adopt the technology that forms the first grid electrode layer and second gate electrode layer, form the 3rd gate electrode layer and the 4th gate electrode layer of filling full said the 3rd groove 304 and the 4th groove 30
After the manufacturing of the semiconductor device in accomplishing device region 301, said epitaxial substrate 300 is cut, remove Cutting Road district 302 parts, said the 4th groove 305 and said the 4th oxide layer 307 are removed in above-mentioned scribing processes simultaneously.
In the method for the control trench transistor gate dielectric layer thickness of present embodiment; Form second groove of the crystal orientation of sidewall in the Cutting Road district of test substrate with respect to the first groove deflection miter angle; In said second groove, form second oxide layer that meets the gate dielectric layer thickness calibration, and in the 3rd groove in outer substrate devices district, form the 3rd oxide layer with the formation technology of said second oxide layer; Because said the 3rd groove is identical with the crystal face of said its sidewall of second groove and lower surface, the oxidated layer thickness that adopts identical thermal oxidation technology to form is identical; Therefore adjust the thickness of gate oxide in test substrate second groove through technological parameter; Make it reach requirement on devices; Thereby adopt formation the 3rd oxide layer of same technological parameter also to meet the gate dielectric layer thickness calibration, and said the 3rd oxide layer is as the gate dielectric layer of the trench transistor of required formation, thereby makes formed trench transistor gate medium Thickness Control more accurate; Testing cost is lower, and formed trench transistor is functional.
In sum, in the Cutting Road district of test substrate, form second groove, adopt thermal oxidation technology to form second oxide layer in the sidewall and the lower surface of said second groove, and when said second thickness of oxide layer reaches preset thickness, the recording process parameter; And in the 3rd groove, forming the 3rd oxide layer with said technological parameter, said the 3rd channel shaped is formed in the device region of epitaxial substrate, and position and shape are identical with position and the shape of first groove in the device region of test substrate; Because the crystal orientation of said epitaxial substrate wafer notch becomes miter angle with respect to the crystal orientation of test substrate wafer notch, therefore the crystal face of the 3rd trenched side-wall becomes miter angle with respect to the crystal face of said first trenched side-wall; When the crystal orientation of said second trenched side-wall during with respect to the crystal orientation deflection miter angle of said first trenched side-wall; The sidewall of said second groove is identical with the indices of crystallographic plane of the 3rd groove with the indices of crystallographic plane of lower surface; The covalent bond density of the sidewall of said second groove and the lower surface also covalent bond density with the sidewall of said the 3rd groove and lower surface is identical, and second oxide layer that therefore adopts identical thermal oxidation technology to form is identical with the 3rd oxidated layer thickness; When formation in second groove in test substrate reaches second oxide layer of preset thickness; Record thermal oxidation technology parameter at that time; And in the 3rd groove, forming the 3rd oxide layer with identical thermal oxidation technology, formed the 3rd oxide layer can reach preset thickness too; When the gate medium Thickness Control of said the 3rd oxide layer formed epitaxial substrate device region during and adjustment as the gate dielectric layer of trench transistor can be more accurately, cost is lower, the device performance of formation is better.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (17)
1. a method of controlling trench transistor gate dielectric layer thickness is characterized in that, comprising:
Test substrate is provided, and said test substrate has some device regions, and said adjacent devices has the Cutting Road district between the district, and the edge of said test substrate has the wafer notch;
In the device region of said test substrate, form some first grooves that are parallel to each other; In the Cutting Road district of said test substrate, form some second grooves that are parallel to each other simultaneously; The crystal orientation of said second trenched side-wall is with respect to the crystal orientation deflection miter angle of said first trenched side-wall; When the shape of said first groove reaches preset shape, obtain the technological parameter that forms said first groove;
Adopt thermal oxidation technology to form first oxide layer in the sidewall and the lower surface of said first groove; Sidewall and lower surface at said second groove form second oxide layer simultaneously; When said second thickness of oxide layer reaches preset thickness, obtain the formation technological parameter of said second oxide layer;
Epitaxial substrate is provided, and said epitaxial substrate has some device regions, and the edge of said epitaxial substrate has the wafer notch, and the crystal orientation of said epitaxial substrate wafer notch becomes miter angle with respect to the crystal orientation of test substrate wafer notch;
Adopt the technological parameter of said first groove, in the device region of said epitaxial substrate, form some the 3rd grooves that are parallel to each other;
Adopt thermal oxidation technology to form the 3rd oxide layer in the sidewall and the lower surface of said the 3rd groove, the parameter of said thermal oxidation technology is identical with the technological parameter of second oxide layer that forms preset thickness.
2. controlling the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that, is 100 dusts ~ 1000 dusts in said preset thickness.
3. control the method for trench transistor gate dielectric layer thickness according to claim 1; It is characterized in that; The preset shape of said first groove comprises: the degree of depth of said first groove is 0.8 ~ 2 micron, and the bottom of said first groove is slick and sly to test substrate sunken inside and surface.
4. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that, the formation step of said first groove and second groove is: with first mask blank, form first photoresist layer on the test substrate surface; With said first photoresist layer is mask, adopts etching technics in the device region of said test substrate, to form some first grooves that are parallel to each other simultaneously, in the Cutting Road district of said test substrate, forms some second grooves that are parallel to each other.
5. like the method for the said control trench transistor of claim 4 gate dielectric layer thickness, it is characterized in that the step of said the 3rd groove is:, form second photoresist layer at the extension substrate surface with first mask blank; With said second photoresist layer is mask, adopts etching technics in the device region of said epitaxial substrate, to form some the 3rd grooves that are parallel to each other; When forming said the 3rd groove, in the Cutting Road district of said epitaxial substrate, form some the 4th grooves that are parallel to each other.
6. like the method for the said control trench transistor of claim 4 gate dielectric layer thickness, it is characterized in that the technological parameter of said first groove comprises: the position of etching gas, etch period, etching bias voltage and said first groove.
7. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that, the technological parameter of second oxide layer of said formation preset thickness comprises: reacting gas, reaction time and reaction temperature.
8. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that, the step of obtaining said second oxidated layer thickness is: said second oxide layer is cut into slices; Section to said second oxide layer section is measured, and obtains said second thickness of oxide layer.
9. control the method for trench transistor gate dielectric layer thickness according to claim 1; It is characterized in that; Also comprise: after forming first oxide layer and second oxide layer; In said first groove, form the first grid electrode layer of filling full said first groove, in said second groove, form second gate electrode layer of filling full said second groove; Obtain forming the technological parameter of the said first grid electrode layer and second gate electrode layer.
10. like the method for the said control trench transistor of claim 9 gate dielectric layer thickness; It is characterized in that; To form the technological parameter of the said first grid electrode layer and second gate electrode layer, in said the 3rd groove, form the 3rd gate electrode layer of filling full said the 3rd groove.
11. the method like the said control trench transistor of claim 10 gate dielectric layer thickness is characterized in that the material of said first grid electrode layer, second gate electrode layer and the 3rd gate electrode layer is a polysilicon.
12. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that said epitaxial substrate also comprises: the Cutting Road district between the adjacent devices district.
13. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that said epitaxial substrate comprises: silicon substrate and the epitaxial loayer that is positioned at said surface of silicon.
14. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that said test substrate is a silicon substrate.
15. control the method for trench transistor gate dielectric layer thickness according to claim 1, it is characterized in that the crystal orientation of the wafer notch of said test substrate or epitaxial substrate is identical with diameter wafer direction through said wafer notch.
16. the method like the said control trench transistor of claim 15 gate dielectric layer thickness is characterized in that the notch crystal orientation of said epitaxial substrate is < 100 >.
17. the method like the said control trench transistor of claim 15 gate dielectric layer thickness is characterized in that the notch crystal orientation of said test substrate is < 110 >.
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