CN102768990B - Array substrate, and manufacturing method and display device of array substrate - Google Patents
Array substrate, and manufacturing method and display device of array substrate Download PDFInfo
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- CN102768990B CN102768990B CN201210265597.3A CN201210265597A CN102768990B CN 102768990 B CN102768990 B CN 102768990B CN 201210265597 A CN201210265597 A CN 201210265597A CN 102768990 B CN102768990 B CN 102768990B
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 113
- 238000009413 insulation Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 13
- 238000004380 ashing Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000002834 transmittance Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 44
- 239000010409 thin film Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000000155 melt Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- -1 as shown in Figure 2 Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
本发明公开了一种阵列基板制作方法，涉及显示技术领域，包括以下步骤：S1：在绝缘基板上形成包括栅极和栅线的图形；S2：在经过步骤S1之后的基板上形成栅绝缘层、有源层图形、源/漏极图形和数据线图形；S3：在经过步骤S2之后的基板上通过一次mask形成钝化层图形及像素电极图形，使所述像素电极图形与所述源/漏极图形接触，且覆盖在所述栅绝缘层上。还公开了一种阵列基板和显示装置。本发明的阵列基板制作方法仅使用三次mask，且只使用了一次灰度掩模技术，降低了成本，提高了良品率；本发明方法制作的阵列基板的像素电极直接位于栅极绝缘层之上，因此这种阵列基板结构有利于提高透过率。
The invention discloses a manufacturing method of an array substrate, which relates to the field of display technology, comprising the following steps: S1: forming a pattern including a gate and a gate line on an insulating substrate; S2: forming a gate insulating layer on the substrate after step S1 , active layer pattern, source/drain pattern and data line pattern; S3: Form passivation layer pattern and pixel electrode pattern through a mask on the substrate after step S2, make the pixel electrode pattern and the source/drain pattern The drain pattern contacts and covers the gate insulating layer. Also disclosed are an array substrate and a display device. The manufacturing method of the array substrate of the present invention only uses three masks and only one grayscale mask technology, which reduces the cost and improves the yield; the pixel electrode of the array substrate manufactured by the method of the present invention is directly located on the gate insulating layer , so this array substrate structure is beneficial to improve the transmittance.
Description
Technical field
The present invention relates to Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.
Background technology
Along with the use of liquid crystal is more and more extensive, therefore the production of liquid crystal panel competition is also growing more intense, and the reduction of cost is most important for Liquid crystal production.Current most TFT panel manufacture craft is 4mask or 5mask technology (masking process), need just can reach requirement by 4 times or 5 exposure imagings, and in the manufacture craft of TFT, spend maximum at present, what the required time was the longest is exactly the exposure of developing, and the number of times that therefore reduces mask is important in inhibiting for the reduction of cost.Traditional 3mask technique generally will be used twice technique of gray-scale mask, has certain help and reduce technique of gray-scale mask to enhancing productivity with product yields.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: how to reduce the process costs that array base palte is made.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of array substrate manufacturing method, comprise the following steps:
S1: form the figure that comprises grid and grid line on insulated substrate;
S2: form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure on the substrate through after step S1;
S3: form passivation layer figure and pixel electrode figure by a mask on the substrate through after step S2, described pixel electrode figure is contacted with described source/drain electrode figure, and cover on described gate insulation layer.
Wherein, described step S1 specifically comprises:
In described transparent insulation substrate, form one deck grid metallic film;
On described grid metallic film, apply photoresist, and by the photoresist in the exposure to photoresist, the reservation gate patterns region of developing;
Etch away the grid metallic film exposing and peel off remaining photoresist, forming the figure that comprises grid and grid line.
Wherein, described step S2 specifically comprises:
Comprise in formation on the substrate of figure of grid and grid line and form successively gate insulation layer film, active layer film and source-drain electrode metallic film, and apply photoresist on described source-drain electrode metallic film;
Adopt duotone mask plate to carry out exposure imaging to photoresist, retain source region and corresponding photoresist and photoresist corresponding to channel region in drain region, and the thickness of photoresist corresponding to channel region is less than photoresist corresponding to source region and drain region;
Etch away the source-drain electrode metallic film and the active layer film that expose, remove through ashing processing the photoresist that described channel region is corresponding, and metallic film formation raceway groove is leaked in etching source;
Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.
Wherein, described step S3 specifically comprises:
On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form passivation layer film, and apply the first photoresist on described passivation layer film;
The first photoresist is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, described photoresist not reserve area corresponding part drain region and pixel electrode area completely, the corresponding described photoresist of the complete reserve area of the described photoresist region beyond reserve area not completely;
By etching procedure by described photoresist completely not the described passivation layer film in reserve area remove, to expose part drain electrode and pixel electrode area;
Continue to form pixel electrode metallic film, and apply the second photoresist on described pixel electrode metallic film, and described the second photoresist is carried out to planarization, corresponding described grid, source/drain electrode, passivation layer top retain described the first photoresist, and the second photoresist thickness of described the first photoresist top is less than the thickness of described the second photoresist in corresponding described part drain region and described pixel electrode area;
Described the second photoresist is carried out to ashing processing, expose the pixel electrode metal level of described the first photoresist top, and retain described second photoresist of described part drain region and described pixel electrode area;
Remove the pixel electrode metal level of described the first photoresist top by etching technics;
Peel off described the first photoresist and described second photoresist of reservation, to form pixel electrode figure.
Wherein, described the second photoresist is the photoresist of viscosity within the scope of 2 ~ 4mpas.
Wherein, there is the photoresist planarization of mobility described in making by the mode of rotary plate.
The present invention also provides a kind of array base palte, comprise grid line, gate insulation layer, the data wire being formed on insulated substrate and be formed on the pixel cell between described grid line and data wire, described pixel cell comprises thin-film transistor and pixel electrode, described gate insulation layer is positioned on the grid of described grid line and described thin-film transistor, described pixel electrode is positioned on described gate insulation layer, and is connected with the drain electrode of described thin-film transistor.
Wherein, described array base palte also comprises the passivation layer being formed on described source/drain electrode and described data wire.
The present invention also provides a kind of display unit, comprises above-mentioned array base palte.
(3) beneficial effect
Array substrate manufacturing method of the present invention is by being merged into passivation layer and twice mask of pixel electrode once, reach the object that only uses three mask just can make array base palte, in whole manufacturing process, only use technique of gray-scale mask one time, reduced cost, improved yields simultaneously.Between traditional pixel electrode and glass substrate, have gate insulator and passivation layer two-layer, the pixel electrode of the array base palte that the inventive method is made is located immediately on gate insulator, and therefore this array base-plate structure is conducive to improve transmitance.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section that forms the substrate after grid and grid line in the array substrate manufacturing method of the embodiment of the present invention through mask etching for the first time;
Fig. 2 is the schematic cross-section that deposits successively the substrate after gate insulation layer film, active layer film and source-drain electrode metallic film on the substrate basis of Fig. 1;
Fig. 3 is the schematic cross-section that forms the substrate after gate insulation layer film, active layer, source/drain electrode and data wire on the substrate basis of Fig. 2 through mask for the second time etching;
Fig. 4 is deposit passivation layer film on the basis of the substrate of Fig. 3, and on passivation layer film, applies the schematic cross-section of the substrate after the first photoresist;
Fig. 5 is the schematic cross-section that forms the substrate after passivation layer figure on the basis of the substrate of Fig. 4 through mask for the third time etching;
Fig. 6 is pixel deposition electrode metal film on the basis of the substrate of Fig. 5, and on pixel electrode metallic film, applies the schematic cross-section of the substrate after its planarization second photoresist;
Fig. 7 is the schematic cross-section that ash melts the substrate after the second photoresist except pixel electrode area and pixel electrode figure and source/drain electrode figure contact area on the basis of the substrate of Fig. 6;
Fig. 8 is the schematic cross-section that etches away the substrate after the pixel electrode metallic film exposing on the basis of the substrate of Fig. 7;
Fig. 9 is the schematic cross-section that peels off the array base palte finally forming after remaining the first photoresist and the second photoresist on the basis of the substrate of Fig. 8;
Figure 10 is the floor map of the array base palte of the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
The array substrate manufacturing method flow process that the present embodiment provides is as follows:
Step 3.1 as shown in Figure 4, is passed through PECVD deposit passivation layer film, and on described passivation layer film, is applied the first photoresist 100 on the substrate that forms gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire.Adopt mask plate that the first photoresist 100 is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, as shown in Figure 5, wherein photoresist not reserve area corresponding part drain region F (drain electrode contact with pixel electrode region) and pixel electrode area G completely, the corresponding described photoresist of the complete reserve area of the photoresist region beyond reserve area not completely, i.e. passivation layer graphics field E.Etch away the passivation layer film that part drain region F and pixel electrode area G expose, as shown in Figure 5, make like this drain electrode of part drain region F and the gate insulation layer 3 of pixel electrode area G come out.After etching away the passivation layer film exposing, also retain first photoresist 100 of falling that do not develop simultaneously.
Step 3.2, through the substrate after step 3.1, be on the substrate shown in Fig. 5, to adopt sputtering sedimentation to plate one deck pixel electrode metallic film, and on pixel electrode metallic film, apply the second photoresist 200, the second photoresist 200 is the good photoresist of mobility, its viscosity, within the scope of 2 ~ 4mpas, can make the second photoresist 200 planarizations by rotation.Substrate after the second photoresist 200 planarizations as shown in Figure 6, due to step 3.1 hierarchical structure of the substrate of (Fig. 5) afterwards, after planarization, the second photoresist 200 thickness above the first photoresist 100 retaining are less than the thickness of the second photoresist 200 on corresponding part drain region F and pixel electrode area G.
Step 3.3, the second photoresist 200 is carried out to ashing processing, because the second photoresist 200 is greater than the thickness of the second photoresist 200 above the first photoresist 100 at the thickness of part drain region F and pixel electrode area G, therefore can make after ashing can reserve part drain region F and the second photoresist 200 of pixel electrode area G, ash melts the second photoresist 200 of the first photoresist 100 tops, the pixel electrode metallic film of the first photoresist 100 tops is come out, as shown in Figure 7, and the pixel electrode metallic film that exposes of etching, after etching as shown in Figure 8.
Step 3.4, peels off the first photoresist 100 and the second photoresist 200 that remain, to form passivation layer 6 and pixel electrode 7, finally forms array base palte, as shown in Figure 9.
When making passivation layer and pixel electrode in step 3, above-mentioned manufacturing process only uses mask one time, reduce mask one time with respect to prior art, together with the mask in step 1 and step 2, totally three mask, and only technique of gray-scale mask or partly adjust mask technique once in 2 in steps, reduce cost, improved yields.
As Fig. 9 and 10 (Fig. 9 be Figure 10 along A-A to profile) as shown in, for the array base palte that method according to described in embodiment 1 is made, this array base palte comprises: comprise grid line 8, gate insulation layer 3, the data wire 9 being formed on glass substrate 1 and be formed on grid line 8 and data wire 9 between pixel cell.Pixel cell comprises thin-film transistor and pixel electrode 7.Thin-film transistor also comprises grid 2, gate insulation layer 3, active layer 4, source/drain electrode 5.Gate insulation layer 3 is positioned on grid line 8 and grid 2, and pixel electrode 7 is directly covered on gate insulation layer 3, and is connected with the source/drain electrode 5 of thin-film transistor.Because pixel electrode 7 is directly covered on gate insulation layer 3, with respect to having gate insulator and passivation layer double-layer structure between traditional pixel electrode and glass substrate, be conducive to improve transmitance.
The present invention also provides a kind of display unit, and this display unit comprises the array base palte of above-described embodiment 2.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer.
Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (5)
1. an array substrate manufacturing method, is characterized in that, comprises the following steps:
S1: form the figure that comprises grid and grid line on insulated substrate;
S2: form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure on the substrate through after step S1;
S3: form passivation layer figure and pixel electrode figure by a mask on the substrate through after step S2, described pixel electrode figure is contacted with described source/drain electrode figure, and cover on described gate insulation layer;
Wherein, described step S3 specifically comprises:
On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form passivation layer film, and apply the first photoresist on described passivation layer film;
The first photoresist is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, described photoresist not reserve area corresponding part drain region and pixel electrode area completely, the corresponding described photoresist of the complete reserve area of the described photoresist region beyond reserve area not completely;
By etching procedure by described photoresist completely not the described passivation layer film in reserve area remove, to expose part drain electrode and pixel electrode area;
Continue to form pixel electrode metallic film, and apply the second photoresist on described pixel electrode metallic film, and described the second photoresist is carried out to planarization, corresponding described grid, source/drain electrode, passivation layer top retain described the first photoresist, and the second photoresist thickness of described the first photoresist top is less than the thickness of described the second photoresist in corresponding described part drain region and described pixel electrode area;
Described the second photoresist is carried out to ashing processing, expose the pixel electrode metal level of described the first photoresist top, and retain described second photoresist of described part drain region and described pixel electrode area;
Remove the pixel electrode metal level of described the first photoresist top by etching technics;
Peel off described the first photoresist and described second photoresist of reservation, to form pixel electrode figure.
2. array substrate manufacturing method as claimed in claim 1, is characterized in that, described step S1 specifically comprises:
On described insulated substrate, form one deck grid metallic film;
On described grid metallic film, apply photoresist, and by the photoresist in the exposure to photoresist, the reservation gate patterns region of developing;
Etch away the grid metallic film exposing and peel off remaining photoresist, forming the figure that comprises grid and grid line.
3. array substrate manufacturing method as claimed in claim 1, is characterized in that, described step S2 specifically comprises:
Comprise in formation on the substrate of figure of grid and grid line and form successively gate insulation layer film, active layer film and source-drain electrode metallic film, and apply photoresist on described source-drain electrode metallic film;
Adopt duotone mask plate to carry out exposure imaging to photoresist, retain source region and corresponding photoresist and photoresist corresponding to channel region in drain region, and the thickness of photoresist corresponding to channel region is less than photoresist corresponding to source region and drain region;
Etch away the source-drain electrode metallic film and the active layer film that expose, remove through ashing processing the photoresist that described channel region is corresponding, and metallic film formation raceway groove is leaked in etching source;
Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.
4. array substrate manufacturing method as claimed in claim 1, is characterized in that, described the second photoresist is the photoresist of viscosity within the scope of 2～4mpas.
5. array substrate manufacturing method as claimed in claim 4, is characterized in that, makes described the second photoresist planarization by the mode of rotary plate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210265597.3A CN102768990B (en) | 2012-07-27 | 2012-07-27 | Array substrate, and manufacturing method and display device of array substrate |
| PCT/CN2012/086776 WO2014015628A1 (en) | 2012-07-27 | 2012-12-17 | Array substrate, method for manufacturing same, and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210265597.3A CN102768990B (en) | 2012-07-27 | 2012-07-27 | Array substrate, and manufacturing method and display device of array substrate |
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| Publication Number | Publication Date |
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| CN102768990A CN102768990A (en) | 2012-11-07 |
| CN102768990B true CN102768990B (en) | 2014-06-25 |
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| WO (1) | WO2014015628A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102768990B (en) * | 2012-07-27 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device of array substrate |
| CN103034049A (en) * | 2012-12-13 | 2013-04-10 | 京东方科技集团股份有限公司 | Method for manufacturing metal wire and array substrate |
| CN103779232B (en) * | 2014-01-28 | 2016-08-17 | 北京京东方光电科技有限公司 | A kind of manufacture method of thin film transistor (TFT) |
| CN105206553A (en) * | 2015-08-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Etching device, etching method of electric conduction layer and preparation method of array substrate |
| CN105914183B (en) | 2016-06-22 | 2019-04-30 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT substrate |
| CN106847930A (en) * | 2017-04-01 | 2017-06-13 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and preparation method |
| CN108089377A (en) | 2018-02-13 | 2018-05-29 | 京东方科技集团股份有限公司 | A kind of display panel of horizontal electric field type, its production method and display device |
| CN109445193A (en) * | 2018-02-13 | 2019-03-08 | 京东方科技集团股份有限公司 | A kind of display panel of horizontal electric field type, its production method and display device |
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|---|---|---|---|---|
| US7056777B2 (en) * | 2002-04-17 | 2006-06-06 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate, manufacturing method thereof, and mask |
| CN101807584A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacture method thereof |
| CN102456620A (en) * | 2010-10-22 | 2012-05-16 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7279370B2 (en) * | 2003-10-11 | 2007-10-09 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate and method of fabricating the same |
| TW200602774A (en) * | 2004-07-06 | 2006-01-16 | Chunghwa Picture Tubes Ltd | Thin-film transistor manufacture method |
| CN100524781C (en) * | 2006-12-13 | 2009-08-05 | 北京京东方光电科技有限公司 | Pixel structure of a thin film transistor LCD and its making method |
| CN102034751B (en) * | 2009-09-24 | 2013-09-04 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacturing method thereof |
| CN102768990B (en) * | 2012-07-27 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device of array substrate |
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2012
- 2012-07-27 CN CN201210265597.3A patent/CN102768990B/en not_active Expired - Fee Related
- 2012-12-17 WO PCT/CN2012/086776 patent/WO2014015628A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7056777B2 (en) * | 2002-04-17 | 2006-06-06 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate, manufacturing method thereof, and mask |
| CN101807584A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacture method thereof |
| CN102456620A (en) * | 2010-10-22 | 2012-05-16 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
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| CN102768990A (en) | 2012-11-07 |
| WO2014015628A1 (en) | 2014-01-30 |
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