CN102761793B - Matrix eID bus circuit - Google Patents
Matrix eID bus circuit Download PDFInfo
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- CN102761793B CN102761793B CN201210191044.8A CN201210191044A CN102761793B CN 102761793 B CN102761793 B CN 102761793B CN 201210191044 A CN201210191044 A CN 201210191044A CN 102761793 B CN102761793 B CN 102761793B
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Abstract
The invention closes a matrix eID bus circuit which comprises a control unit and a plurality of electric tag units, wherein data buses eID-1, eID-2,... and eID-M led out from the control unit are respectively connected with I/O ports of 1-M eID chips respectively on electric tag units from 1-N, so as to form a transverse bus frame, wherein the M as well as the N is an integer larger than 2; and control buses COM-1,COM-2... And COM-N led out form the control unit are respectively with grounded terminals of the 1-M eID chips respectively on electric tag units from 1-N, so as to form a longitudinal bus frame; and the transverse bus frame and the longitudinal bus frame together form the matrix eID bus circuit. According to the invention, the bus resource is saved, hundreds of eID chips can be accurately read at the same time, and the number of the eID chips on one bus is not limited.
Description
Technical field
The present invention relates to optical communication field, particularly relate to a kind of matrixing eID bus circuit.
Background technology
Due to FTTH (Fiber To The Home, Fiber to the home) extensive use, whole world ODN (Optical Distribution Network, optical distribution network) welcomes explosive growth, and the FTTH construction upsurge in global range has further promoted ODN market development.Because FTTH mainly adopts PON (Passive Optical Network, EPON) technology, it is by an OLT (Optical Line Tterminal, optical line terminal) along separate routes to tens of thousands of ONU up to a hundred (Optical Network Unit, optical network unit), this need to carry out distribution scheduled maintenance management with regard to the fibre circuit that makes the user side of ODN net produce magnanimity.
Early stage lightguide cable link is substantially all point to point line, management is relatively easy, the ODN network that is FTTH service is the circuit of point-to-multipoint, continue to continue to use at present can only manual identified character label carry out optical fiber distributing management, its maintenance workload and management difficulty will significantly rise.Add the EPON characteristic of PON technology one-to-many, this just makes on an optical branch network, and user can arbitrarily be linked into and on any one branch road, carry out normal signal transmission, and is not the perception of network manager institute.This characteristic declines to a great extent the manageability of ODN.The leak of labor management will make network data occur not consistent mistake with real network situation, and this will bring a lot of difficulties to follow-up network operation work.
For addressing this problem, there is the light distribution administrative skill of intelligent ODN, it is taking eID (electronic tag) as basis, give an eID chip with global unique coding to each fiber active linker, the mode of utilizing electronics automatically to gather manages optical fiber distributing, to stop the issuable mistake of labor management, and utilize computer networking technology to instruct network operation, thereby can in thickly dotted distributing frame adapter arrays, highlight out the port that need to operate rapidly, to reduce labour intensity.
Utilize existing monobus framework, when read-write eID chip, the number of chips that can connect in bus is limited, can only connect 3～5, and easily makes mistakes when read-write.When number of chips increases, existing monobus framework can not use, and does not reach expected effect.Due to the applied environment of ODN great majority in passive, therefore need to adopt a kind of simple effectively, low-power consumption, bus architecture cheaply, can identify the circuit of thousands of eID of hundreds of, set up a reliable intelligent ODN system.
Summary of the invention
The object of the invention is the deficiency in order to overcome above-mentioned background technology, provide a kind of simple effectively, low-power consumption, matrixing eID bus circuit cheaply, can either save bus resource, can read like clockwork again thousands of eID chips of hundreds of, error rate is 0, and in same bus unrestricted with the quantity of eID chip, be applicable to for forming reliable intelligent ODN system.
A kind of matrixing eID bus circuit provided by the invention, comprise control unit and some electronic tags unit, described control unit comprises CPU, electronic tag unit comprises some eID chips, data/address bus eID-1, eID-2 that control unit is drawn ... eID-M receives respectively electronic tag unit 1, electronic tag unit 2 ... the I/O port of 1st～M eID chip on electronic tag unit N, form horizontal data bus architecture, M, N are the integer that is greater than 2; Control bus COM-1, the COM-2～COM-N that control unit is drawn receives respectively electronic tag unit 1, electronic tag unit 2 ... the earth terminal of 1st～M eID chip on electronic tag unit N, form longitudinal control bus framework, described horizontal data bus architecture and longitudinal control bus framework form matrixing eID bus circuit jointly.
In technique scheme, described control unit carries out timesharing control by data/address bus and the control bus of matrixing to each electronic tag unit.
In technique scheme, the process of described timesharing control is as follows: control unit is by being set to low by a level in control bus COM-1～COM-N, choose electronic tag unit, make the earth terminal ground connection of the eID chip in this electronic tag unit, control unit carries out read-write operation to the eID chip on this electronic tag unit respectively by data/address bus eID-1～eID-M; Meanwhile, the ground connection termination of eID chip of controlling other electronic tag unit is high, forbids that the eID chip of other electronic tag unit is worked simultaneously.
In technique scheme, the CPU of described control unit adopts software control, and the desired sequential of simulation eID chip, by the GPIO bus extender interface of CPU, directly connects the I/O port of eID chip, and data are carried out to read-write operation.
In technique scheme, described matrixing eID bus circuit also comprises CPLD or FPGA, the CPU of control unit is connected with CPLD/FPGA with control bus by data/address bus, address bus, CPU writes signal the related register of CPLD/FPGA, CPU carries out read-write operation to related register, pass through logical transition by CPLD/FPGA again, convert the required data-signal of eID chip to, be connected to the I/O port of eID chip.
In technique scheme, described matrixing eID bus circuit also comprises the driving chip or the field effect transistor that are connected with CPLD/FPGA, drive by increasing chip drives or field effect transistor, control the COM earth terminal of eID chip: in the time that control line CS-1～CS-N of CPU control CPLD/FPGA uprises level, the field effect transistor that conducting is corresponding, make it to be output as low level, corresponding control signal COM-1～COM-N step-down.
In technique scheme, described CPLD/FPGA CS-1～CS-N control line on be connected with pull down resistor.
In technique scheme, in unit, described electronic tag unit, the I/O port of each eID chip connects a single data bus, corresponding one by one with data/address bus eID-1～eID-M.
In technique scheme, the diode of a forward of the earth terminal of each eID chip serial connection in unit, described electronic tag unit, and by a reverse diode ground connection GND, to remove the interference to the chip of working of eID chip that in system, on same bus, other is not worked.
Compared with prior art, advantage of the present invention is as follows:
(1) the present invention can save bus resource, the timesharing control of data/address bus and control bus by this matrixing, reach with minimum bus resource (M bar data wire+N bar control line), read and write the eID number of chips (M × N) of maximum number.
(2) the present invention realizes the read-write operation of the eID chip to greater number by CPLD/FPGA Extended Capabilities Port, can read like clockwork thousands of eID chips of hundreds of, error rate is 0, and in same bus unrestricted with the quantity of eID chip, simple effectively, low-power consumption, low cost.
(3) the present invention increases pull down resistor R on CS-1～CS-N control line, and control signal is more stable, can control reliably the operating state of field effect transistor, and misoperation does not occur.
(4) the present invention is at the diode of a forward of earth terminal serial connection of eID chip, increase a reverse diode ground connection GND simultaneously, be conducive to remove the interference to the chip of working of eID chip that in system, on same bus, other is not worked, thereby make system reliably working.
Brief description of the drawings
Fig. 1 is the structured flowchart of matrixing eID bus circuit in the embodiment of the present invention.
Fig. 2 is the circuit diagram of control unit in the embodiment of the present invention.
Fig. 3 is the circuit diagram of electronic tag unit in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Shown in Figure 1, a kind of matrixing eID bus circuit that the embodiment of the present invention provides, comprise control unit and some electronic tags unit, control unit comprises CPU, electronic tag unit comprises some eID chips, data/address bus eID-1, eID-2 that control unit is drawn ... eID-M receives respectively electronic tag unit 1, electronic tag unit 2 ... I/O (the Input/Output of 1st～M eID chip on electronic tag unit N, input and output) port, formed one group of horizontal data bus architecture, M, N are the integer that is greater than 2.Control bus COM-1, the COM-2～COM-N that control unit is drawn receives respectively electronic tag unit 1, electronic tag unit 2 ... the earth terminal of 1st～M eID chip on electronic tag unit N, forms a longitudinal control bus framework.Horizontal data bus architecture and longitudinal control bus framework form matrixing eID bus circuit jointly.
Control unit is at a time by being set to level some in control signal COM-1～COM-N low, thereby choose this electronic tag unit, make the earth terminal ground connection of the eID chip in this electronic tag unit, control unit just can carry out read-write operation to the eID chip on this unit respectively by data/address bus eID-1～eID-M.Meanwhile, the ground connection termination of the eID chip of other electronic tag unit of control unit control is high, forbids that the eID chip of other electronic tag unit is worked simultaneously.Like this, the timesharing control of data/address bus and control bus by this matrixing, reaches with minimum bus resource (M bar data wire+N bar control line), reads and writes the eID number of chips (M × N) of maximum number.
Shown in Figure 2, control unit comprises CPU (Central Processing Unit, central processing unit), and this CPU can be simple single-chip microcomputer, can be also complicated cpu system.For the read-write of data, can there be two kinds of methods, method one is to adopt CPU software control, the desired sequential of simulation eID chip, by GPIO (the General Purpose Input Output of CPU, universal input/output, or bus extender) interface, directly connect the I/O port of eID chip; Method two is that CPU passes through data/address bus, address bus and control bus, with CPLD (Complex Programmable Logic Device, CPLD) or FPGA (Field-Programmable Gate Array, field programmable gate array) connect, write the related register of CPLD/FPGA by CPU, CPU only reads and writes related register.Pass through logical transition by CPLD/FPGA again, convert the required data-signal of eID chip to, be connected to the I/O port of eID chip.It is less that scheme one is applicable in system eID number of chips, the applied environment that the GPIO port number of CPU can satisfy the demands, it is more that scheme two is applicable in system eID number of chips, the inadequate applied environment of GPIO port number of CPU, realizes the read-write operation of the eID chip to greater number by CPLD/FPGA Extended Capabilities Port.
By the GPIO of CPU out, or by CPLD/FPGA control bus CS-1～CS-N out, general drive current is less, be not enough to drive the operating current of multiple eID chips.Therefore, drive by increasing chip drives or field effect transistor, control the COM earth terminal of eID chip.In the time that CPU control CS-1～CS-N uprises level, the field effect transistor that conducting is corresponding, makes it to be output as low level, thus corresponding control signal COM-1～COM-N step-down.Drive chip or field effect transistor model selection can according to below with the quantity of eID chip determine, number of chips is many, when the drive current that needs is larger, needs choosing output to drive larger.In order to make control signal more stable, need on CS-1～CS-N control line, increase pull down resistor R, so just can control reliably the operating state of field effect transistor, there is not misoperation.
Shown in Figure 3, in electronic tag unit, the I/O port of each eID chip connects a single data bus, and corresponding one by one with data/address bus eID-1～eID-M, number of chips M is the amount doesn't matter, is determined by real system.While controlling the COM earth terminal of each eID chip, need be at the diode of a forward of earth terminal serial connection of eID chip, simultaneously, need to increase a reverse diode ground connection GND, be conducive to like this to remove the interference to the chip of working of eID chip that in system, on same bus, other is not worked, thereby make system reliably working.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention comprises these changes and modification interior.The content not being described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (6)
1. a matrixing eID bus circuit, comprise control unit and N electronic tag unit, it is characterized in that: described control unit comprises CPU, each electronic tag unit comprises M electronic tag eID chip, control unit is drawn M bar data/address bus: eID-1, eID-2 ... eID-M and N bar control bus: COM-1, COM-2～COM-N, M, N are the integer that is greater than 2; EID-1 is connected to the I/O port of the 1st eID chip in each electronic tag unit, eID-2 is connected to the I/O port of the 2nd eID chip in each electronic tag unit, the rest may be inferred, eID-M is connected to the I/O port of M eID chip in each electronic tag unit, forms horizontal data bus architecture; COM-1 is connected to the earth terminal of all eID chips in the first electronic tag unit, COM-2 is connected to the earth terminal of all eID chips in the second electronic tag unit, the rest may be inferred, COM-N is connected to the earth terminal of all eID chips in N electronic tag unit, form longitudinal control bus framework, described horizontal data bus architecture and longitudinal control bus framework form matrixing eID bus circuit jointly; Described control unit carries out timesharing control by data/address bus and the control bus of matrixing to each electronic tag unit, the process of described timesharing control is as follows: control unit is by being set to low by a level in control bus COM-1～COM-N, choose electronic tag unit, make the earth terminal ground connection of the eID chip in this electronic tag unit, control unit carries out read-write operation to the eID chip on this electronic tag unit respectively by data/address bus eID-1～eID-M; Meanwhile, the ground connection termination of eID chip of controlling other electronic tag unit is high, forbids that the eID chip of other electronic tag unit is worked simultaneously.
2. a kind of matrixing eID bus circuit as claimed in claim 1, it is characterized in that: the CPU of described control unit adopts software control, the desired sequential of simulation eID chip, by universal input/output GPIO bus extender interface of CPU, the I/O port that directly connects eID chip, carries out read-write operation to data.
3. a kind of matrixing eID bus circuit as claimed in claim 1, it is characterized in that: described matrixing eID bus circuit also comprises complex programmable logic device (CPLD) or on-site programmable gate array FPGA, the CPU of control unit is connected with CPLD/FPGA with control bus by data/address bus, address bus, CPU writes signal the related register of CPLD/FPGA, CPU carries out read-write operation to related register, pass through logical transition by CPLD/FPGA again, convert the required data-signal of eID chip to, be connected to the I/O port of eID chip.
4. a kind of matrixing eID bus circuit as claimed in claim 3, it is characterized in that: described matrixing eID bus circuit also comprises the driving chip or the field effect transistor that are connected with CPLD/FPGA, drive by increasing chip drives or field effect transistor, control the COM earth terminal of eID chip: in the time that control line CS-1～CS-N of CPU control CPLD/FPGA uprises level, the field effect transistor that conducting is corresponding, make it to be output as low level, corresponding control bus COM-1～COM-N step-down.
5. a kind of matrixing eID bus circuit as claimed in claim 4, is characterized in that: on CS-1～CS-N control line of described CPLD/FPGA, be connected with pull down resistor.
6. a kind of matrixing eID bus circuit as claimed in claim 5, it is characterized in that: the diode of a forward of the earth terminal of each eID chip serial connection in described electronic tag unit, and by a reverse diode ground connection GND, to remove the interference to the chip of working of eID chip that in system, on same bus, other is not worked.
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| CN201210191044.8A CN102761793B (en) | 2012-06-12 | 2012-06-12 | Matrix eID bus circuit |
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| CN201210191044.8A CN102761793B (en) | 2012-06-12 | 2012-06-12 | Matrix eID bus circuit |
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| CN102761793B true CN102761793B (en) | 2014-10-29 |
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| US9323543B2 (en) * | 2013-01-04 | 2016-04-26 | Microsoft Technology Licensing, Llc | Capability based device driver framework |
| CN104268619B (en) * | 2014-09-03 | 2017-10-10 | 烽火通信科技股份有限公司 | A kind of electronic tag of sub-frame of system |
| CN104484301B (en) * | 2014-12-25 | 2017-08-11 | 南京因泰莱电器股份有限公司 | A kind of IO bus units based on FPGA with self-recognition function |
| CN105429835B (en) * | 2015-11-11 | 2018-11-06 | 南车株洲电力机车研究所有限公司 | A kind of local bus circuit based on FPGA |
| CN109829347B (en) * | 2019-02-02 | 2024-01-26 | 常州太平通讯科技有限公司 | Electronic tag reading system based on nested matrix and reading method thereof |
| CN110395146B (en) * | 2019-08-28 | 2024-09-20 | 中车大连机车车辆有限公司 | A ground power supply device, method, controller and storage medium for electric vehicles |
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